📚 A-Level AQA Computer Science: Computer Architecture Essentials | A-Level AQA 计算机：计算机体系结构 考点精讲
In A-Level AQA Computer Science, computer architecture is the foundation upon which all understanding of hardware and low-level software is built. You need to grasp how a processor executes instructions, how memory is organised, and how data flows between components. This guide condenses the key points into one clear, exam-ready resource.
在 A-Level AQA 计算机科学中，计算机体系结构是你理解所有硬件和底层软件的基础。你需要掌握处理器如何执行指令、存储器如何组织以及数据如何在组件之间流动。本指南将这些关键点浓缩为清晰、适合备考的资源。
1. The Von Neumann Architecture | 冯·诺依曼架构
The vast majority of modern computers are based on the stored-program concept proposed by John von Neumann. In this model, both instructions and data are held in the same main memory and share a single set of buses.
绝大多数现代计算机都基于约翰·冯·诺依曼提出的存储程序概念。在该模型中，指令和数据都保存在同一主存储器中，并共享一组总线。
The key components are a central processing unit (CPU), a memory unit that stores both programs and data, input/output devices, and the system buses that connect everything. The CPU fetches each instruction from memory, decodes it and executes it sequentially unless a branch occurs.
关键组件包括一个中央处理器（CPU）、存储程序和数据的存储器单元、输入/输出设备，以及连接所有部件的系统总线。除非发生分支，CPU 会依次从内存中取出每条指令、解码并执行。
An inherent problem is the “Von Neumann bottleneck”: because instructions and data share the same data bus, the CPU often has to wait while competing memory accesses occur, limiting speed.
一个固有问题就是“冯·诺依曼瓶颈”：由于指令和数据共享同一条数据总线，当发生竞争性的内存访问时，CPU 经常需要等待，从而限制了速度。
2. Harvard Architecture vs Von Neumann | 哈佛架构与冯·诺依曼架构对比
The Harvard architecture uses physically separate memories and buses for instructions and data. This allows the CPU to fetch an instruction and read/write data simultaneously, potentially doubling throughput.
哈佛架构为指令和数据使用物理上分离的存储器和总线。这使得 CPU 可以同时取出指令和读/写数据，理论上能使吞吐量翻倍。
In an AQA context, Harvard architecture is typically seen in microcontrollers and embedded systems where fixed program memory (ROM/Flash) is separated from variable data memory (RAM). It is less flexible for general-purpose computing because the split storage cannot be dynamically balanced.
在 AQA 考试中，哈佛架构通常出现在微控制器和嵌入式系统中，其固定的程序存储器（ROM/Flash）与可变的数据存储器（RAM）是分开的。它对通用计算而言灵活性较低，因为分割的存储无法动态平衡。
3. CPU Components in Detail | CPU 组件详解
The CPU is composed of several essential units. The Control Unit (CU) directs operations by sending control signals and managing the fetch-decode-execute cycle. The Arithmetic Logic Unit (ALU) performs arithmetic (add, subtract) and logical (AND, OR, NOT) operations.
CPU 由几个基本单元组成。控制单元（CU）通过发送控制信号并管理取指-解码-执行周期来指挥操作。算术逻辑单元（ALU）执行算术运算（加、减）和逻辑运算（与、或、非）。
A set of registers holds temporary data. The most important are: Program Counter (PC), which holds the address of the next instruction; Memory Address Register (MAR), holding the address to be read from or written to; Memory Data Register (MDR, also called MBR), which stores the actual data or instruction transferred; Current Instruction Register (CIR), holding the instruction being executed; and the Accumulator (ACC), where ALU results are temporarily stored.
一组寄存器用于保存临时数据。最重要的是：程序计数器（PC），存放下一条指令的地址；存储器地址寄存器（MAR），存放要读或写的地址；存储器数据寄存器（MDR，也称为 MBR），存储实际传输的数据或指令；当前指令寄存器（CIR），存放正在执行的指令；累加器（ACC），临时存储 ALU 的运算结果。
4. The Fetch-Decode-Execute Cycle | 取指—解码—执行周期
Every instruction passes through this fundamental cycle. During Fetch, the address in the PC is copied to the MAR, a read signal is sent to memory, the instruction is placed into the MDR, and then transferred to the CIR. The PC is incremented to point to the next instruction.
每条指令都会经过这个基本周期。在取指阶段，PC 中的地址被复制到 MAR，向内存发送读信号，指令被放入 MDR，然后传输到 CIR。PC 递增，指向下一条指令。
In Decode, the control unit interprets the bit pattern in the CIR. It identifies the opcode (what to do) and the operand(s) (what data or address to use).
在解码阶段，控制单元解释 CIR 中的位模式。它识别操作码（做什么）和操作数（用什么数据或地址）。
During Execute, the CU sends signals to the ALU or other components to carry out the operation. This could involve loading a value from memory into the accumulator, performing an addition, or writing a result back to RAM.
在执行阶段，CU 向 ALU 或其他组件发送信号以执行操作。这可能涉及从内存加载一个值到累加器、执行加法或将结果写回 RAM。
5. Factors Affecting Processor Performance | 影响处理器性能的因素
Three main factors determine how fast a CPU completes tasks. Clock speed, measured in Hertz, dictates the number of cycles per second. A higher clock speed means more FDE cycles can occur per second, but it also increases heat and power consumption.
三个主要因素决定了 CPU 完成任务的速度。时钟速度（以赫兹为单位）决定了每秒的周期数。更高的时钟速度意味着每秒可以发生更多的 FDE 周期，但同时会增加发热和功耗。
The number of cores is critical for multitasking. A dual-core or quad-core processor can execute multiple instruction streams truly simultaneously. However, software must be written to take advantage of parallel processing; otherwise the extra cores may sit idle.
核心数量对于多任务处理至关重要。双核或四核处理器可以真正同时执行多个指令流。但是，软件必须写为能利用并行处理，否则多余的核可能闲置。
Cache memory, a small amount of extremely fast SRAM located on or near the CPU, reduces the need to access slower main RAM. Modern CPUs have L1, L2 and often L3 cache levels. The larger and closer the cache, the higher the hit rate, drastically boosting performance.
高速缓存（cache）是位于 CPU 内部或附近的一小部分极快速的 SRAM，它减少了对较慢主存 RAM 的访问需求。现代 CPU 具有 L1、L2 且通常还有 L3 级缓存。缓存越大越靠近核心，命中率就越高，从而大幅提升性能。
6. Instruction Set and Addressing Modes | 指令集与寻址模式
An instruction set is the complete collection of machine language commands a processor can understand. In AQA, you focus on simple instructions such as LOAD, STORE, ADD, SUBTRACT, JUMP, and HALT, typically expressed in assembly-like mnemonics.
指令集是处理器能够理解的机器语言命令的完整集合。在 AQA 中，你主要关注简单指令，如 LOAD、STORE、ADD、SUBTRACT、JUMP 和 HALT，通常用类似汇编的助记符表示。
The operand can be addressed in several ways. In immediate addressing, the operand is the actual data value, e.g., LOAD #5 loads the number 5. In direct addressing, the operand is the memory address where the data is stored.
操作数可以通过几种方式寻址。在立即寻址中，操作数就是实际的数据值，例如 LOAD #5 加载数字 5。在直接寻址中，操作数是存储数据的内存地址。
Indirect addressing uses the operand as a pointer to find the real address, allowing for flexible data structures but requiring an extra memory access. Indexed addressing adds an index register to a base address, which is efficient for arrays.
间接寻址将操作数当作指针来找到真实地址，适合灵活的数据结构，但需要额外的内存访问。变址寻址将一个变址寄存器的值加到基地址上，对数组操作很高效。
7. Pipelining and its Challenges | 流水线及其挑战
Pipelining allows a processor to overlap the stages of the FDE cycle for different instructions. While one instruction is being decoded, the next can be fetched, and another can be executed, improving throughput without increasing clock speed.
流水线允许处理器为不同指令重叠执行 FDE 周期的各个阶段。当一条指令正在解码时，下一条可以开始取指，再下一条可以执行，从而在不提高时钟速度的情况下提升吞吐量。
However, pipelining introduces hazards. Data hazards occur when an instruction depends on the result of a previous one still in the pipeline. Control hazards arise from branch instructions, because the pipeline may have fetched the wrong instructions before the branch is resolved. The processor often flushes the pipeline, wasting cycles.
然而，流水线会引入冲突。当一条指令依赖于仍在流水线中的前一条指令的结果时，就会发生数据冲突。控制冲突由分支指令引起，因为在分支结果确定之前，流水线可能已经取入了错误的指令。处理器通常需要清空流水线，浪费了周期。
8. Memory Hierarchy | 存储层次结构
Computer systems use a memory hierarchy to balance speed, cost and capacity. Registers inside the CPU are the fastest but most limited storage. Next comes cache (SRAM), then main memory (DRAM), and finally secondary storage (hard drives, SSDs) which is slowest but provides massive, non-volatile space.
计算机系统采用存储层次结构来平衡速度、成本和容量。CPU 内部的寄存器是最快但容量最有限的存储器。其次是高速缓存（SRAM），然后是主存储器（DRAM），最后是辅助存储器（硬盘、SSD），后者最慢但提供大容量、非易失性空间。
The principle of locality is vital: temporal locality says recently accessed data is likely to be accessed again soon; spatial locality says data near recently accessed locations is likely to be needed. Cache algorithms exploit this to keep frequently used data in high-speed memory.
局部性原理至关重要：时间局部性是指最近访问过的数据可能很快会再次被访问；空间局部性是指与最近访问位置相邻的数据很可能被需要。缓存算法利用这一点将常用数据保留在高速存储器中。
9. I/O Controllers and Interrupts | 输入/输出控制器与中断
Peripherals connect to the system via I/O controllers, which manage the device-specific protocols and data transfer. The CPU does not talk directly to the hardware; it communicates with the controller’s registers, often via memory-mapped I/O, where device registers appear as if they were RAM addresses.
外设通过 I/O 控制器连接到系统，控制器管理设备特定的协议和数据传输。CPU 不直接与硬件对话，而是与控制器的寄存器通信，通常采用内存映射 I/O 的方式，即设备寄存器就像 RAM 地址一样出现。
Interrupts are signals sent to the processor by hardware or software to request immediate attention. When an interrupt occurs, the CPU finishes its current FDE cycle, saves its state (pushing contents of PC and registers onto the stack), and jumps to an Interrupt Service Routine (ISR). After servicing, it restores the state and resumes the original task.
中断是由硬件或软件发送给处理器的信号，用于请求立即处理。当中断发生时，CPU 完成当前的 FDE 周期，保存其状态（将 PC 和寄存器的内容压入栈），然后跳转到中断服务例程（ISR）。服务完成后，恢复状态并继续执行原任务。
10. System Buses | 系统总线
Buses are parallel sets of wires that transfer information between components. The address bus carries memory addresses from the CPU to memory or I/O controllers. It is unidirectional. The width of the address bus determines the maximum addressable memory (e.g., a 32-bit address bus can address 2³² memory locations).
总线是一组并行的导线，用于在组件之间传输信息。地址总线将内存地址从 CPU 传送到内存或 I/O 控制器，它是单向的。地址总线的宽度决定了最大可寻址内存（例如，32 位地址总线可以寻址 2³² 个内存单元）。
The data bus carries the actual data being transferred. It is bidirectional. A wider data bus can transfer more bits per clock tick, increasing bandwidth. The control bus consists of a collection of individual lines that transmit command and timing signals, such as Read, Write, Clock, Reset, and Interrupt Request.
数据总线传输实际数据，它是双向的。更宽的数据总线每个时钟周期可以传输更多位，从而增加带宽。控制总线由一组独立的线组成，用于传输命令和时序信号，如读、写、时钟、复位和中断请求。
11. Embedded and Specialised Systems | 嵌入式与专用系统
An embedded system is a computer built into a device to perform a dedicated function. Examples include washing machine controllers, engine management systems, and smart card chips. These systems often use Harvard architecture with firmware stored in ROM, optimised for low power and real-time operation.
嵌入式系统是内置于设备中执行特定功能的计算机。例子包括洗衣机控制器、发动机管理系统和智能卡芯片。这些系统通常采用哈佛架构，固件存储在 ROM 中，并针对低功耗和实时操作进行了优化。
AQA may ask you to compare general-purpose computers with embedded systems. The latter are stripped-down, with exactly the I/O ports needed for the task, limited memory, and no user-installable software. They are highly reliable and operate without user intervention once deployed.
AQA 可能会要求你比较通用计算机和嵌入式系统。后者是简化设计的，拥有任务所需的恰好 I/O 端口、有限的内存，并且不能由用户安装软件。它们具有高可靠性，部署后无需用户干预即可运行。
12. Common Exam Pitfalls and Tips | 常见考试陷阱与提示
When explaining the FDE cycle, do not forget to mention the increment of the program counter, and always clarify which register holds which data. Students often confuse MAR and MDR. MAR contains an address; MDR contains the data read from or to be written to that address.
在解释 FDE 周期时，不要忘记提及程序计数器的递增，并始终澄清哪个寄存器保存什么数据。学生常混淆 MAR 和 MDR。MAR 包含地址，MDR 包含从该地址读取或要写入该地址的数据。
In performance questions, a faster clock speed does not automatically mean a faster computer if the cache miss rate is high or the pipeline stalls often. Always link performance factors to their impact on the FDE cycle efficiency.
在性能问题中，如果缓存缺失率高或流水线经常停顿，更快的时钟速度并不自动意味着计算机更快。始终将性能因素与它们对 FDE 周期效率的影响联系起来。
Finally, when describing buses, use precise terminology. The address bus is one-way from CPU to other devices; the data bus is two-way; the control bus is a collection of individual signal wires. This precise wording earns marks.
最后，在描述总线时，请使用精确的术语。地址总线是从 CPU 到其他设备的单向通路；数据总线是双向的；控制总线是一组独立的信号线。这种精确的措辞能获得分数。
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