📚 A-Level OCR Computer Science: Computer Architecture Key Points | A-Level OCR 计算机：计算机体系结构 考点精讲
Computer architecture is the conceptual design and fundamental operational structure of a computer system. In OCR A-Level Computer Science, this topic explores how the Central Processing Unit (CPU) works, how instructions are executed, and how different architectural choices affect performance and functionality. Understanding these principles is essential for grasping how hardware and software interact at the lowest level.
计算机体系结构是计算机系统的概念设计和基本操作结构。在 OCR A-Level 计算机科学课程中，本主题探讨中央处理器 (CPU) 如何工作，指令如何执行，以及不同的架构选择如何影响性能和功能。理解这些原理对于掌握软硬件如何在最底层交互至关重要。
1. CPU Components & Their Functions | CPU 组件及其功能
The CPU consists of several key components, each playing a specific role in processing instructions. The Control Unit (CU) directs the operation of the processor by generating control signals that coordinate all parts of the computer. The Arithmetic Logic Unit (ALU) performs arithmetic and logical operations such as addition, subtraction, comparison, and bitwise logic.
CPU 由几个关键组件组成，每个组件在处理指令时都扮演着特定的角色。控制单元 (CU) 通过生成协调计算机各部分的控制信号来指挥处理器的操作。算术逻辑单元 (ALU) 执行算术和逻辑运算，例如加法、减法、比较和按位逻辑。
Registers are small, high-speed storage locations inside the CPU. The Program Counter (PC) holds the memory address of the next instruction to be fetched. The Memory Address Register (MAR) stores the address of the memory location currently being accessed, while the Memory Data Register (MDR) holds the data being transferred to or from memory. The Current Instruction Register (CIR) contains the current instruction being decoded or executed. The Accumulator (ACC) temporarily stores the results of ALU operations.
寄存器是 CPU 内部的小型高速存储位置。程序计数器 (PC) 保存下一条待取指令的内存地址。内存地址寄存器 (MAR) 存储当前正在访问的内存地址，而内存数据寄存器 (MDR) 保存正在传入或传出内存的数据。现行指令寄存器 (CIR) 包含正在译码或执行的当前指令。累加器 (ACC) 临时存储 ALU 运算的结果。
The system bus connects the CPU to memory and I/O devices. The address bus carries memory addresses from the CPU to memory or other devices; it is unidirectional. The data bus transmits data between the CPU, memory, and I/O devices; it is bidirectional. The control bus carries control signals such as read/write, interrupt requests, and clock signals.
系统总线将 CPU 连接到内存和 I/O 设备。地址总线将内存地址从 CPU 传输到内存或其他设备；它是单向的。数据总线在 CPU、内存和 I/O 设备之间传输数据；它是双向的。控制总线传输控制信号，如读/写、中断请求和时钟信号。
2. The Fetch-Decode-Execute Cycle | 取指—译码—执行周期
The Fetch-Decode-Execute (FDE) cycle is the basic operation cycle of a processor. It repeats continuously while the computer is running, processing one instruction at a time. In the fetch stage, the CPU retrieves an instruction from main memory. The address in the PC is copied to the MAR, a read signal is sent on the control bus, and the instruction is placed on the data bus into the MDR. The instruction is then copied to the CIR, and the PC is incremented to point to the next instruction.
取指—译码—执行 (FDE) 周期是处理器的基本操作周期。它在计算机运行时不断重复，每次处理一条指令。在取指阶段，CPU 从主内存中取出一条指令。PC 中的地址被复制到 MAR，控制总线上发送读信号，指令通过数据总线进入 MDR。然后指令被复制到 CIR，PC 递增以指向下一条指令。
During the decode stage, the Control Unit interprets the opcode part of the instruction stored in the CIR and sets up the necessary datapaths and control lines. The execute stage carries out the instruction. If it is an arithmetic operation, the ALU is activated; if it is a load or store, memory is accessed; if it is a branch, the PC may be updated with a new address. Once execution completes, the cycle restarts.
在译码阶段，控制单元解释存储在 CIR 中的指令的操作码部分，并设置必要的数据通路和控制线。执行阶段执行该指令。如果是算术运算，则激活 ALU；如果是加载或存储，则访问内存；如果是分支，则可能用新地址更新 PC。一旦执行完成，周期重新开始。
3. The Von Neumann Architecture | 冯·诺依曼架构
The Von Neumann architecture is a design model where both data and instructions are stored in a single, unified memory. This approach simplifies the design because there is only one set of address and data buses to manage. The CPU can treat instructions as data if required, which is used in some programming techniques, but it introduces the “Von Neumann bottleneck” — the performance limitation caused by the shared bus between instructions and data fetches.
冯·诺依曼架构是一种设计模型，其中数据和指令都存储在单一的、统一的内存中。这种方法简化了设计，因为只有一组地址和数据总线需要管理。如果必要，CPU 可以将指令视为数据，这在某些编程技术中会用到，但它引入了“冯·诺依曼瓶颈”——由指令和数据取指共享总线引起的性能限制。
In this architecture, instructions are fetched and executed in a sequential manner unless altered by a branch instruction. The program counter ensures sequential flow. Most general-purpose computers and microcontrollers use the Von Neumann architecture because of its cost-effectiveness and simplicity.
在这种架构中，除非被分支指令改变，指令是按顺序提取和执行的。程序计数器确保顺序流程。大多数通用计算机和微控制器使用冯·诺依曼架构，因为它成本效益高且简单。
4. Harvard Architecture | 哈佛架构
Harvard architecture separates the storage and signal pathways for instructions and data. It has physically distinct memory and buses for instructions and data, allowing the CPU to fetch an instruction and read or write data simultaneously. This parallelism can significantly increase performance, especially in real-time embedded systems and Digital Signal Processors (DSPs).
哈佛架构将指令和数据的存储和信号通路分开。它有物理上独立的指令内存和数据内存及总线，允许 CPU 同时取出一条指令并读取或写入数据。这种并行性可以显著提高性能，特别是在实时嵌入式系统和数字信号处理器 (DSP) 中。
A pure Harvard architecture has completely separate address spaces, which makes self-modifying code impossible. Modified Harvard architectures relax this restriction by providing pathways to treat instruction memory as read-only data or by using a unified address space but separate caches, as seen in many modern processors.
纯粹的哈佛架构具有完全独立的地址空间，这使得自修改代码成为不可能。修改后的哈佛架构通过提供途径将指令内存视为只读数据，或使用统一地址空间但分离的缓存来放宽此限制，这在许多现代处理器中可见。
5. Factors Affecting CPU Performance | 影响 CPU 性能的因素
Several factors determine how fast a CPU can execute programs. Clock speed, measured in Hertz, indicates how many cycles per second the CPU can perform. A higher clock speed generally means more instructions executed per unit time, but heat generation and power consumption increase.
有几个因素决定 CPU 执行程序的速度。时钟速度以赫兹为单位，表示 CPU 每秒可以执行多少个周期。更高的时钟速度通常意味着单位时间内执行更多的指令，但发热和功耗也会增加。
The number of processor cores is another crucial factor. A multi-core processor contains multiple independent processing units, enabling true parallel execution of tasks. However, software must be written to take advantage of multiple cores; not all tasks can be parallelized.
处理器核心数量是另一个关键因素。多核处理器包含多个独立的处理单元，能够真正并行执行任务。然而，软件必须写成能利用多核；并非所有任务都可以并行化。
Cache memory, a small amount of very fast memory located close to or on the CPU chip, stores frequently accessed data and instructions. Level 1 (L1) cache is the fastest and smallest, often split into instruction and data caches. Level 2 (L2) and Level 3 (L3) caches are larger but slower. Effective caching reduces the average time to access memory, mitigating the Von Neumann bottleneck.
高速缓存内存是位于 CPU 芯片附近或芯片上的少量极快内存，用于存储频繁访问的数据和指令。一级 (L1) 缓存最快且最小，通常分为指令缓存和数据缓存。二级 (L2) 和三级 (L3) 缓存更大但较慢。有效的缓存减少了平均内存访问时间，缓解了冯·诺依曼瓶颈。
6. Pipelining | 流水线技术
Pipelining is a technique that improves processor throughput by overlapping the execution of multiple instructions. An instruction is broken into stages — typically fetch, decode, execute, and sometimes memory access and write-back. While one instruction is being executed, the next can be decoded and another fetched simultaneously. This keeps all parts of the processor busy most of the time.
流水线是一种通过重叠多条指令的执行来提高处理器吞吐量的技术。一条指令被分解为多个阶段——典型的是取指、译码、执行，有时还包括内存访问和写回。当一条指令正在执行时，下一条可以同时译码，再下一条正在被取出。这使处理器的所有部件大部分时间都处于忙碌状态。
A key challenge in pipelining is handling pipeline hazards. Data hazards occur when an instruction depends on the result of a previous instruction that is not yet available. Control hazards arise from branch instructions, where the next instruction to fetch is unknown until the branch is resolved. Techniques such as operand forwarding, pipeline stalls, and branch prediction are used to mitigate these hazards and maintain smooth pipeline flow.
流水线的一个关键挑战是处理流水线冒险。数据冒险发生在一指令依赖于前一条指令的尚未可用的结果时。控制冒险由分支指令引起，在分支解决之前，下一条要取的指令是未知的。操作数转发、流水线停顿和分支预测等技术用于减轻这些冒险，维持流水线的顺畅流动。
7. CISC vs RISC Architectures | CISC 与 RISC 架构对比
CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer) represent two different design philosophies for the instruction set architecture (ISA). CISC processors have a large set of complex instructions that can perform multi-step operations in a single instruction. This reduces the number of instructions per program but requires more complex hardware and microcode decoding, often leading to variable-length instructions and longer execution times for certain instructions.
CISC (复杂指令集计算机) 和 RISC (精简指令集计算机) 代表了指令集架构 (ISA) 的两种不同设计理念。CISC 处理器拥有大量复杂指令，这些指令可以在单条指令中执行多步操作。这减少了每个程序的指令数量，但需要更复杂的硬件和微码译码，通常导致可变长度指令和某些指令较长的执行时间。
RISC processors use a simplified, highly optimized set of instructions that are typically of fixed length and execute at a rate of one instruction per clock cycle (after pipelining). The philosophy relies on efficient pipelining, a large set of general-purpose registers, and a load/store architecture where only specific instructions access memory. Compilers for RISC are more complex, as they must break down high-level operations into simple RISC instructions. Examples include ARM (used in most smartphones) and early MIPS processors.
RISC 处理器使用一组简化的、高度优化的指令，这些指令通常具有固定长度，并以每个时钟周期一条指令的速率执行（经过流水线后）。其理念依赖于高效的流水线技术、大量通用寄存器以及加载/存储架构，在这种架构中只有特定指令访问内存。RISC 的编译器更复杂，因为它们必须将高级操作分解为简单的 RISC 指令。例如 ARM（用于大多数智能手机）和早期的 MIPS 处理器。
| Feature | CISC | RISC |
|---|---|---|
| Instruction set | Large, complex | Small, simple |
| Instruction length | Variable | Fixed |
| Addressing modes | Many | Few |
| Pipelining | Difficult | Easy |
| Registers | Fewer, specialized | Many general-purpose |
| Memory access | Many instructions access memory | Load/store only |
现代处理器往往融合了两者的特点，例如 x86 架构在内部使用类 RISC 微操作，但外部呈现 CISC 指令集。
8. Multicore and Parallel Processors | 多核与并行处理器
Multicore processors integrate two or more independent processing cores on a single chip. Each core can independently execute instructions, allowing multiple threads or processes to run truly simultaneously. This is different from simultaneous multithreading (SMT), where a single core can execute multiple threads by switching between them very quickly, giving the illusion of parallelism.
多核处理器在单个芯片上集成两个或更多独立的处理核心。每个核心可以独立执行指令，允许多个线程或进程真正同时运行。这与同时多线程 (SMT) 不同，在 SMT 中，单个核心通过在多个线程之间快速切换来执行它们，给人以并行的错觉。
The benefit of multicore processing is linear performance scaling for parallelizable workloads, but it requires operating system support and software designed with concurrency in mind. Challenges include managing shared resources like cache coherency and memory bandwidth. Parallel processors extend this concept to a larger scale, such as in graphics processing and high-performance computing clusters.
多核处理的好处是对可并行化工作负载的线性性能扩展，但它需要操作系统的支持，并且软件在设计时要考虑并发性。挑战包括管理共享资源，如缓存一致性和内存带宽。并行处理器将这一概念扩展到更大规模，例如在图形处理和高性能计算集群中。
9. GPUs and Their Use | GPU 及其应用
A Graphics Processing Unit (GPU) is a specialized processor originally designed to accelerate image rendering. Modern GPUs are massively parallel, containing hundreds or thousands of smaller, simpler cores optimized for performing the same operation on multiple data elements simultaneously — a paradigm known as SIMD (Single Instruction, Multiple Data).
图形处理单元 (GPU) 是专门为加速图像渲染而设计的处理器。现代 GPU 是大规模并行的，包含数百或数千个较小、较简单的核心，这些核心经过优化，可以同时对多个数据元素执行相同的操作——这种范式称为 SIMD（单指令多数据）。
Due to their parallel architecture, GPUs are now widely used for general-purpose computing tasks beyond graphics, such as machine learning, scientific simulations, and cryptocurrency mining. GPGPU (General-Purpose computing on Graphics Processing Units) leverages APIs like CUDA and OpenCL to harness this power. In A-Level context, understanding that GPUs coexist with CPUs and handle parallel data processing while CPUs handle sequential control tasks is vital.
由于其并行架构，GPU 现在广泛用于图形之外的通用计算任务，如机器学习、科学模拟和加密货币挖矿。GPGPU（图形处理单元上的通用计算）利用 CUDA 和 OpenCL 等 API 来利用这种能力。在 A-Level 背景下，理解 GPU 与 CPU 共存，GPU 处理并行数据处理任务而 CPU 处理顺序控制任务是至关重要的。
10. Input/Output and Interrupts | 输入输出与中断
The CPU communicates with external devices through I/O controllers and ports. In memory-mapped I/O, the CPU treats I/O device registers as if they were memory addresses, using the same load and store instructions for communication. Port-mapped I/O uses a separate I/O address space with dedicated instructions, but this is less common in modern architectures.
CPU 通过 I/O 控制器和端口与外部设备通信。在内存映射 I/O 中，CPU 将 I/O 设备寄存器视为内存地址，使用相同的加载和存储指令进行通信。端口映射 I/O 使用单独的 I/O 地址空间和专用指令，但这在现代架构中不太常见。
Polling and interrupts are two methods for the CPU to detect I/O device status. Polling involves the CPU repeatedly checking the status register of a device, which wastes processing time. Interrupts provide a more efficient mechanism: when an I/O device needs attention, it sends an interrupt signal to the CPU. The CPU finishes its current instruction (or not, in the case of a non-maskable interrupt), saves its state, and jumps to an Interrupt Service Routine (ISR). After the ISR runs, the CPU returns to its original task. Interrupts can be prioritized, and multiple interrupt sources can share lines using daisy-chaining or vectored interrupts.
轮询和中断是 CPU 检测 I/O 设备状态的两种方法。轮询涉及 CPU 重复检查设备的状态寄存器，这会浪费处理时间。中断提供了更高效的机制：当 I/O 设备需要关注时，它向 CPU 发送中断信号。CPU 完成当前指令（或在不可屏蔽中断的情况下不必完成），保存其状态，并跳转到中断服务例程 (ISR)。ISR 运行后，CPU 返回原任务。中断可以划分优先级，多个中断源可以使用菊花链或向量中断方式共享线路。
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