📚 Computer Architecture: Core Concepts for IB WJEC | 计算机体系结构考点精讲
Computer architecture forms the bedrock of all modern computing systems. Whether you are studying IB Computer Science or the WJEC specification, a deep understanding of how a processor is structured, how instructions are executed, and how memory is organised is essential. This guide breaks down the key concepts, from the classic Von Neumann model to advanced pipelining and caching mechanisms, providing clear explanations that help you master the topic for your exams.
计算机体系结构是所有现代计算系统的基石。无论你学习的是IB计算机科学还是WJEC考试大纲，深入理解处理器的结构、指令如何执行以及存储器如何组织都至关重要。本指南分解了从经典冯·诺依曼模型到先进的流水线和缓存机制的核心概念，提供清晰的解释，帮助你掌握这一主题以应对考试。
1. The Von Neumann Model | 冯·诺依曼模型
The Von Neumann architecture describes a computer system where data and instructions are stored in the same memory unit. This stored-program concept means that a program can be changed simply by loading new instructions into memory, without rewiring the machine. A single set of buses (data, address, control) connects the CPU to memory and I/O devices, creating a sequential, step‑by‑step execution flow.
冯·诺依曼架构描述了一种数据和指令存储在同一存储器单元中的计算机系统。这种“存储程序”概念意味着只需将新指令加载到内存中即可更改程序，而无需重新布线机器。一组总线（数据总线、地址总线、控制总线）将CPU连接到存储器和I/O设备，从而形成顺序的、逐步执行的流程。
A fundamental bottleneck in this model is the “Von Neumann bottleneck”, caused by the shared bus between program memory and data memory. The processor often waits for instructions or data to be fetched from memory, limiting overall speed. Understanding this limitation motivates the need for cache memory and other performance enhancements discussed later.
该模型的一个根本瓶颈是“冯·诺依曼瓶颈”，它是由程序存储器和数据存储器之间的共享总线引起的。处理器经常需要等待从内存中取指令或数据，从而限制了整体速度。理解这一局限有助于我们认识到缓存和后面讨论的其他性能增强技术的必要性。
2. Central Processing Unit (CPU) Components | CPU核心组件
The CPU consists of several interdependent sub‑units. The Control Unit (CU) orchestrates the entire processor by directing the flow of data between the CPU and other devices, and by decoding instructions. The Arithmetic Logic Unit (ALU) performs all arithmetic (addition, subtraction) and logical (AND, OR, NOT) operations. A set of high‑speed storage locations called registers holds temporary data, instructions, and addresses.
CPU由几个相互依赖的子单元组成。控制单元（CU）通过指导CPU和其他设备之间的数据流以及对指令进行译码来协调整个处理器。算术逻辑单元（ALU）执行所有算术（加法、减法）和逻辑（与、或、非）运算。一组称为寄存器的高速存储单元保存临时数据、指令和地址。
In addition to the CU and ALU, modern CPUs contain a dedicated floating‑point unit (FPU) for decimal number computations and a memory management unit (MMU) that handles virtual memory translation. The exact arrangement of these components influences the processor’s instruction set and its overall efficiency.
除了CU和ALU，现代CPU还包含专用于小数计算的浮点运算单元（FPU）以及处理虚拟内存转换的内存管理单元（MMU）。这些组件的具体排列方式会影响处理器的指令集及其整体效率。
3. The Fetch-Decode-Execute Cycle | 取指-译码-执行周期
At the heart of every processor lies the continuous fetch‑decode‑execute cycle. During the fetch stage, the CPU copies the instruction stored at the address held in the Program Counter (PC) into the Current Instruction Register (CIR), then increments the PC to point to the next instruction. The decode stage sees the Control Unit interpreting the bit pattern in the CIR to determine which operation to perform and which operands are needed. Finally, the execute stage carries out the operation using the ALU, registers, and memory as required.
每个处理器的核心都离不开持续的取指-译码-执行周期。在取指阶段，CPU将程序计数器（PC）所存地址处的指令复制到当前指令寄存器（CIR）中，然后PC递增以指向下一条指令。在译码阶段，控制单元解释CIR中的位模式，以确定要执行的操作以及需要哪些操作数。最后，执行阶段根据需要利用ALU、寄存器和内存执行该操作。
A simple three‑step cycle can be extended to include interrupt checking, where the processor pauses to handle high‑priority events. In IB and WJEC exams, you may be asked to trace this cycle for a specific machine code sequence, identifying register changes at each step.
简单的三步周期可以扩展为包含中断检查，处理器会暂停以处理高优先级事件。在IB和WJEC考试中，可能会要求你针对特定的机器码序列跟踪这一周期，并识别每一步中寄存器的变化。
4. Registers and Their Roles | 寄存器及其作用
Registers are the fastest form of memory, located inside the CPU. Key dedicated registers include the Program Counter (PC) that holds the address of the next instruction; the Memory Address Register (MAR) that stores the address of the memory location to be read from or written to; the Memory Data Register (MDR) that holds the actual data or instruction fetched; and the Accumulator (ACC) where ALU results are temporarily kept.
寄存器是位于CPU内部的最快形式的存储器。关键专用寄存器包括：程序计数器（PC），存放要执行的下一条指令的地址；内存地址寄存器（MAR），存储要读取或写入的内存位置的地址；内存数据寄存器（MDR），存放实际取出的数据或指令；以及累加器（ACC），暂存ALU运算的结果。
General‑purpose registers allow the programmer (or compiler) to store intermediate values. In many architectures, the Status Register (SR) or flag register contains bits that indicate conditions such as zero, overflow, or carry. Understanding which register does what is vital for explaining data paths and instruction execution.
通用寄存器允许程序员（或编译器）存储中间值。在许多架构中，状态寄存器（SR）或标志寄存器包含指示零、溢出或进位等条件的位。理解每个寄存器的作用对于解释数据路径和指令执行至关重要。
5. The System Bus: Data, Address, and Control | 系统总线：数据、地址和控制
A system bus is a collection of parallel wires that transmits information between the CPU, memory, and peripherals. It is typically divided into three logical parts: the address bus carries memory addresses (unidirectional from CPU); the data bus carries the actual data (bidirectional); and the control bus transmits timing and command signals such as read/write, interrupt requests, and clock pulses.
系统总线是一组并行导线，在CPU、存储器和外设之间传输信息。它通常分为三个逻辑部分：地址总线传输内存地址（从CPU发出，单向）；数据总线传输实际数据（双向）；控制总线传输时序和命令信号，如读/写、中断请求和时钟脉冲。
The width of the address bus determines the maximum addressable memory locations (e.g., 32 lines can address 2³² different locations). Similarly, the width of the data bus affects how much data can be moved in one cycle, directly impacting performance. You should be able to calculate addressable memory space given bus sizes.
地址总线的宽度决定了可寻址的最大内存位置数（例如，32条线可寻址2³²个不同位置）。同样，数据总线的宽度影响每个周期可移动的数据量，直接影响性能。你应该能够根据总线大小计算可寻址的内存空间。
6. Cache Memory and Its Levels | 高速缓存及其层级
Cache is a small, extremely fast memory placed between the CPU and main RAM. It stores frequently accessed data and instructions, exploiting the principle of locality. Level 1 (L1) cache is usually split into instruction and data caches and is built directly onto the processor core, offering the lowest latency. Level 2 (L2) cache is larger but slightly slower, and sometimes Level 3 (L3) cache is shared among multiple cores.
高速缓存是一种置于CPU和主存之间的极小且极快的内存。它利用局部性原理存储经常访问的数据和指令。一级缓存（L1）通常分为指令缓存和数据缓存，直接构建在处理器内核上，延迟最低。二级缓存（L2）容量更大但稍慢，有时三级缓存（L3）在多个内核之间共享。
When the CPU finds required data in the cache (a cache hit), the access is very fast; a cache miss forces a slower access to main memory. Hit rate and miss penalty are key metrics. Understanding direct‑mapped, fully associative, and set‑associative mapping methods is often tested at advanced level.
当CPU在缓存中找到所需数据时（缓存命中），访问速度非常快；缓存缺失则强制对主存进行较慢的访问。命中率和缺失代价是关键指标。理解直接映射、全相联和组相联映射方法经常在高级考试中考查。
7. Instruction Set Architecture (ISA) | 指令集架构
The ISA defines the vocabulary of the machine: the set of instructions, their format, addressing modes, and the programmer‑visible registers. It acts as the interface between hardware and low‑level software. Instructions generally consist of an opcode (operation to perform) and one or more operands (data or addresses). Common addressing modes include immediate, direct, indirect, and indexed.
指令集架构（ISA）定义了机器的语言：指令集、指令格式、寻址方式以及程序员可见的寄存器。它是硬件和低级软件之间的接口。指令通常由操作码（要执行的操作）和一个或多个操作数（数据或地址）组成。常见的寻址方式包括立即寻址、直接寻址、间接寻址和变址寻址。
You will be required to interpret or write simple assembly segments. For instance, LDA 64 might load the accumulator with the contents of address 64, while ADD #5 adds the immediate value 5. Keep track of how flags in the Status Register change after each operation.
你将被要求解释或编写简单的汇编代码段。例如，LDA 64可能将地址64中的内容加载到累加器，而ADD #5将立即数5相加。注意每次操作后状态寄存器中的标志位如何变化。
8. Pipelining and Instruction-Level Parallelism | 流水线与指令级并行
Pipelining overlaps the execution of multiple instructions by dividing the fetch‑decode‑execute cycle into discrete stages. While one instruction is being decoded, the next can be fetched, and the previous one can be executed—much like an assembly line. This dramatically increases instruction throughput, though the latency for a single instruction remains the same.
流水线技术通过将取指-译码-执行周期划分为离散的阶段，来重叠执行多条指令。当一条指令正在译码时，下一条指令可以被取出，而前一条指令正在执行——很像一条装配线。这极大地提高了指令的吞吐量，尽管单条指令的延迟保持不变。
Pipeline hazards (data, control, structural) can stall the pipeline. Data hazards occur when an instruction depends on a previous instruction’s result that is still in the pipeline; control hazards arise from branch instructions; structural hazards happen when hardware resources are insufficient. Techniques like forwarding and branch prediction mitigate these issues.
流水线冒险（数据冒险、控制冒险、结构冒险）可能使流水线停顿。数据冒险发生在一条指令依赖于仍在流水线中的前一条指令的结果时；控制冒险由分支指令引起；结构冒险在硬件资源不足时发生。前递和分支预测等技术可以缓解这些问题。
9. Factors Affecting CPU Performance | 影响CPU性能的因素
Several hardware parameters determine how fast a CPU can execute programs. Clock speed, measured in GHz, dictates how many cycles per second the processor can complete. A higher clock rate generally means more instructions executed per second, but it also increases power consumption and heat. The number of cores allows genuine parallel processing; a multi‑core processor can run multiple threads simultaneously, boosting performance for multi‑tasking and parallelisable workloads.
有几个硬件参数决定了CPU执行程序的速度。时钟速度以GHz为单位，规定了处理器每秒可完成的周期数。较高的时钟频率通常意味着每秒可执行更多指令，但也会增加功耗和发热。核心数量允许真正的并行处理；多核处理器可以同时运行多个线程，从而提升多任务处理和可并行化工作负载的性能。
Other critical factors include the amount and speed of cache, the width of data and address buses, and the efficiency of the ISA. In exam questions, be prepared to discuss trade‑offs—for example, between clock speed and core count—and to interpret benchmark data using these metrics.
其他关键因素包括缓存的大小和速度、数据和地址总线的宽度，以及指令集架构的效率。在考题中，要准备好讨论权衡问题——例如时钟速度和核心数量之间的权衡——并运用这些指标解释基准测试数据。
10. Secondary Storage and the Memory Hierarchy | 辅助存储与存储层次
Memory hierarchy organises storage from fastest but smallest (registers, cache) to slowest but largest (hard disk drives, cloud storage). The goal is to give the illusion of a fast, vast memory. Secondary storage devices such as SSDs, HDDs, and optical disks retain data when power is off. In Von Neumann systems, programs must be loaded from secondary storage into RAM before execution.
存储层次将存储器组织为从最快但容量最小（寄存器、缓存）到最慢但容量最大（硬盘驱动器、云存储）的层级。其目标是营造快速且容量巨大的内存的假象。辅助存储设备（如SSD、HDD和光盘）在断电时仍能保存数据。在冯·诺依曼系统中，程序必须先从辅助存储加载到RAM中才能执行。
Virtual memory extends the apparent RAM capacity by using a section of secondary storage as an overflow area. The MMU translates virtual addresses to physical ones, managing pages or segments. Understanding latency differences (e.g., RAM access ~100 ns, SSD ~100 µs, HDD ~10 ms) helps explain why caching and memory hierarchy are so crucial.
虚拟内存通过将一部分辅助存储用作溢出区域，来扩展表观RAM容量。MMU将虚拟地址转换为物理地址，并管理页或段。了解延迟差异（例如，RAM访问约100纳秒，SSD约100微秒，HDD约10毫秒）有助于解释为什么缓存和存储层次如此关键。
11. Basic I/O and Interrupts | 基本输入输出与中断
Input/output (I/O) allows the processor to communicate with the outside world. In memory‑mapped I/O, devices appear as if they are memory locations, simplifying the interface. Isolated I/O uses special instructions to access device ports. Both approaches enable data transfer, but they differ in how addresses are decoded.
输入/输出（I/O）使处理器能够与外界通信。在内存映射I/O中，设备表现得就像内存位置一样，简化了接口。独立I/O则使用专门指令访问设备端口。两种方法都能实现数据传输，但它们在地址解码的方式上有所不同。
An interrupt is a signal that causes the processor to pause its current task, save its state, and jump to an interrupt service routine (ISR). Interrupts improve efficiency by allowing the CPU to respond promptly to external events (keyboard press, disk ready) without constantly polling devices. Priority levels ensure critical tasks are handled first.
中断是一种信号，它使处理器暂停当前任务、保存其状态，并跳转到中断服务程序（ISR）。中断通过允许CPU对外部事件（键盘按键、磁盘就绪）做出及时响应，而无需不断轮询设备，从而提高了效率。优先级确保关键任务首先被处理。
12. Comparing CISC and RISC Architectures | CISC与RISC架构比较
CISC (Complex Instruction Set Computer) processors, like those based on x86, feature a large set of instructions, many of which can perform multi‑step operations in a single command. They often use variable‑length instructions and rely heavily on microcode. RISC (Reduced Instruction Set Computer) architectures, such as ARM, use a small, highly optimised set of instructions, typically fixed‑length, designed for efficient pipelining. Each approach has its own philosophy.
CISC（复杂指令集计算机）处理器，如基于x86架构的处理器，具有庞大的指令集，其中许多指令可在单个命令中执行多步操作。它们通常使用可变长度指令，并严重依赖微码。RISC（精简指令集计算机）架构，如ARM，使用小型、高度优化的指令集，通常为定长设计，旨在实现高效流水线。每种方法都有自己的理念。
With CISC, compiled programs tend to be shorter but at the cost of variable execution time. RISC simplifies the hardware control unit, allowing more registers and easier pipelining, but the compiler must generate longer code. Modern processors often blend ideas from both: they employ RISC‑like cores while retaining a CISC instruction set for compatibility.
使用CISC，编译后的程序往往更短，但代价是执行时间可变。RISC简化了硬件控制单元，允许更多寄存器和更轻松的流水线设计，但编译器必须生成更长的代码。现代处理器通常融合了两者的思想：它们采用类似RISC的内核，同时保留CISC指令集以实现兼容。
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