📚 IB Edexcel Computer Science: Computer Architecture Key Study Points | IB Edexcel 计算机：计算机体系结构考点精讲
Computer architecture forms the backbone of both IB and Edexcel Computer Science syllabuses, covering the fundamental design and operation of a computer system. From the classic Von Neumann model to modern pipelining and cache hierarchies, a deep understanding of these concepts is essential for top marks in exams. This article breaks down every critical examination point with paired English and Chinese explanations, ensuring clarity and retention.
计算机体系结构是 IB 和 Edexcel 计算机科学课程的核心，涵盖计算机系统的基本设计和运行原理。从经典的冯·诺依曼模型到现代流水线和缓存层次，深入理解这些概念对于在考试中取得高分至关重要。本文以中英双语对照的方式，逐点剖析每一个重要考点，确保清晰易懂且便于记忆。
1. Von Neumann Architecture | 冯·诺依曼架构
Von Neumann architecture is a design model in which program instructions and data share the same memory space and are accessed via a single set of buses. It is the foundation of almost all modern computers.
冯·诺依曼架构是一种设计模型，其中程序指令和数据共享同一内存空间，并通过一组总线进行访问。它是几乎所有现代计算机的基础。
The architecture is built around the stored-program concept: both instructions and data are fetched from memory, decoded, and executed sequentially. The control unit (CU) manages the flow, while the arithmetic logic unit (ALU) performs calculations.
该架构围绕存储程序概念构建：指令和数据都从内存取出、译码并按顺序执行。控制单元 (CU) 管理流程，而 算术逻辑单元 (ALU) 执行计算。
A key characteristic is the “Von Neumann bottleneck,” where the single shared bus limits data transfer rate between CPU and memory, often constraining performance.
一个关键特征是“冯·诺依曼瓶颈”，即单一共享总线限制了 CPU 与内存之间的数据传输率，常常制约性能。
Registers such as the Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), and Accumulator (ACC) are indispensable for operation.
程序计数器 (PC)、内存地址寄存器 (MAR)、内存数据寄存器 (MDR) 和 累加器 (ACC) 等寄存器对运行不可或缺。
2. CPU Components | CPU 组件
The Control Unit (CU) directs all processor operations by generating control signals. It decodes instructions and coordinates data movement between registers, ALU, and memory.
控制单元 (CU) 通过生成控制信号指挥处理器的所有操作。它译码指令并协调寄存器、ALU 和内存之间的数据移动。
The Arithmetic Logic Unit (ALU) performs arithmetic (addition, subtraction) and logical (AND, OR, NOT) operations. It receives operands from registers and stores the result.
算术逻辑单元 (ALU) 执行算术运算（加、减）和逻辑运算（与、或、非）。它从寄存器接收操作数并存储结果。
Special-purpose registers include the Program Counter (PC) holding the address of the next instruction, the Instruction Register (IR) holding the current instruction, and the Stack Pointer (SP) pointing to the top of the stack.
专用寄存器包括保存下一条指令地址的 程序计数器 (PC)、保存当前指令的 指令寄存器 (IR) 以及指向栈顶的 栈指针 (SP)。
General-purpose registers allow the CPU to store temporary data, reducing the need to access slower main memory.
通用寄存器允许 CPU 存储临时数据，减少访问较慢主存的需求。
3. System Buses | 系统总线
A bus is a set of parallel wires that transmit data, addresses, and control signals. The three main buses are the data bus, address bus, and control bus.
总线是一组传输数据、地址和控制信号的并行导线。三种主要总线为数据总线、地址总线和控制总线。
The address bus carries the memory address from the CPU to memory. Its width (e.g., 32 bits) determines the maximum addressable memory (2³² locations). It is unidirectional.
地址总线将内存地址从 CPU 传送到内存。其宽度（如 32 位）决定了最大可寻址内存（2³² 个位置）。它是单向的。
The data bus transfers actual data between CPU, memory, and I/O devices. It is bidirectional and its width (e.g., 64 bits) affects data throughput.
数据总线在 CPU、内存和 I/O 设备间传输实际数据。它是双向的，其宽度（如 64 位）影响数据吞吐量。
The control bus carries control signals such as read/write, interrupt requests, and clock signals. Each line has a specific purpose.
控制总线传输控制信号，如读/写、中断请求和时钟信号。每条线路都有特定用途。
4. Fetch-Decode-Execute Cycle | 取指-译码-执行周期
The cycle is the fundamental sequence of steps the CPU repeats to process each instruction. It is often supplemented by a store result step in modern explanations.
该周期是 CPU 处理每条指令所重复的基本步骤序列。在现代解释中，常补充一个存储结果步骤。
Fetch: The address in the PC is copied to the MAR, a read signal is sent, and the instruction at that address is moved from memory to the MDR, then transferred to the IR. The PC is incremented.
取指：PC 中的地址被复制到 MAR，发送读信号，该地址处的指令从内存移入 MDR，然后转送到 IR。PC 自增。
Decode: The control unit interprets the instruction in the IR, splitting it into opcode and operand fields. It prepares necessary control signals for execution.
译码：控制单元解释 IR 中的指令，将其拆分为操作码和操作数字段。它为执行准备必要的控制信号。
Execute: The ALU performs the required operation. Data may be fetched from registers or memory, and the result is stored in the accumulator or a register.
执行：ALU 执行所需操作。数据可能从寄存器或内存中取出，结果存入累加器或寄存器中。
For load/store instructions, extra memory accesses may occur during the execute phase. The cycle then repeats.
对于加载/存储指令，执行阶段可能发生额外的内存访问。然后周期重复。
5. Memory Hierarchy and Cache | 存储层次与缓存
The memory hierarchy balances speed, cost, and capacity. From fastest to slowest: registers, cache (L1, L2, L3), main memory (RAM), and secondary storage (SSD/HDD).
存储层次在速度、成本和容量之间取得平衡。从最快到最慢依次为：寄存器、缓存（L1、L2、L3）、主存 (RAM) 和二级存储 (SSD/HDD)。
Cache memory is a small, high-speed memory placed between the CPU and main memory. It stores frequently accessed data and instructions to reduce the average access time.
高速缓存是介于 CPU 与主存之间的小型高速内存。它存储频繁访问的数据和指令，以减少平均访问时间。
The principle of locality of reference underpins caching. Temporal locality refers to reusing the same data soon; spatial locality refers to accessing nearby addresses.
访问局部性原则是缓存的基础。时间局部性指很快会重新使用相同数据；空间局部性指会访问邻近地址的数据。
Cache performance is measured by hit ratio (hits / total accesses) and average memory access time: T_avg = h × T_cache + (1-h) × T_memory.
缓存性能由命中率（命中次数 / 总访问次数）和平均内存访问时间衡量：T_avg = h × T_cache + (1-h) × T_memory。
6. Instruction Set Architecture (ISA) | 指令集架构
The ISA defines the set of instructions a processor can execute, including their format, addressing modes, and data types. It acts as the interface between hardware and low-level software.
指令集架构定义了处理器可执行的指令集合，包括其格式、寻址方式和数据类型。它充当硬件与底层软件之间的接口。
An instruction typically consists of an opcode (operation to perform) and one or more operands (data or addresses). Operands can be specified through different addressing modes.
一条指令通常由操作码（要执行的操作）和一个或多个操作数（数据或地址）组成。操作数可以通过不同寻址方式指定。
Common addressing modes: immediate (operand is a constant value), direct (operand is a memory address), indirect (address points to another address), and indexed (base address + offset).
常见寻址方式：立即寻址（操作数是常量值）、直接寻址（操作数是内存地址）、间接寻址（地址指向另一个地址）和变址寻址（基地址 + 偏移量）。
The number of operands per instruction can vary (0 to 3), influencing code density and hardware complexity. Examples include STORE, LOAD, ADD, and JUMP.
每条指令的操作数个数可变（0 至 3 个），影响代码密度和硬件复杂度。示例包括 STORE、LOAD、ADD 和 JUMP。
7. RISC versus CISC | RISC 与 CISC 比较
RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer) are two contrasting design philosophies for processors. Both appear in IB and Edexcel exams.
RISC（精简指令集计算机） 和 CISC（复杂指令集计算机） 是两种对立的处理器设计理念，两者均出现在 IB 和 Edexcel 考试中。
RISC processors use a small, highly optimised set of simple instructions, most of which execute in a single clock cycle. Load/store architecture is used, where only load and store instructions access memory.
RISC 处理器使用一组小型、高度优化的简单指令，其中大部分在一个时钟周期内执行。采用加载/存储架构，只有加载和存储指令访问内存。
CISC processors feature a large instruction set with complex, multi-cycle instructions. A single CISC instruction can perform several low-level operations, potentially reducing code size.
CISC 处理器具有庞大的指令集，包含复杂的多周期指令。一条 CISC 指令可以执行多个低层操作，可能减少代码占用空间。
| Feature | RISC | CISC |
| Instruction size | Fixed (e.g., 32 bits) | Variable |
| Execution time | Mainly 1 cycle per instruction | Multiple cycles |
| Hardware complexity | Lower, more registers | Higher, microprogrammed |
| Code density | Often lower (more instructions needed) | Higher |
Table: Key differences between RISC and CISC | 表：RISC 与 CISC 的主要区别
Modern processors often combine elements of both architectures, but the exam focuses on the pure theoretical models.
现代处理器常结合两种架构元素，但考试关注纯理论模型。
8. Pipelining | 流水线
Pipelining is a technique that overlaps the execution of multiple instructions. While one instruction is being decoded, another is being fetched, improving throughput without reducing the latency of a single instruction.
流水线是一种重叠执行多条指令的技术。当一条指令被译码时，另一条指令正在取指，从而在不减少单条指令延迟的情况下提高吞吐量。
An ideal k-stage pipeline can approach a k-fold speedup, but pipeline hazards prevent this ideal. Hazards are classified as structural, data, and control.
理想的 k 级流水线可获得接近 k 倍的加速，但流水线冒险阻碍了这种理想。冒险分为结构冒险、数据冒险和控制冒险。
Structural hazards occur when hardware resources are insufficient to support all concurrent stages (e.g., a single memory port for both fetch and data access).
结构冒险发生在硬件资源不足以支持所有并发阶段时（例如，取指和数据访问共用单一内存端口）。
Data hazards arise when an instruction depends on the result of a previous instruction that is not yet completed. Forwarding (bypassing) or stall insertion can resolve them.
数据冒险发生在某条指令依赖的前一条指令结果尚未完成时。转发（旁路）或插入暂停可以解决。
Control hazards happen with branch instructions: the CPU must decide which instruction to fetch next before knowing the branch outcome. Branch prediction and flushing are used.
控制冒险发生在分支指令时：CPU 必须在知晓分支结果前决定取哪条指令。使用分支预测和清空流水线来处理。
9. Interrupts and Exceptions | 中断与异常
An interrupt is a signal from hardware or software that causes the CPU to pause its current task and execute an Interrupt Service Routine (ISR). After the ISR, the CPU resumes the original task.
中断是由硬件或软件发出的信号，使 CPU 暂停当前任务并执行中断服务程序 (ISR)。ISR 执行完毕后，CPU 恢复原任务。
Interrupts can be maskable (can be ignored) or non-maskable (must be handled). The interrupt controller prioritises multiple requests and delivers the vector to the CPU.
中断可以是可屏蔽的（可以被忽略）或不可屏蔽的（必须处理）。中断控制器对多个请求进行优先级排序，并将中断向量传递给 CPU。
The CPU uses an interrupt vector table stored in memory to map each interrupt type to the address of its ISR. Context saving (registers pushed onto the stack) occurs before the ISR.
CPU 使用存储在内存中的中断向量表将每种中断类型映射到其 ISR 的地址。在执行 ISR 之前，会进行上下文保存（寄存器压入栈中）。
Exceptions are events generated internally by the CPU, such as division by zero or page faults. They are handled similarly to interrupts but are synchronous to the instruction stream.
异常是由 CPU 内部产生的事件，如除以零或缺页。它们的处理方式与中断类似，但与指令流同步。
10. Direct Memory Access (DMA) | 直接存储器访问
DMA allows certain hardware subsystems to access main memory independently of the CPU, significantly speeding up bulk data transfers (e.g., disk reads).
DMA 允许某些硬件子系统独立于 CPU 访问主存，极大加速批量数据传输（如磁盘读取）。
A DMA controller takes ownership of the buses after receiving permission from the CPU. During the transfer, the CPU is free to perform other tasks, but may be stalled if it needs the bus.
DMA 控制器在获得 CPU 许可后接管总线。在传输期间，CPU 可以执行其他任务，但如果需要使用总线则可能被暂停。
DMA uses cycle stealing where the DMA controller seizes a bus cycle from the CPU to move data, causing minimal disruption to CPU execution.
DMA 使用周期窃取技术，即 DMA 控制器从 CPU 夺取一个总线周期来移动数据，从而对 CPU 执行造成的干扰最小。
Once the transfer is complete, the DMA controller sends an interrupt to the CPU, signalling that the data is ready.
传输完成后，DMA 控制器向 CPU 发出中断，通知数据已就绪。
11. Performance Metrics | 性能指标
Key performance metrics include clock speed (f, in Hz), Cycles Per Instruction (CPI), and the total instruction count (I) of a program.
关键性能指标包括时钟频率（f，单位为 Hz）、每条指令周期数 (CPI) 以及程序的总指令数 (I)。
CPU Execution Time (T) = I × CPI / f
CPU 执行时间 (T) = I × CPI / f
To improve performance, designers can lower CPI (e.g., via pipelining), reduce instruction count (compiler optimisation), or increase clock frequency (limited by power dissipation).
为提升性能，设计者可以降低 CPI（如通过流水线）、减少指令数（编译器优化）或提高时钟频率（受功耗限制）。
MIPS (Million Instructions Per Second) and FLOPS (Floating-Point Operations Per Second) are common crude performance measures but can be misleading when comparing different ISAs.
MIPS（每秒百万条指令）和 FLOPS（每秒浮点运算次数）是常见的粗略性能度量，但在比较不同指令集时可能具有误导性。
Benchmarks such as SPECint and SPECfp test real workloads to provide a more reliable performance comparison.
SPECint 和 SPECfp 等基准测试以实际工作负载进行测试，可提供更可靠的性能比较。
12. Multi-core and Parallel Processing | 多核与并行处理
A multi-core processor integrates two or more independent cores on a single chip, enabling true parallel execution of threads. This increases overall throughput for multi-threaded applications.
多核处理器在单个芯片上集成两个或更多独立核心，可实现线程的真正并行执行。这为多线程应用程序提高了总体吞吐量。
Parallelism can be instruction-level (ILP), achieved within a single core via pipelining and superscalar design, or thread-level (TLP), achieved with multiple cores.
并行性可以是指令级并行 (ILP)（在单核内通过流水线和超标量设计实现），也可以是线程级并行 (TLP)（通过多核实现）。
Amdahl’s Law states that the speedup of a program using multiple processors is limited by the sequential fraction of the program. If 10% is sequential, maximum speedup is 10x.
阿姆达尔定律指出，使用多个处理器时程序的加速受其串行部分限制。如果 10% 为串行，则最大加速比为 10 倍。
Cache coherence is a major challenge in multi-core systems: all cores must see a consistent view of memory, often maintained by protocols like MESI.
缓存一致性是多核系统的一大挑战：所有核心必须看到一致的内存视图，通常通过 MESI 等协议来维护。
Exam questions often ask to evaluate the impact of multi-core on performance and to distinguish between concurrency and parallelism.
考试题目经常要求评估多核对性能的影响，并区分并发与并行。
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