IGCSE AQA Computer Science: CPU in Focus | IGCSE AQA 计算机：CPU 考点精讲

📚 IGCSE AQA Computer Science: CPU in Focus | IGCSE AQA 计算机：CPU 考点精讲

The Central Processing Unit (CPU) is often called the ‘brain’ of the computer. For the IGCSE AQA Computer Science specification, understanding the architecture of the CPU, how it processes instructions, and the factors that influence its performance is absolutely fundamental. This article breaks down every essential concept you need to know, from the Von Neumann architecture to the fetch‑decode‑execute cycle, and provides clear explanations paired with key exam tips. Whether you are building your foundation or revising for the final paper, this guide will help you master the CPU topic with confidence.

中央处理器（CPU）常被称为计算机的’大脑’。在 IGCSE AQA 计算机科学课程中，理解 CPU 的架构、它如何处理指令以及影响其性能的因素是至关重要的基础知识。本文拆解了从冯·诺依曼架构到取指–解码–执行周期的每一个必知概念，并配以清晰的解释和关键的考试技巧。无论是打基础还是为最终试卷做复习，这份指南都将帮助你自信地掌握 CPU 专题。

1. The Von Neumann Architecture | 冯·诺依曼架构

The vast majority of modern computers are based on the Von Neumann architecture. In this design, both program instructions and data are stored in the same main memory (RAM). The CPU fetches instructions and data from this shared memory using a set of buses. The architecture revolves around the idea of the stored‑program concept, where a program must first be loaded into memory before execution can begin. This simplicity makes the system cost‑effective, but it also creates the ‘Von Neumann bottleneck’, where the shared bus limits the speed at which data and instructions can be transferred simultaneously.

现代计算机绝大多数都基于冯·诺依曼架构。在这种设计中，程序指令和数据都存储在同一主存储器（RAM）中。CPU 通过一组总线从共享内存中获取指令和数据。该架构的核心思想是存储程序概念，即程序必须先加载到内存中才能开始执行。这种简单性使系统具有成本效益，但也带来了’冯·诺依曼瓶颈’，即共享总线限制了数据和指令同时传输的速度。

In your exam, you may be asked to describe this architecture or identify its key feature: a single memory for both instructions and data. Remember that the alternative, Harvard architecture, uses separate memories, but for IGCSE AQA, Von Neumann is the main focus. The typical components connected to the CPU via buses within this architecture include memory (RAM), input devices, and output devices.

在考试中，你可能会被要求描述这种架构或指出其关键特征：指令和数据共用同一个存储器。请记住，另一种架构——哈佛架构——使用独立的存储器，但在 IGCSE AQA 中，重点是冯·诺依曼架构。在此架构中，通过总线与 CPU 连接的典型组件包括内存（RAM）、输入设备和输出设备。

2. Components of the CPU: An Overview | CPU 组件概览

The CPU consists of three main functional parts: the Control Unit (CU), the Arithmetic Logic Unit (ALU), and a set of registers. These units work together continuously to carry out the fetch‑decode‑execute cycle. The CU orchestrates the entire process by sending control signals, the ALU performs calculations and logical operations, and the registers provide ultra‑fast storage locations for data and addresses currently being used. Modern CPUs also contain cache memory directly on the chip to speed up access to frequently used instructions and data.

CPU 主要由三个功能部分组成：控制单元（CU）、算术逻辑单元（ALU）和一组寄存器。这些单元协同工作，持续执行取指–解码–执行周期。CU 通过发送控制信号来协调整个过程，ALU 执行计算和逻辑运算，而寄存器则为当前正在使用的数据和地址提供超高速的存储位置。现代 CPU 还在芯片上直接集成了缓存（cache memory），以加快对常用指令和数据的访问速度。

When drawing a simple CPU diagram, most exam boards expect you to show the CU, ALU, registers such as the Program Counter and Accumulator, and the connections via buses. The CPU does not store entire programs; it holds only the data and instructions it is immediately working on in its registers and cache. Understanding this basic layout is the first step to explaining how the computer processes any task.

在绘制简单的 CPU 示意图时，多数考试局期望你画出 CU、ALU、诸如程序计数器和累加器之类的寄存器，以及通过总线的连接。CPU 并不存储整个程序；它只在寄存器和缓存中保存当前正在处理的指令和数据。理解这一基本布局是解释计算机如何处理任何任务的第一步。

3. The Arithmetic Logic Unit (ALU) | 算术逻辑单元 (ALU)

The ALU is the part of the CPU that performs all arithmetic and logical operations. Arithmetic operations include addition, subtraction, multiplication, and division. Logical operations involve bitwise AND, OR, NOT, and comparisons (such as checking if one value is greater than another). For any operation to be carried out, data must be moved from registers into the ALU, and the result is then stored back in a register, typically the Accumulator.

ALU 是 CPU 中执行所有算术和逻辑运算的部分。算术运算包括加法、减法、乘法和除法。逻辑运算涉及按位与、或、非以及比较（例如检查一个值是否大于另一个值）。对于任何要执行的操作，数据必须从寄存器移入 ALU，而后运算结果存回寄存器，通常是累加器。

Exam questions often ask students to state what the ALU does or to identify which component performs calculations. A precise answer would be: ‘The ALU performs arithmetic and logical operations on data.’ You may also need to explain that the ALU receives data from the general‑purpose registers and that its outputs can set condition flags (such as zero or overflow) in the status register, influencing future decisions in the program.

考试题目常要求学生说明 ALU 的功能，或指出哪个组件执行计算。准确的回答是：’ALU 对数据进行算术和逻辑运算。’你可能还需要解释 ALU 从通用寄存器接收数据，其输出可以在状态寄存器中设置条件标志（如零或溢出），从而影响程序中的后续决策。

4. The Control Unit (CU) | 控制单元 (CU)

The Control Unit is the coordinator of the CPU. It does not process data; instead, it directs the flow of data and instructions. The CU decodes the instruction fetched from memory and then generates the necessary control signals to tell the ALU what operation to execute, which registers to use, and when to read from or write to memory. It also manages the timing of all steps within the fetch‑decode‑execute cycle using the system clock.

控制单元是 CPU 的协调者。它不处理数据，而是指挥数据和指令的流动。CU 对从内存中取出的指令进行解码，然后生成必要的控制信号，告诉 ALU 要执行什么操作、使用哪些寄存器以及何时读写内存。它还利用系统时钟管理取指–解码–执行周期中所有步骤的时序。

Think of the CU as the conductor of an orchestra: it ensures that every part of the CPU works in harmony at the correct moment. In the exam, you might need to distinguish between the roles of CU and ALU. A simple trick is: CU decides what to do and when, ALU does the actual maths and logic. The CU is also responsible for retrieving the next instruction from the address held in the Program Counter, further emphasizing its steering role.

你可以将 CU 想象成管弦乐队的指挥：它确保 CPU 的每一部分在正确的时刻协调工作。在考试中，你可能需要区分 CU 和 ALU 的角色。一个简单的诀窍是：CU 决定做什么以及何时做，ALU 执行实际的数学和逻辑运算。CU 还负责从程序计数器中保存的地址获取下一条指令，这进一步突显了它的引导作用。

5. Key Registers and Their Roles | 关键寄存器及其作用

Registers are small, extremely fast storage locations inside the CPU. Each register has a specific purpose. The most important ones for IGCSE AQA are:

Program Counter (PC) – holds the memory address of the next instruction to be fetched.
Memory Address Register (MAR) – holds the address of the memory location that is about to be read from or written to.
Memory Data Register (MDR) – holds the actual data or instruction that has been read from memory or is about to be written to memory.
Current Instruction Register (CIR) – holds the instruction currently being decoded and executed.
Accumulator (ACC) – stores the results of calculations performed by the ALU.

寄存器是 CPU 内部极小的、速度极快的存储位置。每个寄存器都有特定的用途。IGCSE AQA 中最重要的寄存器如下：

程序计数器 (PC)——存放下一条要取入的指令的内存地址。
内存地址寄存器 (MAR)——存放即将被读写的内存位置的地址。
内存数据寄存器 (MDR)——存放刚从内存读出的、或即将写入内存的实际数据或指令。
当前指令寄存器 (CIR)——存放当前正在被解码和执行的指令。
累加器 (ACC)——存储 ALU 执行的计算结果。

In addition, a Status Register (SR) holds condition flags such as carry, zero, overflow, and negative, which influence conditional branching. During the fetch‑decode‑execute cycle, the roles of these registers change sequentially. Being able to describe what each register holds at each stage of the cycle is a key skill. For example, during a LOAD instruction, the MDR will contain the data fetched from RAM, which is then transferred into the ACC.

此外，状态寄存器 (SR) 保存进位、零、溢出和负数等条件标志，这些标志影响条件分支。在取指–解码–执行周期中，这些寄存器的作用依次变化。能够描述每个寄存器在周期各阶段存放的内容是一项关键技能。例如，在执行 LOAD 指令时，MDR 将包含从 RAM 中取出的数据，随后该数据被传送到 ACC 中。

6. The Fetch-Decode-Execute Cycle | 取指–解码–执行周期

The CPU processes instructions one at a time using a continuous loop called the fetch‑decode‑execute cycle. Although extremely fast, the sequence is systematic. In the fetch stage, the address in the PC is copied to the MAR, and the PC is incremented to point to the next instruction. A read signal is sent to memory, and the instruction at the address in the MAR is placed into the MDR, then copied to the CIR. In the decode stage, the Control Unit interprets the instruction in the CIR and prepares the necessary circuits. In the execute stage, the instruction is carried out: the ALU may perform a calculation, or data may be loaded from or stored to memory. The cycle then repeats.

CPU 使用一个称为取指–解码–执行周期的连续循环来一次处理一条指令。尽管速度极快，但过程是系统化的。在取指阶段，PC 中的地址被复制到 MAR，PC 递增以指向下一条指令。CPU 向内存发送读信号，MDR 中放入 MAR 所指地址处的指令，然后该指令被复制到 CIR。在解码阶段，控制单元解释 CIR 中的指令并准备必要的电路。在执行阶段，指令被执行：ALU 可能进行运算，或者从内存加载数据或向内存存储数据。然后循环重复。

You may be required to illustrate this cycle for a specific instruction, such as ADD . In that case, the execute stage would involve fetching the operand from memory (another mini‑fetch cycle), passing it to the ALU along with the accumulator value, and storing the result back in the ACC. Another common example is the LOAD instruction, which moves data from RAM into the ACC. Be ready to explain how the MDR, MAR, and CIR are used without mixing up their roles.

你可能会被要求针对特定指令（如 ADD <内存地址>）说明此周期。在这种情况下，执行阶段将涉及从内存中取操作数（另一个微型取指周期）、将其与累加器中的值一起送入 ALU，并将结果存回 ACC。另一个常见例子是 LOAD 指令，它将数据从 RAM 移入 ACC。请准备好解释 MDR、MAR 和 CIR 如何被使用，而不要混淆它们的角色。

7. Buses: Address, Data, and Control | 总线：地址总线、数据总线和控制总线

The CPU communicates with memory and input/output devices via three types of bus. The address bus carries the memory address from the CPU (specifically the MAR) to RAM or an I/O controller. It is a unidirectional bus – data only travels from the CPU outward. The width of the address bus determines the maximum number of addressable memory locations. The data bus carries the actual data or instructions between the CPU and memory or I/O devices; this bus is bidirectional. The control bus carries control signals such as read, write, and clock pulses. It is also bidirectional, with different lines carrying signals in different directions.

CPU 通过三种类型的总线与内存和输入/输出设备通信。地址总线将内存地址从 CPU（特别是 MAR）传送到 RAM 或 I/O 控制器。这是一条单向总线——数据只能从 CPU 向外传输。地址总线的宽度决定了可寻址内存位置的最大数量。数据总线在 CPU 与内存或 I/O 设备之间传输实际数据或指令；这条总线是双向的。控制总线传输控制信号，如读、写和时钟脉冲。它也是双向的，不同的线路承载不同方向的信号。

A typical exam question might ask: ‘State two differences between the address bus and the data bus.’ A model answer would be: the address bus is unidirectional, while the data bus is bidirectional; the address bus carries addresses, while the data bus carries data/instructions. You should also link bus width to performance: a wider data bus can move more bits in one clock cycle, and a wider address bus allows the system to address more memory.

典型的考试问题可能会问：’说出地址总线和数据总线之间的两个区别。’标准答案是：地址总线是单向的，而数据总线是双向的；地址总线传输地址，而数据总线传输数据/指令。你还应将总线宽度与性能联系起来：更宽的数据总线可以在一个时钟周期内传输更多位，更宽的地址总线则允许系统寻址更多内存。

8. Clock Speed and Performance | 时钟速度与性能

The system clock generates a continuous sequence of pulses that synchronises all components. Clock speed is measured in Hertz (Hz), with modern CPUs typically in gigahertz (GHz). Each clock pulse triggers a step in the fetch‑decode‑execute cycle, so in theory, a higher clock speed means more instructions can be processed per second. However, the relationship is not purely linear: other factors such as memory speed and thermal limits also affect real‑world performance. When the clock speed increases, the CPU consumes more power and generates more heat, which is why overclocking requires better cooling.

系统时钟生成连续的脉冲序列，使所有组件同步。时钟速度以赫兹 (Hz) 为单位，现代 CPU 通常为千兆赫兹 (GHz)。每个时钟脉冲触发取指–解码–执行周期中的一个步骤，因此理论上，更高的时钟速度意味着每秒可处理更多指令。然而，这种关系并非纯线性：内存速度和热限制等其他因素也会影响实际性能。当时钟速度提高时，CPU 消耗的功率更大、产生更多热量，这就是为什么超频需要更好的散热。

Exam questions often ask you to explain how increasing clock speed improves performance. Use the following logic: a higher clock speed results in more cycles per second, so more instructions can be fetched, decoded, and executed per unit time. But also mention the diminishing returns caused by the Von Neumann bottleneck: beyond a certain point, the CPU may simply wait for data from the slower RAM, so the advantage of extra speed becomes limited.

考试问题通常要求解释提高时钟速度为何能提升性能。请使用以下逻辑：更高的时钟速度导致每秒更多周期，因此每单位时间可以取指、解码和执行更多指令。但也要提到由于冯·诺依曼瓶颈导致的收益递减：超过一定限度，CPU 可能只是在等待来自较慢 RAM 的数据，因此额外速度的优势变得有限。

9. Number of Cores | 核心数量

A core is a complete processing unit capable of performing its own fetch‑decode‑execute cycle. A multi‑core CPU contains two or more cores on a single chip. In theory, a dual‑core processor can execute two instructions simultaneously, doubling performance. In practice, the speedup is less than linear because the cores share resources like cache and buses, and because software must be specifically written to split tasks into parallel threads. Nevertheless, increasing the number of cores is an effective way to improve multitasking and the performance of modern applications such as video editing and gaming.

核心是能够执行自己的取指–解码–执行周期的完整处理单元。多核 CPU 在单一芯片上包含两个或更多核心。理论上，双核处理器可以同时执行两条指令，性能翻倍。实际上，加速比小于线性，因为核心共享缓存和总线等资源，而且软件必须专门编写以将任务拆分为并行线程。尽管如此，增加核心数量是提高多任务处理能力以及视频编辑和游戏等现代应用程序性能的有效方法。

For IGCSE, you should be careful to state that a quad‑core processor does not automatically run four times faster than a single‑core processor at the same clock speed. The achievable speedup depends on the program’s ability to execute in parallel. Some sequential tasks cannot be divided, so they will only ever use one core. This is a classic exam distinction.

对于 IGCSE，你应注意说明，在相同时钟速度下，四核处理器并不会自动比单核处理器快四倍。实际可达到的加速比取决于程序的并行执行能力。某些顺序任务无法被分割，因此永远只会使用一个核心。这是一个经典的考试区分点。

10. Cache Memory | 缓存内存

Cache is a small amount of very fast memory located directly on the CPU or very close to it. It stores frequently used instructions and data so that the CPU can access them more quickly than fetching from main RAM. There are typically three levels of cache: L1 (fastest, smallest), L2, and sometimes L3 (larger, slightly slower). When the CPU needs data, it first checks L1 cache; if the data is not there (a cache miss), it checks L2, then RAM. The more cache available, the fewer slow accesses to RAM are needed, which boosts overall performance.

缓存是直接位于 CPU 上或非常靠近 CPU 的少量极快内存。它存储常用的指令和数据，以便 CPU 能够比从主 RAM 中获取更快地访问它们。通常有三个级别的缓存：L1（最快、最小）、L2，有时还有 L3（更大、稍慢）。当 CPU 需要数据时，它首先检查 L1 缓存；如果数据不在那里（缓存未命中），则检查 L2，然后检查 RAM。可用缓存越多，对 RAM 的慢速访问就越少，从而提升整体性能。

Exam questions frequently ask for a comparison between cache and RAM. Key points: cache is much faster, more expensive per byte, smaller in capacity, and located on or very close to the CPU. RAM is larger, slower, cheaper, and is placed further away on the motherboard. Also, cache is usually SRAM (static RAM), while main memory is DRAM (dynamic RAM). An increase in cache size is often the most cost‑effective way to improve real‑world performance in everyday computing.

考试问题经常要求比较缓存和 RAM。要点：缓存速度快得多，每字节成本更高，容量更小，位于 CPU 上或非常靠近 CPU。RAM 更大、更慢、更便宜，并且位于主板上较远的位置。此外，缓存通常是静态 RAM (SRAM)，而主内存是动态 RAM (DRAM)。对于日常计算，增加缓存大小往往是最具成本效益的实际性能提升方式。

11. Embedded Systems | 嵌入式系统

An embedded system is a computer system with a dedicated function within a larger mechanical or electrical system. Unlike general‑purpose computers, the CPU in an embedded system is often a microcontroller that integrates the processor, memory, and input/output peripherals on a single chip. Examples include washing machines, digital watches, microwave ovens, and engine control units in cars. Embedded systems are typically designed for low power consumption, real‑time operation, and high reliability.

嵌入式系统是在较大的机械或电气系统中具有专用功能的计算机系统。与通用计算机不同，嵌入式系统中的 CPU 通常是微控制器，它将处理器、存储器和输入/输出外围设备集成在单个芯片上。例子包括洗衣机、数字手表、微波炉和汽车中的引擎控制单元。嵌入式系统通常被设计为低功耗、实时操作和高可靠性。

In the AQA specification, you should know that embedded systems are based on the same principles as general CPUs but are highly specialised. They often have limited resources, no traditional operating system, and the program is stored in ROM or flash memory. When comparing with standard desktop CPUs, focus on the specific, single‑purpose nature, smaller form factor, and lower cost of embedded processors.

在 AQA 考纲中，你应了解嵌入式系统基于与通用 CPU 相同的原理，但高度专用化。它们通常资源有限，没有传统的操作系统，程序存储在 ROM 或闪存中。在与标准台式机 CPU 比较时，请重点突出嵌入式处理器特定、单一用途的本质、更小的外形尺寸和更低的成本。

12. Exam Tips and Common Pitfalls | 考试技巧与常见误区

When answering CPU questions, always use precise terminology. Instead of saying ‘the thing that does maths’, write ‘the ALU performs arithmetic and logical operations’. Marks are often lost through vague language. For the fetch‑decode‑execute cycle, memorise the sequence of register transfers: PC → MAR, memory read, MDR → CIR, then decode and execute. A diagram with clear labels can earn full marks even if your written description is brief, as long as the key steps are shown.

在回答 CPU 问题时，务必使用精确的术语。不要说’做数学运算的东西’，而要写’ALU 执行算术和逻辑运算’。因语言模糊而丢分的情况很常见。对于取指–解码–执行周期，请记住寄存器传输的顺序：PC → MAR，内存读取，MDR → CIR，然后解码并执行。一张带有清晰标签的示意图，只要展示了关键步骤，即使文字描述简短也能获得满分。

Common mistakes include confusing the MDR and MAR (one holds data, the other holds addresses), believing that a higher clock speed always results in proportional performance gains, and forgetting that cache is faster than RAM but smaller. Also, when explaining how cores affect performance, avoid the trap of saying ‘two cores double the speed’. Instead, use qualifiers such as ‘in ideal parallel workloads’ or ‘up to twice the performance’. Always link hardware knowledge back to the stored‑program concept and the flow of data through buses.

常见错误包括混淆 MDR 和 MAR（一个保存数据，另一个保存地址）、认为更高的时钟速度总会带来成比例的性能提升，以及忘记缓存比 RAM 快但容量更小。此外，在解释核心如何影响性能时，避免落入’双核使速度翻倍’的陷阱。相反，应使用限定词，如’在理想并行工作负载下’或’最高可达两倍性能’。始终将硬件知识与存储程序概念以及数据通过总线的流动联系起来。

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IGCSE AQA Computer Science: CPU in Focus | IGCSE AQA 计算机：CPU 考点精讲