📚 IGCSE OCR Computer Science: Computer Architecture Exam Focus | IGCSE OCR 计算机：计算机体系结构 考点精讲
Welcome to this focused revision guide on Computer Architecture for the IGCSE OCR Computer Science specification. Understanding how a computer’s processor works is fundamental to grasping how programs are executed and how to evaluate system performance. This article breaks down every key concept you need to know – from the Von Neumann model to the fetch‑decode‑execute cycle, from registers to cache – all aligned with the OCR exam requirements. We will translate technical ideas into clear explanations, provide comparisons, and highlight common pitfalls so you can tackle any exam question with confidence.
欢迎阅读这篇针对 IGCSE OCR 计算机科学大纲的计算机体系结构考点精讲。理解计算机处理器的工作原理，是掌握程序如何执行以及如何评价系统性能的基础。本文详细解析了所有你需要掌握的关键概念——从冯·诺依曼模型到取指‑解码‑执行周期，从寄存器到缓存——完全贴合 OCR 考试要求。我们将技术概念转化为清晰解释，并提供对比分析和常见误区提醒，让你能够自信应对任何考试题目。
1. What Is Computer Architecture? | 什么是计算机体系结构？
Computer architecture describes the logical design and organisation of the internal components of a computer system, including the central processing unit (CPU), memory, and how data flows between them. In the IGCSE OCR context, the architecture you study is almost exclusively the Von Neumann architecture, which stores both program instructions and data in the same memory. This concept is central because it explains why computers can be reprogrammed simply by loading different software into memory, without rewiring hardware.
计算机体系结构描述了计算机系统内部组件的逻辑设计和组织方式，包括中央处理器 (CPU)、存储器以及它们之间的数据流动。在 IGCSE OCR 范围内，你学习的体系结构几乎完全是冯·诺依曼架构，该架构将程序指令和数据存储在同一个存储器中。这一概念之所以核心，是因为它解释了为什么计算机只须将不同软件加载到内存即可重新编程，而无须更改硬件线路。
When you encounter questions about ‘describe the architecture of a computer’, your answer must include the processor, memory, input/output interfaces, and the buses that connect them. You should also be able to contrast it with alternative models, such as Harvard architecture, where instructions and data are stored in separate memories – a point that frequently appears in high‑mark questions.
当你遇到“描述计算机体系结构”的问题时，你的回答必须包括处理器、内存、输入／输出接口以及连接它们的总线。你还应该能够将其与替代模型（如指令和数据分开存储的哈佛架构）进行对比——这一点常在高分题中出现。
2. The Von Neumann Architecture in Detail | 冯·诺依曼体系结构详解
A Von Neumann machine consists of a single shared memory for both instructions and data, a control unit, an arithmetic logic unit, and input/output facilities. The key feature is the stored‑program concept: the program to be executed is loaded into memory as a sequence of binary machine code instructions. The processor reads these instructions one by one, decodes them, and executes them. This is the foundation of the fetch‑decode‑execute cycle.
冯·诺依曼机器由一个存储指令和数据共享的单一内存、一个控制器、一个算术逻辑单元以及输入／输出设备组成。其关键特征在于存储程序概念：要执行的程序作为一系列二进制机器码指令被加载到内存中。处理器逐条读取这些指令，进行译码并执行。这就是取指‑解码‑执行周期的基础。
The architecture requires at least three main buses: an address bus to specify memory locations, a data bus to transfer the actual information, and a control bus to coordinate activity. OCR examiners expect you to label these on a diagram and state their function. All data and instructions travel along these shared pathways; this creates a limit known as the ‘Von Neumann bottleneck’ – the speed of the processor is constrained by how quickly the bus can transfer data between memory and CPU.
该架构至少需要三条主要总线：用于指定内存地址的地址总线、传输实际信息的数据总线，以及协调活动的控制总线。OCR 考官期望你能够在图上标记这些总线并说明其功能。所有数据和指令都沿着这些共享通路传输；这就产生了一个被称为“冯·诺依曼瓶颈”的限制——处理器的速度受限于总线在内存和 CPU 之间传输数据的速度。
3. Central Processing Unit (CPU) Components | 中央处理器 (CPU) 的组成部分
The CPU is the ‘brain’ of the computer. It is composed of two main sections: the Control Unit (CU) and the Arithmetic Logic Unit (ALU), along with a set of high‑speed storage locations called registers. The CU manages the execution of instructions by sending control signals to other components. The ALU performs arithmetic operations (addition, subtraction) and logical operations (AND, OR, NOT). Together they process every piece of data the computer handles.
CPU 是计算机的“大脑”。它由两个主要部分组成：控制器 (CU) 和算术逻辑单元 (ALU)，以及一组称为寄存器的高速存储位置。CU 通过向其他部件发送控制信号来管理指令的执行。ALU 执行算术运算（加法、减法）和逻辑运算（与、或、非）。它们一起处理计算机处理的每一条数据。
In the IGCSE OCR curriculum, you must be able to identify the role of each component and explain how they interact. For example, the CU fetches an instruction from memory and then directs the ALU to carry out a calculation if the instruction is an arithmetic one. The results may be stored back in a register or in memory. A table of component functions is an excellent way to revise this:
在 IGCSE OCR 课程中，你必须能够识别每个组件的作用并解释它们如何交互。例如，CU 从内存中取出一条指令，然后如果该指令是算术指令，则指挥 ALU 执行计算。结果可能存回寄存器或内存中。用表格梳理各组件功能是复习的好方法：
| Component | Function | OCR Exam Tip |
| Control Unit (CU) | Decodes instructions and controls data flow. | Mention ‘control signals’ and ‘decoding’. |
| Arithmetic Logic Unit (ALU) | Performs calculations and logical tests. | Give examples: addition, AND, OR. |
| Registers | Extremely fast memory locations inside the CPU. | Know PC, MAR, MDR, ACC at minimum. |
4. Registers and Their Specialised Roles | 寄存器及其专用功能
Registers are small, super‑fast storage cells within the CPU that hold temporary data during instruction execution. The most important registers for your exam are the Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), and Accumulator (ACC). Each has a precisely defined role in the fetch‑decode‑execute cycle.
寄存器是 CPU 内部极小的超高速存储单元，用于在指令执行期间暂存数据。考试中最重要的寄存器有程序计数器 (PC)、内存地址寄存器 (MAR)、内存数据寄存器 (MDR) 和累加器 (ACC)。每个寄存器在取指‑解码‑执行周期中都有精确定义的功能。
The PC holds the memory address of the next instruction to be fetched. The MAR holds the address from which data will be read or to which it will be written. The MDR holds the actual data or instruction that has been read from or is about to be written to memory. The ACC temporarily stores the results of calculations performed by the ALU. A typical exam question might ask: ‘After incrementing the PC, which register holds the address of the instruction just read?’ Your answer: the MAR. Practice with these details is essential.
PC 保存下一条待取指令的内存地址。MAR 保存将要读取或写入数据的地址。MDR 保存从内存读出的或将要写入内存的实际数据或指令。ACC 暂存 ALU 执行的计算结果。一道典型的考题可能会问：“在 PC 自增后，哪个寄存器保存刚刚被读取的指令的地址？”答案是 MAR。对这些细节的练习至关重要。
5. The Fetch‑Decode‑Execute Cycle | 取指‑解码‑执行周期
This cycle is the pulse of every Von Neumann computer. It repeats continuously while the computer is powered on, processing billions of instructions per second. Each stage involves specific registers and buses. In the fetch stage, the address from the PC is copied into the MAR, the instruction is read from memory into the MDR, and then the PC is incremented. In the decode stage, the CU interprets the instruction. In the execute stage, the relevant operation is carried out – perhaps an ALU calculation or a memory access.
这个周期是每台冯·诺依曼计算机的脉搏。当计算机通电时，它会连续重复，每秒处理数十亿条指令。每个阶段都涉及特定的寄存器和总线。在取指阶段，PC 中的地址被复制到 MAR，指令从内存读入 MDR，然后 PC 自增。在解码阶段，CU 解释指令。在执行阶段，相关操作被执行——可能是一次 ALU 计算或者一次存储器访问。
You must be able to describe this cycle step by step, referencing registers. Many students lose marks by forgetting that the PC is incremented before execution actually occurs. A helpful mnemonic is ‘Find the address, Fetch the instruction, Decode what it means, Execute the action’. Always link each step to the register content. For instance, after fetching, the MDR contains the instruction opcode, and the PC points to the next instruction.
你必须能够逐步描述这一周期，并引用寄存器。许多学生因为忘记 PC 是在执行实际发生之前自增而丢分。一个有用的记忆口诀是“找地址、取指令、解含义、执行动作”。始终将每一步与寄存器内容联系起来。例如，取指后 MDR 包含指令操作码，而 PC 指向下一条指令。
6. Factors Affecting CPU Performance: Clock Speed | 影响 CPU 性能的因素：时钟速度
Clock speed is measured in gigahertz (GHz) and defines the number of fetch‑decode‑execute cycles the CPU can complete per second. A 3.5 GHz processor can theoretically perform 3.5 billion cycles per second. Higher clock speed generally means faster processing, but it is not the only factor. The speed is governed by an internal clock that synchronises all components. However, simply increasing clock speed generates more heat and consumes more power, so there are physical limits.
时钟速度以吉赫 (GHz) 为单位，定义了 CPU 每秒能够完成的取指‑解码‑执行周期数。一个 3.5 GHz 的处理器理论上每秒可完成 35 亿个周期。更高的时钟速度通常意味着更快的处理速度，但这并非唯一因素。速度受内部时钟控制，该时钟同步所有组件。然而，单纯提高时钟速度会产生更多热量并消耗更多电能，因此存在物理限制。
When answering OCR questions on performance, always relate clock speed to the cycle. Example: ‘A processor with a clock speed of 4 GHz can execute more instructions per second than a 2 GHz processor, assuming other factors are equal.’ Avoid the common mistake of claiming that a doubling of clock speed always doubles real‑world performance – other bottlenecks like memory latency may limit the improvement.
在回答 OCR 关于性能的问题时，务必将时钟速度与周期联系起来。例如：“在其它因素相同的情况下，4 GHz 处理器比 2 GHz 处理器每秒能执行更多指令。”要避免一个常见错误：声称时钟速度翻倍总能带来实际性能翻倍——内存延迟等其它瓶颈可能会限制性能提升。
7. Factors Affecting CPU Performance: Cores | 影响 CPU 性能的因素：核心数
A core is a complete processing unit capable of executing instructions independently. A multi‑core processor contains two or more cores, enabling true parallel processing. This means multiple instructions can be fetched, decoded, and executed simultaneously. Modern CPUs often have 4, 8, or more cores, which significantly boosts performance for multitasking and for software designed to take advantage of multiple threads.
核心是一个完整的处理单元，能够独立执行指令。多核处理器包含两个或更多核心，支持真正的并行处理。这意味着可以同时进行取指、解码和执行多条指令。现代 CPU 通常拥有 4 核、8 核甚至更多核心，这显著提升了多任务处理能力以及专为利用多线程设计的软件的性能。
However, more cores do not simply multiply performance. Some tasks are inherently sequential and cannot be split across cores. The software must be written to support parallel execution. In your exam, a typical comparison might be: a dual‑core 3 GHz processor can execute up to two instruction streams at once, whereas a single‑core 3.5 GHz processor might perform better on a single‑threaded task. You should be comfortable explaining the trade‑off.
然而，核心数增多并不会简单地使性能翻倍。某些任务本质上是顺序执行的，无法拆分到多个核心上。软件必须支持并行执行才能发挥优势。在考试中，一种典型的比较可能是：双核 3 GHz 处理器能够同时执行多达两条指令流，而单核 3.5 GHz 处理器可能在单线程任务上表现更好。你应能熟练解释这种权衡。
8. Factors Affecting CPU Performance: Cache Memory | 影响 CPU 性能的因素：缓存
Cache is a small amount of extremely high‑speed memory located inside or very close to the CPU. It stores frequently accessed instructions and data to reduce the time needed to fetch them from the slower main memory (RAM). There are usually three levels: L1 cache is the fastest and smallest, L2 is larger but slightly slower, and L3 is even larger and shared among cores. The principle of locality explains why cache works: programs tend to reuse the same data and instructions repeatedly.
缓存是位于 CPU 内部或非常靠近 CPU 的一小部分超高速存储器。它存储频繁访问的指令和数据，以减少从速度较慢的主存 (RAM) 中提取它们所需的时间。缓存通常分为三级：L1 缓存最快也最小，L2 较大但稍慢，L3 更大且在核心间共享。局部性原理解释了缓存为何有效：程序倾向于反复使用相同的数据和指令。
For the OCR exam, you need to state that more cache generally improves performance, especially when the cache hit rate is high. A cache hit occurs when the required data is found in cache; a cache miss forces the CPU to wait for data from RAM. Understand that adding cache is expensive and increases the physical size of the processor die, so manufacturers must balance cost and performance. Comparing two processors with different cache sizes is a common question.
对于 OCR 考试，你需要说明更多的缓存通常能提高性能，尤其是在缓存命中率高的时候。当所需数据在缓存中找到时称为缓存命中；若缓存未命中，则 CPU 必须等待来自 RAM 的数据。要理解增加缓存成本高昂，且会增大处理器芯片的物理尺寸，因此制造商必须在成本和性能之间取得平衡。比较两种不同缓存大小的处理器是常见的考题。
9. Embedded Systems: A Different Kind of Architecture | 嵌入式系统：一种不同的体系结构
An embedded system is a computer built into a larger device to perform a dedicated function. Unlike general‑purpose desktops, embedded systems have a very specific task – for example, controlling a washing machine cycle, managing a car’s engine control unit, or operating a microwave oven. They typically use microcontrollers that contain a processor, memory, and input/output peripherals all on a single chip, to minimise size and power consumption.
嵌入式系统是内置于较大设备中、用于执行专用功能的计算机。与通用台式机不同，嵌入式系统有非常特定的任务——例如，控制洗衣机程序、管理汽车引擎控制单元或操作微波炉。它们通常使用微控制器，将处理器、存储器和输入／输出外设集成在单一芯片上，以最大限度地减少尺寸和功耗。
Exam questions often ask you to identify why an embedded system is suitable for a given scenario. Key points: they are reliable (fewer components, dedicated software), energy efficient, small, and can be mass‑produced at low cost. They do not need a full operating system; instead they run firmware stored in ROM. Be ready to contrast embedded systems with general‑purpose computers: one is optimised for a single task, the other is designed for flexibility.
考题经常要求你识别为何嵌入式系统适用于特定场景。关键点包括：可靠性高（组件少、软件专用）、能效好、体积小、可低成本批量生产。它们不需要完整的操作系统，而是运行存储在 ROM 中的固件。准备好将嵌入式系统与通用计算机进行对比：一个为单一任务优化，一个为灵活性而设计。
10. The Impact of Architecture on Everyday Performance | 体系结构对日常性能的影响
Architecture choices directly influence how a computer feels to use. For instance, a browser opening many tabs benefits from multiple cores and ample cache, because each tab may run as a separate process. Video editing software uses the ALU heavily for rendering effects and performs best when clock speeds are high and multiple cores are available. In contrast, a sensor‑based temperature logger may use a simple microcontroller with a low clock speed because it only needs to wake up periodically and record a value – an embedded system approach.
体系结构的选择直接影响计算机的使用体验。例如，打开多个标签的浏览器会受益于多核心和充足的缓存，因为每个标签可能作为独立进程运行。视频编辑软件重度依赖 ALU 进行特效渲染，当时钟速度高且多核可用时表现最佳。相反，基于传感器的温度记录仪可能使用低时钟速度的简单微控制器，因为它只需定时唤醒并记录一个数值——这正是嵌入式系统的思路。
Understanding these real‑world links helps you answer extended‑answer questions. The OCR mark scheme often rewards explicit connections between a component and a use‑case. For example, ‘a smartphone employs a multi‑core processor with L2 cache to swiftly switch between apps, while using low‑power cores for background tasks’ combines several architectural concepts. Practice making such links in your revision.
理解这些现实联系有助于你回答扩展题。OCR 评分方案常常奖励将组件与使用场景明确联系起来的做法。例如，“智能手机采用带有 L2 缓存的多核处理器，以在应用间快速切换，同时使用低功耗核心处理后台任务”——这就结合了多个体系结构概念。复习时要练习建立此类联系。
11. Common Exam Pitfalls and How to Avoid Them | 常见考试陷阱及如何避免
Many candidates mix up the MAR and MDR. Remember: MAR holds the address, MDR holds the data. The PC is not the same as the MAR; the PC holds the next instruction address, while the MAR holds the address of the memory location currently being accessed. Another common mistake is describing the fetch‑decode‑execute cycle without naming registers – OCR expects you to include them. Also, don’t simply say ‘cache speeds up the computer’; explain that it reduces the number of times the CPU must wait for slower main memory.
许多考生混淆 MAR 和 MDR。请记住：MAR 保存地址，MDR 保存数据。PC 不同于 MAR；PC 保存下一条指令的地址，而 MAR 保存当前正被访问的内存地址。另一个常见错误是描述取指‑解码‑执行周期却不提及寄存器——OCR 期望你将其包含在内。此外，不要简单地说“缓存加快计算机速度”，而要解释它减少了 CPU 必须等待较慢主存的次数。
When asked to compare two processors, always refer to the three main factors: clock speed, number of cores, and cache size. Make sure you state that the benefit depends on the type of task. A quad‑core 2.5 GHz processor might not outperform a dual‑core 3.5 GHz processor on a single‑threaded application. Finally, watch out for ‘state’ vs ‘describe’ vs ‘explain’ command words; they require different levels of detail.
当被要求比较两种处理器时，始终要提及三个主要因素：时钟速度、核心数和缓存大小。确保说明其益处取决于任务类型。一个四核 2.5 GHz 处理器在单线程应用上可能不如双核 3.5 GHz 处理器表现得更好。最后，注意“陈述 (state)”、“描述 (describe)”和“解释 (explain)”这些指令词的区别；它们要求的详细程度不同。
12. Revision Summary and Key Takeaways | 考点总结与核心要点
Computer architecture sits at the heart of IGCSE OCR Computer Science. The Von Neumann model, with its shared memory and sequential fetch‑decode‑execute cycle, explains how a CPU interprets and runs a program. The CU and ALU cooperate with registers such as PC, MAR, MDR, and ACC to carry out each instruction. Performance is determined by the interplay of clock speed, core count, and cache size, and the choice of architecture must match the intended application – from powerful desktops to tiny embedded microcontrollers. Master these concepts, use precise terminology, and you will be ready for any architecture question.
计算机体系结构是 IGCSE OCR 计算机科学的核心内容。冯·诺依曼模型凭借其共享存储器和顺序取指‑解码‑执行周期，解释了 CPU 如何解释并运行程序。CU 和 ALU 与 PC、MAR、MDR、ACC 等寄存器协同工作，执行每一条指令。性能取决于时钟速度、核心数和缓存大小之间的相互作用，而体系结构的选择必须与目标应用相匹配——从强大的台式机到微小的嵌入式微控制器。掌握这些概念，运用精确术语，你就能应对任何体系结构问题。
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