IGCSE WJEC Computer Science: Computer Architecture Key Points | IGCSE WJEC 计算机：计算机体系结构 考点精讲

📚 IGCSE WJEC Computer Science: Computer Architecture Key Points | IGCSE WJEC 计算机：计算机体系结构 考点精讲

This article breaks down the essential topics for the IGCSE WJEC Computer Science unit on computer architecture. We examine von Neumann design, the CPU and its components, the fetch‑decode‑execute cycle, factors affecting performance, embedded systems, and primary memory. Each section pairs an English explanation with a matching Chinese version to reinforce understanding.

本文精讲 IGCSE WJEC 计算机科学中计算机体系结构的核心考点。我们逐一拆解冯·诺依曼架构、CPU 及其组成、取指-解码-执行循环、影响性能的因素、嵌入式系统以及主存储器。每个要点均提供英文讲解与中文对照，帮助你在备考中真正吃透概念。

1. The Von Neumann Architecture | 冯·诺依曼体系结构

The von Neumann architecture is the foundation of almost all modern computers. It describes a design where program instructions and data share the same memory and are transferred along a single set of buses. A central processing unit (CPU) fetches each instruction from memory, decodes it, and executes it sequentially. This stored‑program concept means that software can be changed without altering the hardware, making general‑purpose computing possible.

冯·诺依曼体系结构是绝大多数现代计算机的基石。它指出，程序指令与数据共用同一块内存，并通过同一组总线传输。中央处理器（CPU）从内存中逐条取出指令、解码并执行。这种“存储程序”的思想意味着无需改动硬件即可更换软件，通用计算由此变为现实。

• Instructions and data are stored in a common main memory. | 指令和数据保存在公共的主存中。

• The CPU uses a single data bus and address bus for both fetches and data transfers. | CPU 使用同一组数据总线和地址总线完成取指和数据传输。

• Processing is sequential unless branch instructions alter the flow. | 除非遇到跳转指令，处理过程总是顺序进行。

• The architecture is simple, flexible, and forms the basis of most desktop, laptop, and server CPUs. | 该结构简单灵活，是大多数台式机、笔记本和服务器 CPU 的基础。

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2. The CPU and Its Main Components | CPU 及其主要组件

The CPU is the ‘brain’ of the computer. It consists of three essential functional units: the control unit (CU), the arithmetic logic unit (ALU), and a set of registers. The CU orchestrates the fetch‑decode‑execute cycle by sending control signals to the other components. The ALU performs arithmetic operations (addition, subtraction) and logic operations (AND, OR, NOT). Registers are small, ultrafast storage locations inside the CPU that hold data, instructions, and addresses temporarily.

CPU 堪称计算机的“大脑”，由三个核心功能单元构成：控制单元（CU）、算术逻辑单元（ALU）以及一组寄存器。控制单元通过向其他部件发出控制信号来指挥取指‑解码‑执行循环。ALU 负责算术运算（加、减）和逻辑运算（与、或、非）。寄存器是 CPU 内部极小且极快的存储区域，用于临时存放数据、指令和地址。

• Control Unit (CU) – decodes instructions and generates timing and control signals. | 控制单元 (CU) – 解码指令并生成时序与控制信号。

• Arithmetic Logic Unit (ALU) – carries out calculations and logical comparisons. | 算术逻辑单元 (ALU) – 执行计算和逻辑比较。

• Registers – provide immediate storage for the CU and ALU. Key registers include the program counter (PC), memory address register (MAR), memory data register (MDR), current instruction register (CIR), and accumulator (ACC). | 寄存器 – 为 CU 和 ALU 提供即时存储。关键寄存器包括程序计数器 (PC)、内存地址寄存器 (MAR)、内存数据寄存器 (MDR)、当前指令寄存器 (CIR) 和累加器 (ACC)。

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3. Special Registers and Their Roles | 专用寄存器及其作用

Registers close to the control unit and ALU ensure the fetch‑decode‑execute cycle runs smoothly. The program counter holds the memory address of the next instruction to be fetched. The memory address register stores the address currently being accessed in main memory. The memory data register (or memory buffer register) contains the data or instruction that has been read from, or is about to be written to, main memory. The current instruction register holds the opcode and operand of the instruction currently being decoded and executed. The accumulator temporarily stores results produced by the ALU.

靠近控制单元和 ALU 的寄存器保证了取指‑解码‑执行循环的顺畅运行。程序计数器存放着下一条待取指令的内存地址。内存地址寄存器存放当前正在访问的主存地址。内存数据寄存器（或称内存缓冲寄存器）保存刚从主存读出或即将写入主存的数据或指令。当前指令寄存器存放正在解码和执行的操作码与操作数。累加器则暂存 ALU 产生的结果。

Register | 寄存器	Purpose | 用途
PC (Program Counter) | 程序计数器	Holds address of next instruction to fetch. | 存放下一条要取指令的地址。
MAR (Memory Address Register) | 内存地址寄存器	Holds the address of the memory location being accessed. | 存放正在访问的内存单元地址。
MDR (Memory Data Register) | 内存数据寄存器	Stores data or instructions moving to/from main memory. | 存放往来主存的数据或指令。
CIR (Current Instruction Register) | 当前指令寄存器	Holds the instruction being decoded and executed. | 存放正在解码与执行的指令。
ACC (Accumulator) | 累加器	Temporarily stores results from the ALU. | 暂存 ALU 的运算结果。

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4. The Fetch‑Decode‑Execute Cycle | 取指‑解码‑执行循环

The CPU operates in a continuous loop known as the fetch‑decode‑execute (FDE) cycle. In the fetch phase, the address from the PC is copied to the MAR, the instruction is read from main memory into the MDR, and the PC is incremented. During decode, the CU interprets the bit pattern in the CIR and configures the ALU and data pathways accordingly. In the execute phase, the ALU performs the required operation—whether a calculation, a memory access, or a branching decision—and any result is written back to a register or to main memory. The cycle then repeats for the next instruction.

CPU 以“取指‑解码‑执行” (FDE) 循环持续运转。取指阶段：PC 的地址被复制到 MAR，指令从主存读入 MDR，随后 PC 递增。解码阶段：CU 解读 CIR 中的位模式，并相应配置 ALU 及数据通路。执行阶段：ALU 完成所需操作（可能是计算、访存或跳转判断），结果写回寄存器或主存。然后，循环对下一条指令重复进行。

• Fetch – address from PC → MAR; read memory → MDR; instruction moved to CIR; PC incremented. | 取指 – PC 地址 → MAR；读内存 → MDR；指令移入 CIR；PC 递增。

• Decode – CU interprets the instruction in the CIR. | 解码 – CU 解读 CIR 中的指令。

• Execute – ALU performs the operation; result stored in ACC or main memory. | 执行 – ALU 执行操作；结果存入 ACC 或主存。

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5. Buses and Their Functions | 总线及其功能

Buses are sets of parallel wires that carry data, addresses, and control signals between the CPU, memory, and I/O devices. There are three main buses: the data bus (bidirectional, carries the actual data being transferred), the address bus (unidirectional, carries the memory address, and its width determines the maximum addressable memory), and the control bus (carries timing and command signals such as read/write and interrupts). Together they ensure all components communicate efficiently.

总线是 CPU、内存和 I/O 设备之间传输数据、地址和控制信号的并行导线组。主要分为三种总线：数据总线（双向，承载实际传输的数据）、地址总线（单向，承载内存地址，其宽度决定可寻址的最大内存容量）和控制总线（承载读写、中断等时序与命令信号）。它们共同保证各组件高效通信。

• Data bus – width matches the CPU word size; influences how much data can be moved in one cycle. | 数据总线 – 宽度与 CPU 字长匹配，决定单周期可传输的数据量。

• Address bus – unidirectional; n lines can address 2ⁿ memory locations. | 地址总线 – 单向；n 条线可寻址 2ⁿ 个内存单元。

• Control bus – coordinates activities with signals like memory read, memory write, I/O read, I/O write, and clock. | 控制总线 – 通过内存读、内存写、I/O 读、I/O 写和时钟等信号协调活动。

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6. Factors Affecting CPU Performance | 影响 CPU 性能的因素

CPU performance is not determined by a single number. Three major factors are often examined: clock speed, number of processing cores, and cache size. Clock speed, measured in hertz, indicates how many FDE cycles the CPU can execute per second. Multiple cores allow true parallel execution of instructions, boosting performance for multi‑threaded applications. Cache memory, usually built with high‑speed SRAM, stores frequently used instructions and data close to the CPU, reducing the need to access slower main memory. In WJEC questions, always connect the factor to the FDE cycle or to the speed of data access.

CPU 性能并非由单一指标决定。常考的三大因素为：时钟频率、处理核心数量和缓存大小。时钟频率以赫兹为单位，表示 CPU 每秒可执行多少个 FDE 循环。多核心允许真正的并行执行，从而提升多线程应用的性能。缓存通常由高速 SRAM 构成，将常用指令和数据保存在离 CPU 最近的地方，减少访问较慢主存的次数。在 WJEC 试题中，务必把每个因素与 FDE 循环或数据访问速度联系起来。

• Clock speed – higher frequency means more cycles per second and faster instruction processing, but also more heat. | 时钟频率 – 频率越高，每秒周期越多，指令处理越快，但发热也更多。

• Number of cores – a quad‑core CPU can work on four tasks simultaneously, provided the software supports parallel processing. | 核心数量 – 四核 CPU 可同时处理四个任务，前提是软件支持并行处理。

• Cache size – larger Level 1 and Level 2 caches reduce average memory access time, keeping the pipeline busy. | 缓存大小 – 更大的 L1、L2 缓存可降低平均内存访问时间，使流水线保持繁忙。

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7. Cache Memory in Detail | 缓存详解

Cache memory is a small, fast memory located inside or very close to the CPU. It temporarily holds copies of instructions and data that are likely to be reused. When the CPU needs to read from main memory, it first checks the cache. A ‘hit’ means the required data is already in the cache, allowing near‑instant access. A ‘miss’ means the CPU must fetch the data from slower RAM, which costs extra clock cycles. Modern CPUs use multiple cache levels (L1, L2, often L3) to balance speed and capacity. L1 is the smallest and fastest, L2 larger but slightly slower, and L3 shared among cores.

缓存是位于 CPU 内部或极近处的一块小型高速存储器。它临时存放可能会再次使用的指令和数据的副本。CPU 需要读取主存时，会先检查缓存。“命中”表示所需数据已在缓存中，可实现近乎即时的访问；“未命中”则意味着 CPU 必须从较慢的 RAM 获取数据，这会浪费额外的时钟周期。现代 CPU 采用多级缓存（L1、L2，常常还有 L3），以平衡速度与容量。L1 最小最快，L2 更大但略慢，L3 在各核心间共享。

• Cache is built with SRAM, which is faster and more expensive than DRAM used in main memory. | 缓存采用 SRAM，比主存用的 DRAM 更快也更昂贵。

• Temporal locality: a recently accessed item is likely to be reused soon. | 时间局部性：刚访问过的数据很可能再次被使用。

• Spatial locality: items near a recently accessed location are likely to be needed. | 空间局部性：刚访问过的地址附近的数据也很可能被需要。

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8. Embedded Systems vs General‑Purpose Computers | 嵌入式系统与通用计算机

An embedded system is a computer built into a larger device to perform a dedicated function. Unlike a desktop or laptop, it usually runs a single program stored in ROM. Embedded systems are found in microwave ovens, washing machines, digital watches, car engine control units, and smart home sensors. They are optimised for low power consumption, physical compactness, and reliability. General‑purpose computers can load and run many different applications, while embedded systems sacrifice flexibility for efficiency.

嵌入式系统是嵌入在更大设备内部、执行特定功能的计算机。与台式机或笔记本不同，它通常只运行存储在 ROM 中的单一程序。嵌入式系统应用于微波炉、洗衣机、电子手表、汽车发动机控制单元和智能家居传感器中。它们经过优化，追求低功耗、体积小巧和高可靠性。通用计算机可以加载运行各种不同应用，而嵌入式系统以牺牲灵活性为代价换取高效率。

• Runs dedicated firmware, often unchangeable by the user. | 运行专用固件，用户通常无法更改。

• Resource‑constrained: limited RAM and processing power, but sufficient for the task. | 资源受限：RAM 和处理能力有限，但对任务而言足够。

• Examples: digital thermostat, traffic light controller, fitness tracker. | 示例：数字恒温器、交通灯控制器、健身追踪器。

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9. Types of Primary Memory | 主存储器类型

Primary memory is directly accessible by the CPU and consists mainly of RAM and ROM. RAM (Random Access Memory) is volatile, losing its content when power is removed. It holds the operating system, applications, and data currently in use. ROM (Read Only Memory) is non‑volatile and stores firmware such as the BIOS or bootloader. ROM content is written during manufacture or through special procedures. In exam questions, be clear to contrast volatility, speed, and typical usage of each.

主存由 CPU 直接访问，主要包括 RAM 和 ROM。RAM（随机存取存储器）具有易失性，断电后数据丢失；它保管正在使用的操作系统、应用与数据。ROM（只读存储器）为非易失性，存储 BIOS 或引导程序等固件。ROM 的内容在生产过程中或通过特殊流程写入。答题时，务必清楚对比两者的易失性、速度与典型用途。

Property | 属性	RAM | 随机存取存储器	ROM | 只读存储器
Volatility | 易失性	Volatile (loses content without power) | 易失	Non‑volatile | 非易失
Common use | 常见用途	Main memory for running programs | 运行程序的主存	Stores firmware, BIOS, boot instructions | 存储固件、BIOS、引导指令
Read/Write | 读写	Read and write | 可读可写	Typically read‑only (may be programmable) | 通常只读（可编程）

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10. Clock Speed, Cores and the FDE Cycle | 时钟频率、核心与 FDE 循环

Each tick of the system clock triggers one step of the FDE cycle—or a micro‑operation within a step. A 3.5 GHz CPU can theoretically complete 3.5 billion cycles per second. However, pipelining and multi‑core designs complicate this simple picture. Pipelining allows several instructions to overlap in different stages of the FDE cycle, much like an assembly line. With multiple cores, each core has its own PC, registers, and FDE cycle, enabling truly parallel instruction streams. The WJEC specification expects you to explain how clock speed or extra cores can increase the number of instructions completed per second.

系统时钟的每一次跳变触发 FDE 循环的一步——或一步中的一个微操作。3.5 GHz 的 CPU 理论上一秒可完成 35 亿个周期。但流水线和多核设计让这幅简单图像变得复杂。流水线允许多条指令在 FDE 循环的不同阶段重叠，类似装配线。多核架构下，每个核心拥有独立的 PC、寄存器和 FDE 循环，从而实现真正的并行指令流。WJEC 大纲要求你能解释时钟频率或额外核心如何提高每秒完成的指令数。

• Pipelining: while one instruction is being executed, another is being decoded, and a third is being fetched. | 流水线：一条指令执行时，另一条正在解码，还有一条正在取指。

• Multi‑core: each core can run a separate program or thread, reducing the need for context switching. | 多核：每个核心可运行不同的程序或线程，减少上下文切换的需求。

• Parallelism is limited by data dependencies and the fraction of code that can be executed simultaneously (Amdahl’s law). | 并行受限于数据依赖以及可同时执行的代码比例（阿姆达尔定律）。

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11. Interrupts and the FDE Cycle | 中断与 FDE 循环

An interrupt is a signal that temporarily halts the normal FDE cycle so the CPU can handle an urgent event—such as a key press, a moving mouse, or a completed disk read. When an interrupt occurs, the CPU saves its current state (typically the PC and registers) onto the stack, then jumps to a dedicated interrupt service routine (ISR). After the ISR finishes, the saved state is restored and the original program resumes exactly where it left off. Interrupts enable multitasking and make computers responsive to external input without wasteful polling.

中断是一种信号，它会暂时停下正常的 FDE 循环，让 CPU 去处理紧急事件——例如按键、鼠标移动或磁盘读取完成。当中断发生时，CPU 把当前状态（通常是 PC 和寄存器）保存到栈中，然后跳转到专门的中断服务程序 (ISR)。ISR 完成后，恢复保存的状态，原程序从断点处继续执行。中断机制让多任务成为可能，使计算机无需浪费轮询即可对外部输入作出响应。

• Hardware interrupts come from devices; software interrupts are triggered by programs (e.g., divide‑by‑zero). | 硬件中断来自外设；软件中断由程序触发（如除以零）。

• Priorities determine which interrupt gets serviced first when multiple occur simultaneously. | 优先级决定同时发生多个中断时先处理哪一个。

• The stack stores return addresses so that nested interrupts can be handled cleanly. | 栈保存返回地址，以便干净地处理嵌套中断。

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12. Summary and Exam Tips | 总结与应试技巧

Computer architecture questions in WJEC IGCSE papers require precise use of terminology. Always name registers correctly, describe the flow of data in the FDE cycle step by step, and link performance factors to real technical mechanisms—not vague statements like ‘faster is better’. Use diagrams in your explanations if they help, but ensure you can describe every stage in words. Compare embedded and general‑purpose systems by highlighting dedicated function vs. flexibility, resource constraints, and typical examples. Finally, revise common bus widths and their implications: a 32‑bit address bus can address 2³² memory locations, which equals 4 GiB of address space.

在 WJEC IGCSE 考卷中，计算机体系结构试题要求准确使用术语。务必正确命名寄存器，逐步描述 FDE 循环中的数据流动，并将性能因素与实际技术机制相联系——而非简单一句“更快就更好”。如果图表有助于理解，不妨画图辅助，但要保证能用文字完整描述每一阶段。对比嵌入式系统与通用系统时，突出专用功能与灵活性、资源限制和典型实例。最后，复习常见总线宽度及其含义：32 位地址总线可寻址 2³² 个内存单元，即 4 GiB 的地址空间。

• Always distinguish between MAR (address) and MDR (data) – a classic exam trap. | 务必区分 MAR（地址）和 MDR（数据）——这是经典考题陷阱。

• Explain why cache improves speed: temporal and spatial locality of reference. | 解释缓存为何能提速：引用的时间局部性和空间局部性。

• Be prepared to label a simple CPU block diagram or fill in register values during an FDE cycle. | 做好标记 CPU 简单框图或填写 FDE 循环中寄存器值的准备。

• Relate each component to its function in the FDE cycle. | 将每个部件与其在 FDE 循环中的功能联系起来。

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