Standard Logic Gate Symbols | 标准逻辑门符号

📚 Standard Logic Gate Symbols | 标准逻辑门符号

Logic gates are the fundamental building blocks of digital electronics. In the Cambridge IGCSE Science syllabus, you are required to recognise and draw the standard symbols for six basic logic gates, understand their truth tables, and apply them to simple circuits. This article systematically covers every gate with its symbol, truth table, and key exam-focused notes.

逻辑门是数字电子的基本构建模块。在剑桥IGCSE科学考纲中，要求你识别并绘制六种基本逻辑门的标准符号，理解它们的真值表，并能将其应用于简单电路。本文系统涵盖每一种逻辑门的符号、真值表以及考试要点。

1. The AND Gate | 与门

The AND gate has two or more inputs and one output. The output is 1 (HIGH) only when ALL inputs are 1. Its symbol features a flat left side and a curved right side (D-shape).

与门有两个或更多输入和一个输出。只有当所有输入均为1（高电平）时，输出才为1。其符号特征是左侧平直、右侧弧形（D形）。

A AND B = Q → Q = A · B

In IGCSE examinations, the AND gate is often tested with two inputs. Remember: “All inputs high gives high output.”

在IGCSE考试中，与门通常以两个输入的形式考查。记住：”所有输入为高，输出才为高。”

Input A	Input B	Output Q
0	0	0
0	1	0
1	0	0
1	1	1

A common exam question asks: “In a security system, two sensors ANDed together — what does this represent?” The answer: the alarm activates only when both conditions are true.

常见考题：”在安防系统中，两个传感器通过与门连接——这代表什么？”答案是：只有当两个条件同时满足时，警报才触发。

2. The OR Gate | 或门

The OR gate outputs 1 when ANY input is 1. Its symbol is similar to the AND gate but with a curved left side (concave) and a pointed right side.

或门在任一输入为1时输出为1。其符号与与门相似，但左侧为弧形（凹入），右侧为尖形。

A OR B = Q → Q = A + B

Key memory aid: “Any input high gives high output.” The only case where the output is 0 is when all inputs are 0.

关键记忆法：”任一输入为高，输出即为高。”唯一输出为0的情况是所有输入均为0。

Input A	Input B	Output Q
0	0	0
0	1	1
1	0	1
1	1	1

Application example: a hospital call button — pressing any one of several bedside buttons triggers a nurse’s alert. This is a classic OR gate scenario.

应用实例：医院呼叫按钮——按下任何一位病床旁的按钮均可触发护士提示。这是典型的或门场景。

3. The NOT Gate | 非门

The NOT gate has only ONE input and ONE output. It inverts the input: 0 becomes 1, and 1 becomes 0. Its symbol is a triangle with a small circle (bubble) at the output.

非门只有一个输入和一个输出。它将输入取反：0变为1，1变为0。其符号是一个三角形，输出端带一个小圆圈（气泡）。

NOT A = Q → Q = Ā

Examiners often ask: “How many inputs does a NOT gate have?” The answer: one. It is also described as an inverter.

考官常问：”非门有几个输入？”答案是：一个。它也被称为反相器。

Input A	Output Q
0	1
1	0

In circuit diagrams, the small circle (bubble) at the output always indicates inversion. Whenever you see a bubble, you know the signal is flipped.

在电路图中，输出端的小圆圈（气泡）始终表示取反。无论何时看到气泡，你就知道信号被翻转了。

4. The NAND Gate | 与非门

The NAND gate is the combination of an AND gate followed by a NOT gate. The output is the exact opposite of the AND gate: it outputs 0 only when ALL inputs are 1. Its symbol is the AND symbol with a bubble at the output.

与非门是与门后接非门的组合。其输出与门完全相反：仅当所有输入均为1时输出为0。其符号是与门符号在输出端加气泡。

Q = NOT (A · B)

NAND gates are called “universal gates” because any other gate can be constructed using only NAND gates. This is a common discussion point in IGCSE extensions.

与非门被称为”通用门”，因为仅用与非门就可以构建任何其他逻辑门。这是IGCSE拓展部分的常见讨论点。

Input A	Input B	Output Q
0	0	1
0	1	1
1	0	1
1	1	0

Examiner tip: memorise the NAND truth table by first recalling the AND table, then inverting every output value.

考官提示：记忆与非门真值表的方法是先回忆与门真值表，然后将每个输出值取反。

5. The NOR Gate | 或非门

The NOR gate is the combination of an OR gate followed by a NOT gate. It outputs 1 only when ALL inputs are 0. Its symbol is the OR symbol with a bubble at the output.

或非门是或门后接非门的组合。仅当所有输入均为0时输出为1。其符号是或门符号在输出端加气泡。

Q = NOT (A + B)

The NOR gate is also a universal gate. Remember: “All inputs low gives high output.”

或非门同样是通用门。记住：”所有输入为低，输出才为高。”

Input A	Input B	Output Q
0	0	1
0	1	0
1	0	0
1	1	0

In exam questions, you may be asked to identify a NOR gate from a list of symbols. The key identifier is the OR shape plus the output bubble.

在考题中，你可能会被要求从一组符号中识别或非门。关键识别特征是或门形状加上输出端气泡。

6. The XOR Gate | 异或门

The XOR (Exclusive OR) gate outputs 1 when the two inputs are DIFFERENT. It is like an OR gate, but it excludes the case where both inputs are 1. Its symbol is the OR symbol with an extra curved line on the input side.

异或门在两个输入不同时输出1。它类似于或门，但排除了两个输入都为1的情况。其符号是或门符号在输入端多一条弧形线。

Q = A ⊕ B

XOR gates are commonly tested in IGCSE. Memory aid: “Different inputs, high output; same inputs, low output.”

异或门在IGCSE中经常考查。记忆法：”输入不同，输出为高；输入相同，输出为低。”

Input A	Input B	Output Q
0	0	0
0	1	1
1	0	1
1	1	0

Real-world application: XOR gates are used in adder circuits and parity checking. When two bits are added, the sum bit is produced by an XOR gate.

实际应用：异或门用于加法电路和奇偶校验。当两个二进制位相加时，和位由异或门产生。

7. Drawing Standards | 绘图规范

Cambridge IGCSE requires you to draw logic gate symbols accurately. The symbols must follow the IEC (International Electrotechnical Commission) standard used in the syllabus.

剑桥IGCSE要求你准确绘制逻辑门符号。符号必须遵循考纲中使用的IEC（国际电工委员会）标准。

AND gate: flat input side, curved output side — no bubble

与门：输入端平直，输出端弯曲——无气泡
OR gate: curved input side, pointed output side — no bubble

或门：输入端弯曲，输出端尖形——无气泡
NOT gate: triangle with output bubble

非门：三角形加输出端气泡
NAND gate: AND shape plus output bubble

与非门：与门形状加输出端气泡
NOR gate: OR shape plus output bubble

或非门：或门形状加输出端气泡
XOR gate: OR shape plus extra curve on input side

异或门：或门形状加输入端额外弧形线

Labels: always label inputs (A, B) on the left and output (Q) on the right. Use straight lines for wires and avoid crossing wires where possible.

标注：始终在左侧标注输入（A、B），在右侧标注输出（Q）。连线使用直线，尽可能避免交叉。

8. Truth Tables in Exams | 考试中的真值表

Truth tables are the most frequently tested element of logic gates. You must be able to construct one from a given symbol, and identify a gate from a given truth table.

真值表是逻辑门最常考查的内容。你必须能够根据给定符号构建真值表，也能根据给定的真值表识别逻辑门。

A general strategy for construction: list all possible input combinations in binary order (00, 01, 10, 11 for two inputs), then compute the output for each row.

构建真值表的一般策略：按二进制顺序列出所有可能的输入组合（两个输入为00、01、10、11），然后计算每一行的输出。

Number of rows = 2ⁿ, where n = number of inputs

行数 = 2ⁿ，其中 n = 输入个数

Most IGCSE questions use 2-input gates (4 rows). Three-input gates have 8 rows and may appear in extended (supplement) papers.

大多数IGCSE题目使用双输入门（4行）。三输入门有8行，可能出现在拓展（补充）试卷中。

9. Combined Logic Circuits | 组合逻辑电路

IGCSE questions often combine multiple gates into a single circuit. You need to trace the signal flow from inputs to output, writing intermediate values at each connection point.

IGCSE题目经常将多个逻辑门组合成单一电路。你需要追踪从输入到输出的信号流，在每个连接点写出中间值。

Example scenario: two AND gates feeding into an OR gate. First compute each AND output, then feed both results into the OR gate.

示例场景：两个与门接入一个或门。先计算每个与门的输出，然后将两个结果输入或门。

A systematic approach is to draw a “signal table”: list each input combination, then write the output of each intermediate gate column by column.

系统化方法是绘制”信号表”：列出每种输入组合，然后逐列写出每个中间门的输出。

Examiner tip: always show intermediate steps in your working. Even if the final answer is wrong, you may receive partial credit for correct intermediate values.

考官提示：在解题过程中始终展示中间步骤。即使最终答案错误，正确的中间值也可能为你赢得部分分数。

10. Circuit Symbols and Pin Numbers | 电路符号与引脚编号

Occasionally, IGCSE questions refer to 7400-series IC chips. For example, the 7400 chip contains four NAND gates; the 7402 contains four NOR gates; the 7408 contains four AND gates; the 7432 contains four OR gates; the 7486 contains four XOR gates.

偶尔，IGCSE题目会提及7400系列集成电路芯片。例如：7400芯片包含四个与非门；7402包含四个或非门；7408包含四个与门；7432包含四个或门；7486包含四个异或门。

Each gate has a standard pin-out diagram, but in IGCSE you are only expected to know the logic behaviour and gate symbols — not the physical pin numbers.

每个门都有标准的引脚排列图，但在IGCSE中你只需掌握逻辑行为和门符号——不需要记忆物理引脚编号。

However, you should be able to state that a logic gate has a power supply (VCC and GND) and that outputs are connected to other components or gates.

然而，你应该能够说明逻辑门具有电源（VCC和GND），且输出连接到其他元件或逻辑门。

11. Practical Applications | 实际应用

Cambridge IGCSE paper questions often ask you to suggest a practical application for a logic circuit. This tests your understanding of the gate’s behaviour, not just its symbol.

剑桥IGCSE试卷题目经常要求你为某个逻辑电路提出实际应用。这考查的是你对逻辑门行为的理解，而不仅仅是符号。

AND gate: safety interlock — a machine operates only when both a safety guard is closed AND a start button is pressed

与门：安全联锁——只有当安全护罩关闭且启动按钮被按下时，机器才运行
OR gate: alarm system — a warning sounds when any one of several sensors is triggered

或门：报警系统——当多个传感器中任何一个被触发时，警报响起
NOT gate: automatic night light — a light turns on when a light sensor detects darkness (signal inverted)

非门：自动夜灯——当光线传感器检测到黑暗时灯亮起（信号取反）
NAND gate: warning indicator — turns off only when all safety conditions are met

与非门：警告指示灯——仅当所有安全条件满足时才熄灭
XOR gate: staircase light switch — two switches control one light; flipping either switch changes the light state

异或门：楼梯照明开关——两个开关控制一盏灯；拨动任一开关都会改变灯的状态

When writing applications, always mention both the input conditions and the resulting output. Full sentences score better than single words.

描述应用时，务必同时说明输入条件和相应输出。完整句子比单个词语得分更高。

12. Revision Checklist and Exam Tips | 复习清单与应考技巧

Before entering the exam hall, ensure you can confidently complete every item on this checklist.

进入考场前，请确保你能自信地完成清单上的每一项。

I can draw all six standard gate symbols from memory

我能凭记忆绘制所有六种标准逻辑门符号
I can state the truth table for each gate without hesitation

我能毫不犹豫地写出每种逻辑门的真值表
I can recognise a gate from its symbol or from its truth table

我能根据符号或真值表识别逻辑门
I can trace signal flow through combined circuits with multiple gates

我能追踪信号通过多门组合电路
I can construct a truth table for a combined circuit with up to 3 inputs

我能为最多3个输入的组合电路构建真值表
I can suggest practical applications for each type of gate

我能为每种逻辑门提出实际应用

Three common exam traps to avoid: (1) forgetting the output bubble on NAND/NOR gates; (2) confusing AND with OR when reading word descriptions such as “both” vs “either”; (3) missing the XOR row where both inputs equal 1 giving output 0.

三个常见的考试陷阱需要避免：（1）忘记NAND/NOR门输出端的气泡；（2）在阅读文字描述时将AND与OR混淆，如”两者都”与”任一”；（3）遗漏XOR门中两个输入均为1时输出为0的行。

Finally, practise writing the symbols by hand repeatedly. In the exam, drawing a clean and recognisable symbol takes less than 5 seconds — but a messy symbol may cost you marks.

最后，反复手绘这些符号。在考试中，绘制一个清晰可辨的符号只需不到5秒——但一个潦草的符号可能会让你丢分。

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Standard Logic Gate Symbols | 标准逻辑门符号