Core Components and Working Principles of Computer Architecture | 计算机体系结构核心组成与工作原理

📚 Core Components and Working Principles of Computer Architecture | 计算机体系结构核心组成与工作原理

Computer architecture is the study of how the components of a computer system are organised and how they work together to execute instructions and process data. For the CIE Computer Science syllabus, understanding the central processing unit (CPU), memory, buses, and the instruction cycle is essential.

计算机体系结构研究计算机系统的各组件如何组织、如何协同工作以执行指令和处理数据。在 CIE 计算机科学考纲中，理解中央处理器（CPU）、存储器、总线以及指令周期是核心考点。

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1. Von Neumann Architecture | 冯·诺依曼体系结构

The Von Neumann architecture, proposed by John von Neumann in the late 1940s, describes a system where program instructions and data are both stored in the same memory unit. This stored-program concept means that both instructions and data are fetched and processed using a single set of buses.

冯·诺依曼体系结构由约翰·冯·诺依曼于 20 世纪 40 年代末提出。在该结构中，程序指令和数据都存储在同一内存单元中。这种“存储程序”概念意味着指令和数据共用一组总线进行取用和处理。

• Single memory space for both instructions and data | 指令和数据共用单一存储空间

• Sequential execution of instructions | 指令按顺序逐条执行

• The CPU alternates between fetching instructions and fetching data | CPU 在取指令与取数据之间交替工作

A key consequence of this design is the Von Neumann bottleneck: because instructions and data share the same bus, the rate of data transfer becomes a limiting factor on overall system performance.

该设计的一个关键后果是冯·诺依曼瓶颈：由于指令和数据共用同一条总线，数据传输速率成为制约系统整体性能的因素。

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2. Main Memory and Storage Hierarchy | 主存储器与存储层次结构

Main memory, also known as random-access memory (RAM), is a volatile storage medium that holds data and instructions while the computer is running. It is organised as a sequence of addressable cells, each with a unique address.

主存储器，即随机存取存储器（RAM），是一种易失性存储介质，在计算机运行时保存数据和指令。它以一系列可寻址单元的形式组织，每个单元有唯一地址。

• Volatile: contents are lost when power is removed | 易失性：断电后内容丢失

• Directly accessible by the CPU | CPU 可直接访问

• Much faster than secondary storage such as hard disks | 速度远快于硬盘等辅助存储器

The storage hierarchy places faster but smaller memory closer to the CPU. Cache memory sits between the CPU and RAM, holding frequently accessed instructions and data to reduce the average time needed to access memory.

存储层次结构将速度更快但容量更小的存储器安排在靠近 CPU 的位置。缓存存储器位于 CPU 与 RAM 之间，保存频繁访问的指令和数据，以缩短平均内存访问时间。

Access Time: Register < Cache < RAM < Secondary Storage

访问时间：寄存器 < 缓存 < RAM < 辅助存储器

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3. Arithmetic and Logic Unit | 算术逻辑单元

The Arithmetic and Logic Unit (ALU) is the part of the CPU that carries out arithmetic operations, such as addition and subtraction, as well as logical operations, such as AND, OR, and NOT. It also performs comparison operations that determine relationships between values.

算术逻辑单元（ALU）是 CPU 中执行算术运算（如加法和减法）和逻辑运算（如 AND、OR、NOT）的部件，还执行比较操作以判断数值之间的关系。

• Arithmetic operations: ADD, SUBTRACT, MULTIPLY, DIVIDE | 算术运算：加、减、乘、除

• Logical operations: AND, OR, XOR, NOT | 逻辑运算：与、或、异或、非

• Comparison operations: compare two values and set status flags | 比较运算：比较两个值并设置状态标志

The ALU works with the accumulator, a special register that stores the result of an operation. For example, to add two numbers, one operand is loaded into the accumulator, the second operand is provided by another register or memory location, and the ALU computes the sum, replacing the accumulator’s previous value.

ALU 与累加器配合工作。累加器是一个特殊寄存器，用于存储运算结果。例如，两个数相加时，先将一个操作数装入累加器，另一个操作数由其他寄存器或存储单元提供，ALU 计算和并将结果存入累加器，覆盖其原值。

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4. Control Unit | 控制单元

The Control Unit (CU) coordinates the activities of the CPU. It does not process data itself; instead, it directs the flow of data between the CPU and other components, and orchestrates the fetch–decode–execute cycle.

控制单元（CU）协调 CPU 的各项活动。它本身不处理数据，而是负责引导 CPU 与其他组件之间的数据流动，并统筹取指–译码–执行周期。

• Controls the system clock and timing of operations | 控制系统时钟和操作时序

• Decodes instructions and generates control signals | 译码指令并生成控制信号

• Manages the sequence of fetching, decoding, and executing instructions | 管理取指、译码和执行指令的顺序

The CU sends control signals to the ALU, registers, memory, and input/output devices, ensuring that each component acts at the correct moment in the instruction cycle. These signals are synchronised by the clock generator, which produces a continuous stream of pulses.

CU 向 ALU、寄存器、存储器和输入输出设备发送控制信号，确保每个组件在指令周期中正确的时刻动作。这些信号由时钟发生器同步，时钟产生连续的脉冲序列。

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5. Registers and Their Functions | 寄存器及其功能

Registers are small, high-speed storage locations inside the CPU. They hold data and addresses temporarily and operate at the same speed as the CPU itself, which makes them significantly faster than main memory.

寄存器是 CPU 内部容量小、速度高的存储单元。它们临时保存数据和地址，以与 CPU 相同的速度工作，因此明显快于主存储器。

Register | 寄存器	Function | 功能
Program Counter (PC)	Holds the address of the next instruction to be fetched | 保存下一条待取指令的地址
Memory Address Register (MAR)	Holds the address of the memory location currently being accessed | 保存当前正在访问的内存单元地址
Memory Data Register (MDR)	Holds data or instructions being transferred between memory and CPU | 保存内存与 CPU 之间传输的数据或指令
Current Instruction Register (CIR)	Stores the instruction currently being decoded and executed | 存储当前正在译码和执行的指令
Accumulator (ACC)	Stores the result of operations performed by the ALU | 存储 ALU 执行运算后的结果
Index Register (IX)	Used in indexed addressing to calculate effective addresses | 用于变址寻址以计算有效地址

During the fetch stage, the PC provides the address of the next instruction, which is copied into the MAR. The memory is then read, and the instruction is transferred to the MDR and then to the CIR for decoding. Meanwhile, the PC is incremented to point to the next instruction.

在取指阶段，PC 提供下一条指令的地址并复制到 MAR。随后读取内存，指令被送入 MDR，再传送到 CIR 进行译码。与此同时，PC 递增以指向下一条指令。

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6. The Fetch–Decode–Execute Cycle | 取指–译码–执行周期

The instruction cycle is the fundamental sequence of steps that the CPU follows to process each instruction. It is often called the fetch–decode–execute cycle and consists of three main stages.

指令周期是 CPU 处理每条指令所遵循的基本步骤序列，通常称为取指–译码–执行周期，包含三个主要阶段。

Stage 1: Fetch | 第一阶段：取指

The address held in the PC is copied into the MAR. The control unit issues a read signal, causing the memory to place the instruction on the data bus. The instruction travels from memory through the MDR to the CIR, and the PC is incremented.

PC 中的地址被复制到 MAR。控制单元发出读信号，使内存将指令放到数据总线上。指令经 MDR 传送至 CIR，同时 PC 递增。

Stage 2: Decode | 第二阶段：译码

The control unit examines the opcode (operation code) in the CIR to determine what operation is required. It identifies the operands and the addressing mode used, and prepares the necessary control signals.

控制单元检查 CIR 中的操作码，判断需要执行什么操作，确定操作数和所用的寻址方式，并准备相应的控制信号。

Stage 3: Execute | 第三阶段：执行

The ALU performs arithmetic or logical operations, data is moved between registers and memory, or the sequence of execution is altered by a branch, depending on the decoded instruction.

ALU 执行算术或逻辑运算，数据在寄存器与内存之间移动，或根据译码后的指令发生跳转以改变执行顺序。

Fetch → Decode → Execute → Repeat | 取指 → 译码 → 执行 → 重复

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7. System Buses and Data Transfer | 系统总线与数据传输

A bus is a set of parallel wires or pathways that transmits data, addresses, or control signals between components of the computer. The three main buses are the address bus, data bus, and control bus.

总线是一组并行导线或通路，用于在计算机各组件之间传输数据、地址或控制信号。三大总线是地址总线、数据总线和控制总线。

Bus | 总线	Direction | 方向	Purpose | 用途
Address bus | 地址总线	Unidirectional | 单向	Carries addresses from CPU to memory or I/O devices | 从 CPU 向内存或 I/O 设备传输地址
Data bus | 数据总线	Bidirectional | 双向	Transfers data between CPU and memory or I/O | 在 CPU 与内存或 I/O 之间传输数据
Control bus | 控制总线	Bidirectional | 双向	Carries control signals such as read, write, and interrupt | 传输读、写、中断等控制信号

The width of the address bus determines the maximum addressable memory: if the address bus has n lines, the CPU can address up to 2ⁿ memory locations. The width of the data bus determines how many bits can be transferred at once — a 64-bit data bus transfers 8 bytes simultaneously.

地址总线的宽度决定最大可寻址内存空间：若地址总线有 n 条线，CPU 最多可寻址 2ⁿ 个存储单元。数据总线的宽度决定一次可传输的位数——64 位数据总线一次传输 8 字节。

Max Memory = 2^n bytes (where n = address bus width)

最大内存 = 2ⁿ 字节（n 为地址总线宽度）

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8. Clock Speed and Performance | 时钟速度与性能

The system clock generates a series of electrical pulses that synchronise the operations of the CPU. Clock speed is measured in hertz (Hz), which represents the number of cycles per second. Modern processors operate at speeds measured in gigahertz (GHz), meaning billions of cycles per second.

系统时钟产生一系列电脉冲，用于同步 CPU 的各项操作。时钟速度以赫兹（Hz）为单位，表示每秒钟的周期数。现代处理器的工作速度以吉赫（GHz）为单位，即每秒数十亿个周期。

• Higher clock speed generally means more instructions executed per second | 更高的时钟速度通常意味着每秒执行更多指令

• Performance is also affected by the number of cores, cache size, and bus width | 性能还受核心数、缓存容量和总线宽度影响

• Pipelining allows multiple instructions to be processed at different stages simultaneously | 流水线技术允许多条指令同时处于不同处理阶段

It is important to note that clock speed on its own is not a reliable measure of performance. Two processors with the same clock speed can perform differently because of differing microarchitectures, cache sizes, and instruction sets.

需要注意，时钟速度本身不是衡量性能的可靠指标。两款时钟速度相同的处理器可能因微架构、缓存大小和指令集不同而性能各异。

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9. Pipelining | 流水线技术

Pipelining is a technique that improves CPU throughput by overlapping the execution of multiple instructions. Instead of waiting for one instruction to complete before fetching the next, the CPU can fetch, decode, and execute several instructions at different stages at the same time.

流水线是一种通过重叠多条指令的执行来提高 CPU 吞吐量的技术。CPU 无需等待一条指令完成再取下一条，而可以同时让不同指令处于取指、译码、执行的不同阶段。

I₁: Fetch → Decode → Execute → Write-back

I₂: Fetch → Decode → Execute → Write-back

I₃: Fetch → Decode → Execute → Write-back

In an ideal pipeline with k stages, the time to complete each instruction is reduced to approximately one-kth of the non-pipelined time, although the latency of each individual instruction remains the same. Hazards, such as data dependencies or branch jumps, can cause pipeline stalls.

在理想的 k 级流水线中，每条指令完成所需的时间大约降低为非流水线时间的 k 分之一，尽管单条指令的延迟保持不变。数据相关或分支跳转等冒险可能导致流水线停滞。

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10. Harvard Architecture | 哈佛体系结构

The Harvard architecture is a computer architecture that uses physically separate storage and separate buses for instructions and data. This differs from the Von Neumann architecture, where instructions and data share one memory and one bus.

哈佛体系结构是一种指令和数据使用物理分离的存储空间及独立总线的计算机体系结构。这与指令和数据共用存储空间和总线的冯·诺依曼结构不同。

• Separate memory units for instructions and data | 指令和数据分别使用独立存储器

• Separate buses allow simultaneous access to instructions and data | 独立总线允许同时访问指令和数据

• Commonly used in microcontrollers and digital signal processors | 常用于微控制器和数字信号处理器

Because the CPU can fetch an instruction and read or write data at the same time, the Harvard architecture can achieve higher throughput. However, it is more complex and expensive to implement than the Von Neumann architecture.

由于 CPU 可以同时取指令和读写数据，哈佛体系结构可以获得更高的吞吐量。但它的实现比冯·诺依曼结构更复杂、成本更高。

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11. CISC and RISC Processors | 复杂指令集与精简指令集处理器

Complex Instruction Set Computer (CISC) and Reduced Instruction Set Computer (RISC) represent two contrasting design philosophies for CPU instruction sets.

复杂指令集计算机（CISC）和精简指令集计算机（RISC）代表了 CPU 指令集设计的两种对立理念。

Feature | 特征	CISC	RISC
Instruction complexity | 指令复杂度	Complex, multi-step instructions | 复杂、多步指令	Simple, single-cycle instructions | 简单、单周期指令
Instruction length | 指令长度	Variable length | 可变长度	Fixed length | 固定长度
Addressing modes | 寻址方式	Large number | 数量多	Small number | 数量少
Examples | 实例	x86 processors | x86 处理器	ARM processors | ARM 处理器

RISC processors reduce the complexity of the instruction set to allow for simpler hardware, which enables pipelining and higher clock speeds. CISC processors aim to reduce the number of instructions per program by making individual instructions more powerful.

RISC 处理器通过简化指令集来实现更简单的硬件，从而支持流水线和更高的时钟速度。CISC 处理器则试图通过使单条指令更强大来减少程序中的指令条数。

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12. Input/Output and Interrupts | 输入/输出与中断

Input/output (I/O) devices allow the computer to communicate with the outside world. Input devices include keyboards and mice, while output devices include monitors and printers. I/O controllers act as interfaces between the CPU, main memory, and peripheral devices.

输入/输出（I/O）设备使计算机能与外部世界通信。输入设备包括键盘和鼠标，输出设备包括显示器和打印机。I/O 控制器充当 CPU、主存储器与外设之间的接口。

An interrupt is a signal sent to the CPU by an I/O device or software to request attention. When the CPU receives an interrupt, it suspends its current task, saves the current state of the registers (often on the system stack), and transfers control to an interrupt service routine (ISR). After the ISR finishes, the CPU restores the saved state and resumes the original task.

中断是 I/O 设备或软件发送给 CPU 的一种信号，请求 CPU 予以关注。CPU 收到中断后，挂起当前任务，将寄存器当前状态保存到系统栈中，并将控制转移到中断服务例程（ISR）。ISR 执行完毕后，CPU 恢复保存的状态，继续原来的任务。

• Interrupts allow the CPU to respond to events asynchronously | 中断使 CPU 能异步响应事件

• Polling is an alternative to interrupts but wastes CPU time | 轮询是中断的替代方案，但会浪费 CPU 时间

• Interrupt priorities ensure that critical devices are served first | 中断优先级确保关键设备优先得到服务

Mastery of these fundamental topics — the CPU components, the instruction cycle, buses, and the architectural distinctions — forms the basis for solving examination questions on computer architecture in CIE Computer Science.

掌握这些基础主题——CPU 组件、指令周期、总线以及体系结构之间的区别——是解答 CIE 计算机科学考试中计算机体系结构题目的基础。

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