Core Exam Points in Computer Hardware | 计算机硬件核心考点精讲

📚 Core Exam Points in Computer Hardware | 计算机硬件核心考点精讲

This article covers the essential hardware topics you need for the CIE A-Level Computer Science exam: CPU architecture, registers, buses, memory, input/output, and how instructions are executed. We explain each point in English and Chinese side by side, with exam-focused clarity.

本文专为 CIE A-Level 计算机科学考生整理计算机硬件核心考点，包括 CPU 结构、寄存器、总线、存储器、输入输出以及指令执行过程。每个要点均采用中英对照讲解，帮助你在考试中快速抓住得分点。

1. Von Neumann Architecture | 冯·诺依曼体系结构

Von Neumann architecture stores both data and instructions in the same memory, using a single bus for both. The CPU fetches instructions from memory, decodes them, and then executes them sequentially.

冯·诺依曼体系结构将数据和指令存储在同一个存储器中，并通过单一总线访问两者。CPU 从存储器取出指令，进行译码，然后按顺序执行。

Key registers: Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), Accumulator (ACC), Current Instruction Register (CIR).

关键寄存器：程序计数器（PC）、存储器地址寄存器（MAR）、存储器数据寄存器（MDR）、累加器（ACC）、当前指令寄存器（CIR）。
Key buses: Address bus, data bus, control bus.

关键总线：地址总线、数据总线、控制总线。

PC → MAR → Memory → MDR → CIR → Decode → Execute

This fetch-decode-execute cycle is the underlying operation of all stored-program computers.

取指-译码-执行周期是所有存储程序计算机的基本工作过程。

2. CPU Registers and Their Roles | CPU 寄存器及其作用

Each register has a specific function. You must be able to describe what each one does in the fetch-decode-execute cycle.

每个寄存器都有特定功能。你必须能够描述它们在取指-译码-执行周期中的作用。

Register	Function	中文功能
PC	Holds the address of the next instruction to be fetched.	存储下一条要取出指令的地址。
MAR	Holds the address of memory location currently being accessed.	存储当前正在访问的存储器地址。
MDR	Holds data transferred between memory and CPU.	暂存存储器与 CPU 之间传输的数据。
ACC	Stores intermediate results of arithmetic/logic operations.	存储算术逻辑运算的中间结果。
CIR	Holds the current instruction being decoded and executed.	保存当前正在译码和执行的指令。

In the fetch stage, the address in the PC is copied to the MAR. Then the PC is incremented to point to the next instruction.

在取指阶段，PC 中的地址被复制到 MAR，随后 PC 自增以指向下一条指令。

3. Buses: Address, Data, Control | 总线：地址、数据、控制

A bus is a set of parallel wires that carry data or control signals between components. The width of a bus affects system performance.

总线是一组并行导线，用于在部件之间传输数据或控制信号。总线宽度会影响系统性能。

Address bus: carries memory addresses from CPU to memory or I/O. It is unidirectional.

地址总线：用于 CPU 向存储器或 I/O 传输地址，是单向的。
Data bus: carries actual data between CPU, memory, and I/O. It is bidirectional.

数据总线：在 CPU、存储器和 I/O 之间传输实际数据，是双向的。
Control bus: carries control signals such as read/write, clock, and interrupt requests. It is bidirectional.

控制总线：传输读写、时钟、中断请求等控制信号，是双向的。

If the address bus has n lines, the CPU can address up to 2ⁿ memory locations.

如果地址总线有 n 条线，CPU 最多可以寻址 2ⁿ 个存储单元。

4. Fetch-Decode-Execute Cycle | 取指-译码-执行周期

You must know the exact steps of the cycle and the state of each register after each step.

你需准确掌握该周期的每一步以及每步之后各寄存器的状态。

Fetch: PC → MAR → Memory → MDR → CIR; PC = PC + 1

During fetch, the instruction is copied from memory into the CIR. The PC is then incremented.

取指阶段，指令从存储器复制到 CIR，PC 随后加 1。

Decode: examine the opcode in CIR to determine what operation is required.

译码阶段：检查 CIR 中的操作码，确定需要执行什么操作。

Execute: carry out the operation, possibly involving ACC and MAR/MDR.

执行阶段：完成该操作，可能涉及 ACC 以及 MAR/MDR。

Questions often ask: “What is the purpose of the PC increment?” The answer is to prepare the address of the next instruction for the next fetch.

常见问题：”PC 自增的目的是什么？”答案是：为下一次取指准备好下一条指令的地址。

5. Core and Multicore Processors | 核心与多核处理器

A processor core consists of the ALU, control unit, and registers. A multicore processor contains two or more independent cores on a single chip.

一个处理器核心由 ALU、控制单元和寄存器组成。多核处理器在单个芯片上包含两个或更多独立核心。

Advantage: multiple tasks or threads can run in parallel, improving throughput.

优点：多个任务或线程可以并行运行，提高吞吐量。
Limitation: not all software is written to use multiple cores; clock speed per core may be lower.

限制：并非所有软件都能利用多核；每个核心的时钟频率可能较低。

In exams, distinguish between “parallelism” and “concurrency” and explain why a single-core CPU with high clock speed can still outperform a slower multicore CPU for sequential tasks.

考试中要区分”并行”和”并发”，并解释为什么对于顺序任务，高时钟频率的单核 CPU 可能比慢速多核 CPU 更快。

6. Memory: RAM, ROM, and Cache | 存储器：RAM、ROM 与缓存

RAM is volatile, used for currently running programs and data. ROM is non-volatile, often used for boot code. Cache is small, fast memory between CPU and RAM.

RAM 是易失性存储器，用于存放当前运行的程序和数据。ROM 是非易失性存储器，常用于启动代码。缓存是位于 CPU 与 RAM 之间的小容量高速存储器。

Feature	RAM	ROM	Cache
Volatile?	Yes	No	Yes (usually)
Writable?	Yes	No or slow	Yes
Speed	Fast	Fast	Very fast
Purpose	Main memory	Boot firmware	Speed up access

Cache memory stores frequently used instructions and data to reduce the average time to access main memory.

缓存存储频繁使用的指令和数据，以减少访问主存储器的平均时间。

7. Memory Addresses and Direct/Indirect Addressing | 存储器地址与直接/间接寻址

In direct addressing, the operand is the actual memory address of the data. In indirect addressing, the operand is a memory address that contains another address pointing to the data.

直接寻址中，操作数就是数据的实际内存地址。间接寻址中，操作数是一个内存地址，该地址中存储着另一个指向数据的地址。

Direct: LOAD 500 → ACC = Memory[500]

Indirect: LOAD (500) → ACC = Memory[Memory[500]]

Indirect addressing allows greater flexibility but requires more memory accesses and is slower.

间接寻址更灵活，但需要更多次访问内存，速度更慢。

8. Input and Output Devices | 输入与输出设备

Input devices convert external data into a form the computer can process. Output devices convert computer data into human-readable or machine-usable forms.

输入设备将外部数据转换为计算机可处理的形式。输出设备将计算机数据转换为人类可读或机器可用的形式。

Sensors: measure physical quantities (temperature, pressure, light) and produce analogue signals, which are converted to digital by an ADC.

传感器：测量物理量（温度、压力、光）并产生模拟信号，由 ADC 转换为数字信号。
Actuators: receive digital signals and cause physical movement in control systems.

执行器：接收数字信号并在控制系统中产生物理动作。
Common output devices: monitors, printers, speakers.

常见输出设备：显示器、打印机、扬声器。

Be prepared to explain the role of ADC and DAC in a computer control system.

要能解释 ADC 和 DAC 在计算机控制系统中的作用。

9. Interrupts and Handling | 中断与中断处理

An interrupt is a signal that causes the CPU to temporarily stop its current activity and execute an interrupt service routine (ISR).

中断是一种信号，使 CPU 暂时停止当前活动，转去执行中断服务程序（ISR）。

Interrupt → Save current state → Run ISR → Restore state → Resume

When an interrupt occurs, the CPU saves the current PC and register contents (often on a stack), then loads the address of the ISR.

中断发生时，CPU 保存当前 PC 和寄存器内容（通常压入栈中），然后加载 ISR 的地址。

Examples of interrupts include I/O completion, timer signals, and hardware errors.

中断的例子包括 I/O 完成、定时器信号以及硬件错误。

10. Impact of Hardware on Performance | 硬件对性能的影响

Several hardware factors affect CPU performance: clock speed, cache size, number of cores, bus width, and RAM size.

影响 CPU 性能的硬件因素包括：时钟频率、缓存大小、核心数量、总线宽度和 RAM 大小。

Higher clock speed → more fetch-decode-execute cycles per second.

较高的时钟频率 → 每秒更多取指-译码-执行周期。
Larger cache → more data available close to the CPU, reducing wait time.

更大缓存 → 更多数据靠近 CPU，减少等待时间。
More cores → parallel execution of independent tasks.

更多核心 → 独立任务可并行执行。
Wider data bus → more bits transferred per memory access.

更宽数据总线 → 每次内存访问传输更多位。

In CIE exams, always mention the trade-off: faster components usually cost more and may generate more heat.

在 CIE 考试中，务必提到权衡：更快的部件通常更贵，并可能产生更多热量。

11. Control Unit and ALU | 控制单元与 ALU

The control unit (CU) coordinates all CPU activities. It generates control signals and directs data flow between registers, ALU, and memory.

控制单元（CU）协调 CPU 的所有活动。它产生控制信号，并指引数据在寄存器、ALU 和存储器之间流动。

The ALU performs arithmetic operations (add, subtract) and logical operations (AND, OR, NOT, compare).

ALU 执行算术运算（加、减）和逻辑运算（AND、OR、NOT、比较）。

Component	Role	中文作用
CU	Generates timing and control signals	产生时序和控制信号
ALU	Performs arithmetic and logic	执行算术和逻辑运算

The status flags (carry, zero, negative, overflow) are set in a special register inside the CPU after ALU operations.

ALU 运算后，特殊寄存器中的状态标志（进位、零、负、溢出）会被设置。

12. Assembly Instructions in Hardware Context | 硬件语境下的汇编指令

Assembly language is a low-level programming language directly related to CPU instructions. CIE exams often give simple assembly programs using instructions like LDA, STA, ADD, SUB, JMP, IN, OUT, HLT.

汇编语言是一种与 CPU 指令直接相关的低级编程语言。CIE 考试常给出简单汇编程序，如 LDA、STA、ADD、SUB、JMP、IN、OUT、HLT 等指令。

LDA #10 → load the value 10 into ACC

ADD #5 → add 5 to ACC

Understand the difference between immediate addressing (#value) and direct addressing (memory address).

要理解立即寻址（#数值）与直接寻址（内存地址）的区别。

Practise tracing small programs and recording register/memory changes using trace tables.

练习使用跟踪表记录小型程序执行时寄存器和存储器的变化。

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Core Exam Points in Computer Hardware | 计算机硬件核心考点精讲