📚 IB & OCR Computer Science: Computer Architecture Key Points | IB OCR 计算机：计算机体系结构 考点精讲
Computer architecture is the backbone of every digital system, defining how a computer’s processor, memory, and input/output devices cooperate to execute programs. In IB and OCR A-Level Computer Science, mastering architecture concepts is vital for understanding performance, efficiency, and the hardware-software interface. This revision guide distils essential topics – from von Neumann fundamentals to pipelining, caching, and performance metrics – into clear, paired English–Chinese explanations that align with syllabus requirements.
计算机体系结构是每个数字系统的脊梁，它定义了处理器、存储器和输入/输出设备如何协同工作以执行程序。在 IB 和 OCR A-Level 计算机科学课程中，掌握体系结构概念对于理解性能、效率以及软硬件接口至关重要。本复习指南将核心考点——从冯·诺依曼基础到流水线、缓存及性能指标——提炼为清晰的中英双语讲解，贴合考纲要求。
1. Introduction to Computer Architecture | 计算机体系结构导论
Computer architecture refers to the logical design and functional behaviour of a computer system as seen by the programmer. It encompasses the instruction set, data types, addressing modes, and I/O mechanisms. A well-designed architecture balances performance, power consumption, and cost while maintaining compatibility with software ecosystems.
计算机体系结构指程序员视角下的计算机系统的逻辑设计和功能行为。它包含指令集、数据类型、寻址模式及 I/O 机制。一个精心设计的架构会在性能、功耗和成本之间取得平衡，同时保持与软件生态的兼容性。
The boundary between architecture (what the machine does) and microarchitecture (how the machine is built) is fundamental. IB and OCR syllabi expect you to distinguish between these layers and explain how architectural decisions affect program execution and hardware complexity.
体系结构（机器做什么）与微体系结构（机器如何构建）之间的界限是根本性的。 IB 与 OCR 考纲要求你区分这些层次，并解释体系结构决策如何影响程序执行和硬件复杂性。
2. Von Neumann Architecture | 冯·诺依曼架构
The von Neumann architecture stores both program instructions and data in a single, unified memory. A control unit fetches instructions sequentially, decodes them, and coordinates the ALU and registers to execute them. This stored-program concept allows computers to be reprogrammed simply by loading new instructions, without rewiring hardware.
冯·诺依曼架构将程序指令与数据存储于同一个统一的内存中。控制单元顺序取指、译码，并协调 ALU 和寄存器来执行指令。这种存储程序概念使得计算机只需加载新指令即可重新编程，而无需改动硬件连线。
A von Neumann machine typically contains a central processing unit (CPU) with an arithmetic logic unit (ALU), a control unit (CU), a set of registers, and a system bus connecting to memory and I/O. The bottleneck of this design – the shared bus for instructions and data – is known as the von Neumann bottleneck, which limits execution speed.
冯·诺依曼机器通常包含一个中央处理器（CPU），其中有算术逻辑单元（ALU）、控制单元（CU）、一组寄存器以及连接到内存和 I/O 的系统总线。该设计的瓶颈——指令和数据共享同一条总线——被称为冯·诺依曼瓶颈，它限制了执行速度。
3. CPU Components and Buses | CPU 组件与总线
Inside the CPU, key registers include the Program Counter (PC) holding the address of the next instruction, the Memory Address Register (MAR), the Memory Data Register (MDR), the Current Instruction Register (CIR), and the Accumulator (ACC). The ALU performs arithmetic and logic operations, while the Control Unit orchestrates data movement and decoding.
CPU 内部的关键寄存器包括：存放下一条指令地址的程序计数器（PC）、存储器地址寄存器（MAR）、存储器数据寄存器（MDR）、当前指令寄存器（CIR）和累加器（ACC）。ALU 执行算术与逻辑运算，而控制单元则协调数据移动与译码。
The system bus consists of three sub-buses: the address bus (unidirectional, carries memory addresses), the data bus (bidirectional, carries data), and the control bus (carries read/write signals, clock pulses, and interrupts). Wider buses increase data throughput, a concept examined in both IB and OCR questions on bus width and performance.
系统总线由三组构成：地址总线（单向，传送内存地址）、数据总线（双向，传送数据）以及控制总线（传送读写信号、时钟脉冲和中断）。更宽的总线能提高数据吞吐量，这是 IB 和 OCR 中有关总线宽度与性能的常见考点。
| Register | Function |
|---|---|
| PC | Holds address of next instruction |
| MAR | Holds address for memory access |
| MDR | Holds data being transferred to/from memory |
| CIR | Holds current instruction being decoded and executed |
Table: Essential CPU registers and their roles | 表格：主要 CPU 寄存器及其功能
4. The Fetch-Decode-Execute Cycle | 取指-解码-执行循环
The fetch-decode-execute (FDE) cycle is the fundamental operating loop of a processor. During the fetch phase, the address from the PC is copied to the MAR, a memory read is requested, and the instruction is placed into the MDR, then moved to the CIR. The PC is incremented to point to the next instruction.
取指-解码-执行（FDE）循环是处理器基本的工作循环。在取指阶段，PC 中的地址被复制到 MAR，发出内存读请求，指令被放入 MDR，再移入 CIR。PC 递增以指向下一条指令。
In the decode phase, the control unit interprets the opcode in the CIR and prepares the necessary data paths. During execute, the ALU or other functional units perform the required operation, which may involve reading operands from registers or memory, computing a result, and writing it back. The cycle repeats until a halt instruction is encountered.
在解码阶段，控制单元解读 CIR 中的操作码，并准备所需的数据通路。在执行阶段，ALU 或其他功能单元完成必要的操作，可能涉及从寄存器或存储器读取操作数、计算结果并写回。循环重复，直到遇到停机指令。
A pipeline can overlap these stages for different instructions, but in a single-cycle model, each instruction passes through FDE atomically. Understanding the detailed steps is essential for answering trace-table or timing-diagram questions in exams.
流水线可以将不同指令的这些阶段重叠，但在单周期模型中，每条指令原子式地经历取指-解码-执行。理解详细步骤对于解答考试中的追踪表或时序图问题至关重要。
5. Instruction Set Architecture | 指令集架构
An Instruction Set Architecture (ISA) defines the set of machine-level instructions a processor can execute. It specifies supported data types, registers, addressing modes, and the binary encoding of each instruction. The ISA acts as the contract between hardware and low-level software, including compilers.
指令集架构（ISA）定义了处理器可执行的机器级指令集合。它规定了支持的数据类型、寄存器、寻址模式以及每条指令的二进制编码。ISA 充当硬件与包括编译器在内的底层软件之间的契约。
Instructions typically consist of an opcode (operation) and one or more operands. Addressing modes such as immediate, direct, indirect, indexed, and relative dictate how operands are located. In OCR A-Level, you are expected to describe the LMC (Little Man Computer) model; IB similarly uses a simplified assembly language to illustrate instruction formats.
指令通常由操作码和若干操作数组成。立即、直接、间接、变址和相对等寻址模式决定了如何定位操作数。在 OCR A-Level 中，你需要描述 LMC（小人计算机）模型；IB 同样使用简化的汇编语言来说明指令格式。
Example: ADD R1, R2 // Add contents of R2 to R1 | 示例：ADD R1, R2 // 将 R2 的内容加到 R1
6. RISC vs CISC | 精简指令集与复杂指令集
RISC (Reduced Instruction Set Computer) architectures use a small set of simple, fixed-length instructions that can be executed in a single clock cycle. They employ a load-store model, where only dedicated load and store instructions access memory; all other operations work on registers. This uniformity simplifies pipelining and enables higher clock speeds.
RISC（精简指令集计算机）架构采用一小套简单、定长的指令，这些指令可在单个时钟周期内执行。它们采用加载-存储模型，即只有专用的加载和存储指令访问内存；其他所有操作均在寄存器上进行。这种一致性简化了流水线设计，并支持更高的时钟频率。
CISC (Complex Instruction Set Computer) architectures feature a rich set of variable-length instructions, some of which perform multi-step operations (e.g., string manipulation, complex memory addressing). CISC reduces the number of instructions per program, but complicates decoding and pipelining. Modern x86 processors internally translate CISC instructions into RISC-like micro-operations.
CISC（复杂指令集计算机）架构包含丰富的变长指令集，其中一些指令可执行多步操作（例如字符串处理、复杂的内存寻址）。CISC 减少了每条程序的指令数，但增加了解码和流水线的复杂性。现代 x86 处理器在内部将 CISC 指令翻译成类似 RISC 的微操作。
IB and OCR both require a comparison of RISC and CISC with respect to compiler complexity, power efficiency, and use cases (e.g., ARM in mobile devices vs. x86 in desktops). The trend is towards a hybrid approach that reaps the benefits of both philosophies.
IB 和 OCR 都要求比较 RISC 和 CISC 在编译器复杂性、功耗效率以及应用场景（如移动设备中的 ARM 与桌面端的 x86）方面的差异。趋势是采取混合方法来获得两种理念的优势。
7. Pipelining | 流水线技术
Pipelining decomposes instruction execution into discrete stages (e.g., fetch, decode, execute, memory access, write-back) and allows multiple instructions to overlap in time. An ideal k-stage pipeline can achieve up to k times the throughput of a non-pipelined processor, though hazards prevent perfect scaling.
流水线将指令执行分解为离散的阶段（例如取指、译码、执行、访存、写回），并使多条指令在时间上重叠。理想的 k 级流水线可实现高达非流水线处理器 k 倍的吞吐量，但冒险（hazards）阻止了完美的线性扩展。
Hazards are classified as structural (resource conflicts), data (dependencies between instructions), and control (branch mispredictions). Techniques like forwarding (data bypass), branch prediction, and compiler scheduling mitigate their impact. Examination questions often ask you to identify hazards in a sequence of instructions and propose solutions.
冒险分为结构冒险（资源冲突）、数据冒险（指令间依赖）和控制冒险（分支预测错误）。转发（数据旁路）、分支预测和编译器调度等技术可减轻其影响。考试题目常要求你识别指令序列中的冒险并提出解决方案。
Pipeline throughput = (Number of instructions) / (Pipeline depth × Cycle time per stage) | 流水线吞吐率 = 指令数 / (流水线深度 × 每阶段周期时间)
8. Memory Hierarchy and Caching | 存储器层次与缓存
The memory hierarchy arranges storage from fast, small, and expensive registers and caches near the processor to slower, larger, and cheaper main memory (DRAM) and secondary storage (SSD/HDD). This design exploits the principle of locality: temporal locality (recently accessed data is likely to be reused) and spatial locality (nearby addresses are likely to be accessed soon).
存储器层次结构将存储从靠近处理器的高速、小容量、昂贵的寄存器和缓存，排列到较慢、大容量、便宜的主存（DRAM）和二级存储（SSD/HDD）。这种设计利用了局部性原理：时间局部性（最近访问的数据很可能被再次使用）和空间局部性（邻近地址很可能即将被访问）。
Caches store copies of frequently accessed memory blocks. A typical system includes L1 (split instruction/data), L2 (unified), and sometimes L3 caches. Cache performance is measured by hit rate, miss rate, miss penalty, and access time. Mapping schemes – direct, fully associative, and set-associative – determine where a block resides and how replacement occurs.
缓存存储经常访问的内存块的副本。典型系统包含 L1（指令/数据分离）、L2（统一）以及有时 L3 缓存。缓存性能通过命中率、缺失率、缺失代价和访问时间来衡量。映射方案——直接映射、全相联和组相联——决定块存放位置以及如何进行替换。
| Mapping Type | Key Feature |
|---|---|
| Direct-mapped | Each memory block maps to exactly one cache line; simple but prone to conflict misses |
| Fully associative | Block can go anywhere; high flexibility but expensive hardware |
| Set-associative | Block maps to a set of lines; best trade-off, common in modern CPUs |
9. Interrupts and I/O | 中断与输入/输出
An interrupt is a signal that diverts the CPU from its current execution to handle an external or internal event, such as I/O completion, a timer, or an error. The processor saves the state (including PC and registers) onto the stack, executes an Interrupt Service Routine (ISR), and then restores the state to resume the interrupted program. Interrupts are prioritized, and in nested interrupt systems, higher-priority interrupts can preempt lower ones.
中断是一种信号，使 CPU 从当前执行中转向处理外部或内部事件，如 I/O 完成、定时器或错误。处理器将状态（包括 PC 和寄存器）保存到栈上，执行中断服务程序（ISR），然后恢复状态以继续被中断的程序。中断有优先级，在嵌套中断系统中，高优先级中断可抢占低优先级中断。
I/O can be handled through programmed I/O (CPU polls device status), interrupt-driven I/O (device alerts CPU), or Direct Memory Access (DMA). DMA allows a device to transfer data directly to/from memory without continuous CPU involvement, greatly improving throughput for large transfers. Both syllabi expect you to compare these methods and explain why DMA is preferred for block storage.
I/O 可通过程序控制 I/O（CPU 轮询设备状态）、中断驱动 I/O（设备提醒 CPU）或直接存储器访问（DMA）来处理。DMA 允许设备直接与内存传输数据，无需 CPU 持续介入，极大提高了大块数据传输的吞吐量。两个考纲都要求你比较这些方法，并解释为何 DMA 更适合块存储。
10. Performance Metrics | 性能指标
CPU performance is evaluated using execution time, clock rate, Instructions Per Cycle (IPC), Cycles Per Instruction (CPI), and throughput. The classic formula relates these:
CPU time = Instruction count × CPI × Clock cycle time
where clock cycle time = 1 / clock frequency. Reducing any factor improves total execution time.
CPU 性能通过执行时间、时钟频率、每周期指令数（IPC）、每指令周期数（CPI）和吞吐量来评估。经典公式将其关联起来：
CPU 时间 = 指令数 × CPI × 时钟周期时间
其中时钟周期时间 = 1 / 时钟频率。减少任何一个因素均可缩短总执行时间。
Benchmarks such as SPEC CPU provide standardised performance measurements. MIPS (Millions of Instructions Per Second) and FLOPS (Floating-point Operations Per Second) are sometimes used, but they can be misleading because they do not account for differences in ISAs. In IB and OCR, you are required to calculate performance gains from parallelism, pipelining improvement, or cache optimisations.
如 SPEC CPU 等基准测试提供了标准化的性能测量。有时使用 MIPS（每秒百万条指令）和 FLOPS（每秒浮点运算次数），但可能产生误导，因为它们未考虑 ISA 差异。在 IB 和 OCR 中，你需计算因并行性、流水线改进或缓存优化带来的性能提升。
Speedup = Old execution time / New execution time = 1 / [(1 – fraction enhanced) + (fraction enhanced / speedup factor)] (Amdahl’s Law)
加速比 = 原执行时间 / 新执行时间 = 1 / [(1 – 增强比例) + (增强比例 / 加速因子)] (阿姆达尔定律)
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