4E3 Circuit Diagrams | 4E3 电路图解析

📚 4E3 Circuit Diagrams | 4E3 电路图解析

In the study of computer science, circuit diagrams form the visual language of digital logic. They map out how logic gates – the building blocks of all computing hardware – are interconnected to manipulate binary signals. Mastery of these diagrams is vital for analysing combinational and sequential circuits, designing processors, and troubleshooting hardware. This article walks you through the key concepts, symbols, analysis techniques, and design practices relevant to the 4E3 topic, ensuring you can confidently read, interpret, and construct circuit diagrams for your A-Level examinations.

在计算机科学的学习中，电路图构成了数字逻辑的视觉语言。它们描绘出逻辑门（所有计算硬件的构建块）如何相互连接以处理二进制信号。掌握这些图对于分析组合逻辑和时序逻辑电路、设计处理器以及排查硬件故障至关重要。本文将带你逐一了解与4E3主题相关的关键概念、符号、分析技术和设计实践，确保你能够自信地阅读、解读并构建电路图，为A-Level考试做好准备。

1. The Purpose of Circuit Diagrams | 电路图的用途

Circuit diagrams, often called logic diagrams or schematics, are graphical representations of electronic circuits. In digital electronics, they use standard symbols for logic gates to illustrate how input signals are combined to generate specific outputs. Unlike physical wiring diagrams, these focus on the logical flow rather than the physical placement of components.

电路图（常称作逻辑图或原理图）是电子电路的图形化表示。在数字电子学中，它们使用标准的逻辑门符号，以展示输入信号如何组合并产生特定的输出。与物理接线图不同，电路图关注的是逻辑流向而非元件的物理位置。

Every digital system, from a simple alarm controller to a complex CPU, can be broken down into logic circuits. Engineers first design and simulate at the gate level using these diagrams before moving on to transistor-level implementation. This abstraction makes it possible to reason about functionality without getting lost in semiconductor physics.

从简单的报警控制器到复杂的CPU，每个数字系统都可以分解为逻辑电路。工程师们首先在门级层面使用这些图进行设计和仿真，然后再进入晶体管级别的实现。这种抽象使得我们可以在不陷入半导体物理的情况下推演电路的功能。

Conventions such as left-to-right signal flow, standard power and ground symbols, and junction dots ensure that circuit diagrams can be shared and understood universally. Misreading a diagram or using a non-standard symbol can lead to catastrophic design errors, so adherence to conventions is non-negotiable in professional practice.

诸如从左到右的信号流向、标准电源和接地符号以及连接点等惯例，确保了电路图能够被普遍共享和理解。误读电路图或使用非标准符号可能导致灾难性的设计错误，因此在专业实践中严格遵守惯例是必须的。

2. Standard Logic Gate Symbols | 标准逻辑门符号

At the heart of every circuit diagram lie the symbols for logic gates. The most common are AND, OR, NOT, NAND, NOR, XOR, and XNOR. In A-Level Computer Science, you are expected to recognise the distinctive shapes: the AND gate is a D-shaped symbol with a flat input side; the OR gate is a curved shield with a pointed output; the NOT gate is a triangle with a small circle at its tip; and XOR is similar to OR but with an additional curved line at the input.

每张电路图的核心都是逻辑门的符号。最常见的门包括AND、OR、NOT、NAND、NOR、XOR和XNOR。在A-Level计算机科学中，你需要识别它们独特的形状：AND门是一个平输入侧的D形符号；OR门是带尖输出的弧形盾牌；NOT门是一个尖端带小圆的三角形；而XOR与OR相似，但在输入端多了一条弧线。

The table below summarises the essential gates, their Boolean expressions, and the shape descriptions used in standard schematics.

下表总结了基本门、它们的布尔表达式以及在标准原理图中使用的形状描述。

Gate	Shape Description	Boolean Expression
AND	D-shaped, flat left, curved right	F = A · B
OR	Curved input side forming a pointed shield	F = A + B
NOT	Triangle with a small circle at the output	F = ¬A
NAND	AND gate with a small circle at the output	F = ¬(A · B)
NOR	OR gate with a small circle at the output	F = ¬(A + B)
XOR	OR gate with an extra curved line on the input side	F = A ⊕ B
XNOR	XOR gate with a small circle at the output	F = ¬(A ⊕ B)

You will also encounter buffer gates (triangle without circle) and, in more advanced schematics, three-state buffers. However, for the 4E3 circuit diagrams topic, mastering the seven fundamental gates is the priority.

你还会遇到缓冲门（不带圆圈的三角形），以及在更高级的原理图中见到三态缓冲器。不过，针对4E3电路图这一主题，优先掌握七种基本门即可。

3. From Boolean Expressions to Circuit Diagrams | 从布尔表达式到电路图

One of the core skills is translating a Boolean expression into a circuit diagram. Start by identifying the primary operations and their precedence. For example, the expression F = (A · B) + ¬C tells you that A and B are first ANDed, C is inverted, and then the two results are ORed together.

一项核心技能是将布尔表达式转换为电路图。首先识别主要操作及其优先级。例如，表达式 F = (A · B) + ¬C 告诉你，先对A与B进行AND运算，对C取反，然后将两个结果进行OR运算。

We draw inputs A, B, C as lines on the left. An AND gate takes A and B, producing an intermediate signal. Meanwhile, a NOT gate inverts C. Both intermediate outputs feed into an OR gate, whose output is F. In this way, the expression directly determines the structure of the diagram.

我们将输入A、B、C画成左侧的连线。一个AND门接收A和B，产生一个中间信号；同时，一个NOT门将C取反。两个中间输出送入一个OR门，其输出就是F。这样，表达式直接决定了电路图的结构。

When expressions contain parentheses, treat the sub-expression inside as a block. Draw that sub-circuit first, label its output, and then treat that label as an input to the outer operation. This modular approach prevents overcrowding and makes the diagram easier to read.

当表达式中含有括号时，将括号内的子表达式视为一个模块。先画出该子电路，标出其输出，然后将该输出标号视为外层操作的输入。这种模块化方法能防止图形拥挤，使电路图更易读。

It is also important to appreciate that the same Boolean function can be implemented in many ways. A student must learn to convert an expression into a circuit using only NAND gates, or only NOR gates, because these are the universal gates often used in practice.

同样重要的是要认识到，同一个布尔函数可以有多种实现方式。学生必须学会仅用NAND门或仅用NOR门将一个表达式转换为电路，因为这些门是实际中常用的通用门。

4. Analysing Circuits with Truth Tables | 使用真值表分析电路

A truth table exhaustively lists all possible input combinations and the corresponding output of a circuit. To construct one, systematically count through binary values for n inputs (from 0 to 2ⁿ-1). For each combination, propagate the values through the gates according to their logical function until you obtain the final output.

真值表详尽列出所有可能的输入组合及其对应的电路输出。要构建真值表，需要系统地遍历n个输入的二进制值（从0到2ⁿ-1）。对于每一种组合，根据逻辑功能将值传播通过各个门，直至得到最终输出。

Consider a simple circuit: A XOR B implemented as (A · ¬B) + (¬A · B). The truth table below confirms that the output is 1 only when A and B differ.

考虑一个简单电路：用(A · ¬B) + (¬A · B)实现的A异或B。下表证实仅当A和B不同时输出才为1。

A	B	A XOR B
0	0	0
0	1	1
1	0	1
1	1	0

When analysing a given diagram in an exam, the safest method is to label all intermediate nodes. Write the Boolean sub-expression at each node, and then evaluate these sub-expressions row by row in the truth table. This eliminates guesswork and makes it easy to spot errors.

在考试中分析给定的电路图时，最稳妥的方法是对所有中间节点进行标注。在每个节点处写出布尔子表达式，然后在真值表中逐行计算这些子表达式。这可以消除猜测，并易于发现错误。

Truth tables also serve as a foundation for circuit simplification. By inspecting the rows where the output is 1, you can derive a sum-of-products expression, which can then be simplified using Boolean algebra or Karnaugh maps.

真值表也是电路简化的基础。通过检查输出为1的行，可以导出积之和表达式，随后可用布尔代数或卡诺图进行简化。

5. Common Combinational Circuits | 常见组合逻辑电路

Several combinational circuits appear repeatedly in the 4E3 syllabus. The half adder is the simplest: it adds two single-bit numbers, producing a sum (S = A ⊕ B) and a carry (C = A · B). It employs one XOR gate and one AND gate.

有几个组合逻辑电路在4E3大纲中反复出现。半加器是最简单的：它将两个单位二进制数相加，产生和（S = A ⊕ B）与进位（C = A · B）。它使用一个异或门和一个与门。

A full adder extends this to add three bits – two input bits and a carry-in – and its circuit typically involves two XOR gates, two AND gates, and an OR gate. Full adders are cascaded to build multi-bit adders found in ALUs.

全加器则扩展为将三个位相加——两个输入位和一个进位输入——其电路通常包含两个异或门、两个与门和一个或门。全加器级联后即可构建ALU中的多比特加法器。

The multiplexer (MUX) is a data selector that channels one of several input lines to a single output, based on select lines. A 2-to-1 MUX expression is F = (A · ¬S) + (B · S), and its circuit diagram clearly reflects this structure.

多路复用器（MUX）是一种数据选择器，它根据选择线将多个输入线之一导向单一输出。2选1 MUX的表达式为 F = (A · ¬S) + (B · S)，其电路图清晰地反映了这一结构。

Conversely, a decoder takes n inputs and activates exactly one of 2ⁿ outputs. For example, a 2-to-4 decoder uses NOT gates to generate inverses and AND gates to combine them, giving output lines that correspond to minterms.

相反，译码器接收n个输入并恰好激活2ⁿ个输出中的一个。例如，2-4译码器使用非门生成反相并用与门进行组合，产生的输出线对应于各个最小项。

Being able to draw and identify these standard building blocks saves time during design and analysis. You are often required to interconnect them to build larger systems, such as using a decoder to select a register in a memory unit.

能够绘制并识别这些标准构建块，可节省设计和分析的时间。考试中常常要求你将其相互连接以构建更大的系统，例如用译码器在内存单元中选择寄存器。

6. Simplifying Circuit Designs | 简化电路设计

Complex circuits often contain redundant gates. Boolean algebra provides a set of rules – such as identity, complement, commutative, distributive, and De Morgan’s theorems – to reduce expressions and, consequently, the number of gates in a diagram.

复杂电路常常含有冗余的门。布尔代数提供了一套规则——如恒等律、互补律、交换律、分配律和德摩根定理——用以化简表达式，进而减少电路图中的门数。

For example, the expression F = ¬(A · B) + A can be simplified by De Morgan: ¬A + ¬B + A, which reduces to 1 because A + ¬A = 1. The resulting circuit is simply a constant high output, requiring no gates at all.

例如，表达式 F = ¬(A · B) + A 可通过德摩根定理化简：¬A + ¬B + A，这化简为1，因为 A + ¬A = 1。最终电路就是一个常高输出，完全不需要任何门。

While Boolean algebra is powerful, the Karnaugh map (K-map) offers a visual method for minimisation. For up to four variables, the K-map quickly reveals adjacent 1s that can be combined, yielding a minimal sum-of-products expression. This expression is then directly translated into an optimised circuit diagram.

虽然布尔代数功能强大，卡诺图（K-map）提供了一种可视化的化简方法。对于最多四个变量，卡诺图能快速显示出可合并的相邻1，从而得到最简积之和表达式。该表达式随后可直接转化为最优化电路图。

In examination questions, you may be given a truth table or an unoptimised expression and asked to design a circuit using the fewest gates. Always aim for the minimal form first, then draw the diagram, ensuring you use the most appropriate gates.

在考试题目中，你可能会拿到一个真值表或未优化的表达式，并被要求用最少的门设计电路。务必先求出最简形式，然后再绘制电路图，并确保使用最合适的门。

7. Sequential Circuit Diagrams: Flip-Flops | 时序电路图：触发器

Unlike combinational circuits, sequential circuits have memory. Their outputs depend on current inputs and previous states. The simplest memory element is the SR latch, made by cross-coupling two NOR gates. Its circuit diagram shows output fed back to the input of the other gate, creating a storage loop.

与组合逻辑电路不同，时序逻辑电路具有记忆功能，其输出取决于当前输入和之前的状态。最简单的记忆元件是SR锁存器，它由两个NOR门交叉耦合而成。其电路图显示输出反馈至另一个门的输入，形成了一个存储环路。

A D-type flip-flop is edge-triggered and only updates its output on the rising edge of a clock signal. Its diagram typically includes a clock input, a D input, and Q and ¬Q outputs. The internal structure often builds upon a master-slave latch configuration, but at the diagram level you may treat it as a block symbol.

D型触发器是边沿触发的，仅在时钟信号的上升沿更新其输出。其电路图通常包含时钟输入、D输入以及Q和¬Q输出。内部结构通常基于主从锁存器配置，但在图级层面，你可以将其视为一个模块符号。

When drawing sequential circuit diagrams, it is crucial to indicate the clock line clearly, often with a small triangle symbol at the clock input. Arrows or labels should clarify the direction of data flow, especially where outputs loop back to earlier stages.

绘制时序电路图时，务必清晰地标出时钟线，通常在时钟输入处使用小三角形符号。箭头或标签应明确数据流向，特别是在输出环回至较早阶段时。

Registers, counters, and shift registers are all built by connecting flip-flops in specific patterns. Understanding their diagrams is foundational for topics like processor architecture and memory design.

寄存器、计数器和移位寄存器都是通过以特定模式连接触发器构建的。理解它们的电路图是学习处理器体系结构和存储器设计等主题的基础。

8. Diagram Conventions and Best Practices | 电路图惯例与最佳实践

Well-drawn diagrams follow strict conventions. Inputs are drawn on the left, outputs on the right. Power and ground connections are often omitted for clarity, but when shown, use standard symbols. Signal names should be descriptive, such as ‘Enable’ or ‘Carry_In’.

绘制良好的电路图严格遵循惯例。输入画在左侧，输出画在右侧。为清晰起见，电源和接地连接常被省略，但若要展示则应使用标准符号。信号名称应具有描述性，如“Enable”或“Carry_In”。

Use consistent spacing and avoid tangled wires. Where wires cross without connecting, no dot is placed; a junction dot is only used when three or more wires intentionally meet. Buses (multiple parallel signals) can be indicated by a thicker line with a slash and the number of lines.

保持间距一致，避免杂乱无章的连线。导线交叉而不连接时，不放置连接点；仅当三根或以上导线有意相连时才使用连接点。总线（多根并行信号线）可用粗线和斜杠加数字表示。

Label intermediate nodes, especially

Published by TutorHao | Computer Science Revision Series | aleveler.com

更多咨询请联系16621398022（同微信）

4E3 Circuit Diagrams | 4E3 电路图解析