📚 GCSE AQA Computer Architecture: Key Points | GCSE AQA 计算机体系结构考点精讲
This article provides a focused revision guide on computer architecture for the AQA GCSE Computer Science specification. It explains key concepts such as the von Neumann design, CPU components, registers, the fetch-decode-execute cycle, buses, factors affecting performance, and embedded systems. Each section presents the technical content in both English and Chinese to support bilingual learners and ensure exam readiness.
本文是针对 AQA GCSE 计算机科学考试中计算机体系结构考点的精讲指南。内容涵盖冯·诺依曼设计、CPU 组件、寄存器、取指-解码-执行周期、总线、影响性能的因素以及嵌入式系统等关键概念。每个部分均采用中英双语对照讲解，帮助双语学习者充分备考。
1. What is Computer Architecture? | 什么是计算机体系结构？
Computer architecture refers to the design and internal organisation of a computer system’s fundamental components and how they interact. It determines how a processor manages instructions and data, impacting the machine’s functionality and performance.
计算机体系结构是指计算机系统基本组件的设计及其内部组织方式，以及它们之间如何协同工作。它决定了处理器如何管理指令和数据，进而影响机器的功能和性能。
In GCSE terms, studying architecture means understanding the structure of the central processing unit (CPU), the pathways that link it to memory, and the step-by-step process by which programs are executed.
在 GCSE 的范畴中，学习体系结构意味着了解中央处理器 (CPU) 的结构、连接内存的数据通路，以及程序被逐步执行的过程。
2. The Von Neumann Architecture | 冯·诺依曼体系结构
The von Neumann architecture is a design model in which program instructions and data share the same memory space and are accessed over the same buses. It is built on the stored-program concept, where instructions are held in main memory just like ordinary data.
冯·诺依曼体系结构是一种设计模型，其中程序指令和数据共享同一内存空间，并通过相同的总线进行访问。它建立在存储程序概念之上，即指令像普通数据一样保存在主存中。
This unified memory approach simplifies hardware design but can create a bottleneck because the CPU must wait when fetching both instructions and data through a single pathway.
这种统一内存的方法简化了硬件设计，但会产生瓶颈，因为 CPU 在通过单一通路获取指令和数据时必须等待。
The key functional units within the von Neumann architecture are the processor (including CU and ALU), memory, input/output systems, and the buses that connect them.
冯·诺依曼体系结构中的关键功能单元包括处理器 (含 CU 和 ALU)、存储器、输入/输出系统以及连接它们的总线。
3. Core Components of the CPU | CPU 的核心部件
The CPU is the brain of the computer and contains two main parts: the Control Unit (CU) and the Arithmetic Logic Unit (ALU). The CU directs operations, managing the flow of data between the processor, memory, and input/output devices by generating control signals.
CPU 是计算机的大脑，包含两个主要部分：控制单元 (CU) 和算术逻辑单元 (ALU)。CU 负责指挥操作，通过生成控制信号来管理处理器、内存和输入/输出设备之间的数据流。
The ALU performs all arithmetic calculations (addition, subtraction, etc.) and logical comparisons (AND, OR, NOT). Every calculation or decision inside the CPU passes through the ALU.
ALU 执行所有算术运算 (如加、减等) 和逻辑比较 (与、或、非)。CPU 内部的每一次计算或判断都要经过 ALU。
These units are supported by small, fast storage locations called registers, which hold data and addresses temporarily during processing.
这些单元由称为寄存器的小型快速存储位置提供支持，寄存器在处理过程中临时保存数据和地址。
4. Key Registers in Detail | 关键寄存器详解
The Program Counter (PC) holds the memory address of the next instruction to be fetched. After each fetch, the PC is incremented to point to the following instruction, ensuring the program runs in sequence unless a jump occurs.
程序计数器 (PC) 保存下一条要取指的指令的内存地址。每次取指后，PC 会递增指向下一条指令，确保程序按顺序运行，除非发生跳转。
The Memory Address Register (MAR) stores the address of the memory location that the CPU is about to read from or write to. Any access to RAM must have its target address placed in the MAR first.
内存地址寄存器 (MAR) 存储 CPU 即将读取或写入的内存位置的地址。对 RAM 的任何访问都必须先将目标地址放入 MAR。
The Memory Data Register (MDR) holds the actual data or instruction that has been fetched from memory or that is waiting to be written back. It acts as a buffer between memory and the processor’s internal registers.
内存数据寄存器 (MDR) 保存从内存中取出的实际数据或指令，或者等待写回的数据。它充当内存与处理器内部寄存器之间的缓冲。
The Accumulator (ACC) is where the results of ALU operations are temporarily stored. When a calculation is carried out, the output lands in the accumulator, ready for the next operation or storage.
累加器 (ACC) 是临时存放 ALU 运算结果的地方。执行计算时，输出结果会进入累加器，为下一步操作或存储做好准备。
5. The Fetch-Decode-Execute Cycle | 取指-解码-执行周期
The fetch-decode-execute cycle is the continuous process the CPU follows to run programs. In the fetch stage, the address from the PC is copied into the MAR, and the instruction at that address is read into the MDR. The PC is then incremented.
取指-解码-执行周期是 CPU 运行程序时不断重复的过程。在取指阶段，PC 中的地址被复制到 MAR，然后该地址处的指令被读入 MDR。随后 PC 递增。
During the decode stage, the Control Unit interprets the instruction held in the MDR. It determines what operation is required and which components need to be activated.
在解码阶段，控制单元对 MDR 中的指令进行解释。它确定需要执行什么操作以及需要激活哪些组件。
In the execute stage, the CPU carries out the instruction. This may involve the ALU performing a calculation, data moving between registers, or a jump that changes the PC value to branch to a different part of the program.
在执行阶段，CPU 实际执行指令。这可能包括 ALU 执行计算、数据在寄存器之间移动，或者执行跳转指令从而改变 PC 值以转向程序的其他部分。
Once the execute stage finishes, the cycle immediately repeats from the fetch stage, processing instruction after instruction unless the computer is halted.
一旦执行阶段完成，周期立即从取指阶段重新开始，逐条处理指令，直到计算机停止运行为止。
6. System Buses | 系统总线
System buses are parallel sets of wires that transfer information between the CPU and other components. There are three main buses: the address bus, the data bus, and the control bus.
系统总线是用于在 CPU 与其他部件之间传输信息的并行导线组。主要有三条总线：地址总线、数据总线和控制总线。
The address bus carries memory addresses from the CPU to memory or other devices. It is unidirectional (one-direction) from the CPU. The width of the address bus determines the maximum number of addressable memory locations.
地址总线将内存地址从 CPU 传送到内存或其他设备。它是单向的 (从 CPU 发出)。地址总线的宽度决定了可寻址内存位置的最大数量。
The data bus transfers actual data and instructions between components, typically bidirectionally (both ways). The width of the data bus indicates how many bits can be moved simultaneously, affecting data throughput.
数据总线在组件之间传输实际的数据和指令，通常是双向的。数据总线的宽度表示可以同时移动多少位，影响数据吞吐量。
The control bus carries control signals from the CU to coordinate operations, such as read/write commands, clock pulses, and interrupt requests. It can be bidirectional depending on the signal.
控制总线传递来自控制单元的控制信号以协调操作，例如读/写命令、时钟脉冲和中断请求。根据信号的不同，它可以是双向的。
7. Clock Speed and Performance | 时钟速度与性能
The CPU clock sends out regular electrical pulses that synchronise all operations. Clock speed, measured in hertz (Hz), tells how many cycles per second the CPU can perform. Modern processors run at gigahertz (GHz), meaning billions of cycles per second.
CPU 时钟发出规律的电子脉冲以同步所有操作。时钟速度以赫兹 (Hz) 为单位，表示 CPU 每秒可执行的周期数。现代处理器以千兆赫 (GHz) 运行，即每秒数十亿个周期。
A higher clock speed generally means the fetch-decode-execute cycle runs more times each second, allowing more instructions to be processed. However, overheating and power consumption increase, limiting how fast a chip can run sustainably.
更高的时钟速度通常意味着取指-解码-执行周期每秒运行更多次，从而能处理更多指令。但过热和功耗也会随之增加，限制了芯片可持续运行的速度。
Performance is not solely about clock speed; the efficiency of the architecture, how many cycles an instruction takes, and other factors also play a large role.
性能不仅仅取决于时钟速度；体系结构的效率、每条指令所需的周期数以及其他因素也起很大作用。
Performance ∝ (Clock Speed × Cores × Cache Efficiency)
性能 ∝ (时钟速度 × 核心数 × 缓存效率)
8. Cache Memory | 缓存存储器
Cache is a small amount of extremely fast memory located inside or very close to the CPU. It stores frequently used instructions and data so that the processor does not need to fetch them from slower main memory repeatedly.
缓存是位于 CPU 内部或紧邻 CPU 的一小块极快存储器。它保存常用指令和数据，使处理器无需反复从较慢的主存中获取它们。
Modern CPUs often have multiple levels of cache: L1 (fastest but smallest), L2, and sometimes L3 (larger but slightly slower). When the CPU finds the needed data in cache (a cache hit), execution speeds up; when it must go to RAM (a cache miss), performance drops.
现代 CPU 通常有多级缓存：一级缓存 (最快但最小)、二级缓存，有时还有三级缓存 (更大但稍慢)。当 CPU 在缓存中找到所需数据 (缓存命中) 时，执行速度加快；当它必须访问 RAM (缓存未命中) 时，性能下降。
The size of the cache is a key factor in CPU performance. More cache can store a larger working set of instructions and data, reducing the frequency of slow main-memory accesses.
缓存大小是 CPU 性能的关键因素。更大的缓存可以存储更多的工作指令和数据，从而减少对慢速主存的访问频率。
9. Multi-core Processing | 多核处理
A multi-core processor contains more than one processing unit (core) on a single chip. Each core can independently run its own fetch-decode-execute cycle, allowing multiple instructions to be processed truly in parallel.
多核处理器在单个芯片上包含不止一个处理单元 (核心)。每个核心可以独立运行自己的取指-解码-执行周期，从而真正并行处理多条指令。
A dual-core CPU can handle two streams of instructions at the same time, while a quad-core can handle four. However, the performance gain is not always directly proportional because software must be designed to split tasks efficiently across cores.
双核 CPU 可同时处理两条指令流，而四核可处理四条。然而，性能提升并不总是成正比，因为软件必须被设计为能够高效地将任务分配到各个核心。
Adding more cores increases multitasking capability and raw throughput, but clock speed limitations and thermal constraints still apply. Exam questions often ask you to balance clock speed, cores, and cache when evaluating performance.
增加核心数可提升多任务处理能力和原始吞吐量，但仍有时钟速度限制和散热约束。考试问题常要求评估性能时综合考虑时钟速度、核心数和缓存。
10. Embedded Systems | 嵌入式系统
An embedded system is a computer built into a larger device to perform a dedicated function. Unlike general-purpose desktops or laptops, an embedded system typically runs a single, specialised program and is designed for low power consumption and reliability.
嵌入式系统是内置于较大设备中用于执行特定功能的计算机。与通用台式机或笔记本电脑不同，嵌入式系统通常运行单一的专用程序，并设计为低功耗和高可靠性。
Examples include washing machine controllers, microwave timers, car engine management units, digital watches, and smart thermostats. These systems use simpler processors with minimal resources, often omitting components not required for their task.
例子包括洗衣机控制器、微波炉定时器、汽车引擎管理单元、数字手表和智能恒温器。这些系统使用资源极少的简单处理器，通常省去任务不需要的部件。
Because embedded systems are tailored to one job, they can be optimised to be small, cheap, and energy-efficient. Their software is often stored in ROM and not intended to be changed by the user.
由于嵌入式系统专为一项工作而定制，它们可以被优化得小巧、便宜且节能。其软件通常存储在 ROM 中，用户一般不能更改。
11. Summary and Exam Tips | 考点总结与考试技巧
To master computer architecture for AQA GCSE, be able to label a diagram of the CPU showing the CU, ALU, PC, MAR, MDR, and Accumulator, and describe what each does. Practise writing out the full fetch-decode-execute cycle with changes to the registers.
要掌握 AQA GCSE 的计算机体系结构，应能标注 CPU 示意图中 CU、ALU、PC、MAR、MDR 和累加器的位置，并描述各自功能。练习写出完整的取指-解码-执行周期并说明寄存器变化。
Understand how the address, data, and control buses work together and be prepared to explain the effect of bus widths on performance. When asked about improving CPU performance, always consider clock speed, number of cores, and cache size, giving a balanced argument.
理解地址总线、数据总线和控制总线如何协同工作，并准备好解释总线宽度对性能的影响。当被问及如何提升 CPU 性能时，要始终考虑时钟速度、核心数和缓存大小，给出均衡的论述。
Remember that embedded systems have different design priorities compared to general-purpose computers. Use specific examples and be clear about the stored-program concept from the von Neumann model, as it underpins most of modern computing.
记住，嵌入式系统的设计优先级与通用计算机不同。要多用具体例子，并清晰阐述冯·诺依曼模型中的存储程序概念，因为它是现代计算的基础。
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