📚 GCSE WJEC Computer Science: CPU Key Points | GCSE WJEC 计算机科学：CPU 考点精讲
Understanding how the Central Processing Unit (CPU) works is a fundamental part of the WJEC GCSE Computer Science syllabus. This guide breaks down the key topics you need to know, including the von Neumann architecture, the fetch-decode-execute cycle, and factors that affect CPU performance.
理解中央处理器 (CPU) 的工作原理是 WJEC GCSE 计算机科学大纲的基础部分。本书将分解你需要掌握的关键主题，包括冯·诺依曼架构、取指-译码-执行周期以及影响 CPU 性能的因素。
1. The Von Neumann Architecture | 冯·诺依曼架构
The von Neumann architecture is a design model for stored-program computers. In this model, the CPU, memory, and input/output devices are connected by a system of buses. Both instructions and data are stored in the same memory unit. This means the CPU can read an instruction and data from the same memory, which simplifies the design.
冯·诺依曼架构是一种存储程序计算机的设计模型。在这种模型中，CPU、内存和输入/输出设备通过总线系统连接。指令和数据存储在同一内存单元中。这意味着 CPU 可以从同一内存读取指令和数据，从而简化了设计。
One key characteristic is the use of a single shared memory for both program instructions and data. The CPU fetches instructions in sequence, using the program counter. This is called the stored-program concept. The disadvantage is the von Neumann bottleneck: because instructions and data share the same bus, they cannot be accessed simultaneously, potentially slowing down the system.
一个关键特征是程序指令和数据共用一个内存。CPU 使用程序计数器顺序获取指令。这就叫存储程序概念。其缺点是冯·诺依曼瓶颈：由于指令和数据共用同一总线，它们不能同时被访问，可能降低系统速度。
2. Main Components of the CPU | CPU 的主要组件
The CPU consists of two primary components: the Control Unit (CU) and the Arithmetic Logic Unit (ALU). The CU directs the flow of data and instructions, decodes instructions, and controls the execution of operations. The ALU performs all arithmetic and logical operations, such as addition, subtraction, comparisons, and Boolean AND/OR/NOT.
CPU 由两个主要组件组成：控制单元 (CU) 和算术逻辑单元 (ALU)。CU 指导数据和指令的流动，对指令进行译码，并控制操作的执行。ALU 执行所有的算术和逻辑运算，如加法、减法、比较以及布尔与/或/非运算。
Additional temporary storage locations called registers are inside the CPU. Registers are much faster to access than main memory (RAM). Together, the CU, ALU, and registers form the core of the processor.
CPU 内部还有称为寄存器的临时存储位置。访问寄存器的速度比访问主存 (RAM) 快得多。CU、ALU 和寄存器共同构成处理器的核心。
3. Registers in Detail | 寄存器的详细介绍
The CPU contains several special-purpose registers that play essential roles in the fetch-decode-execute cycle. The table below summarises the key registers you must know for the WJEC exam.
CPU 包含若干专用寄存器，它们在取指-译码-执行周期中起着至关重要的作用。下表总结了 WJEC 考试中你必须掌握的关键寄存器。
| Register | 中文名称 | Abbreviation | Function / 功能 |
|---|---|---|---|
| Program Counter | 程序计数器 | PC | Holds the memory address of the next instruction to be fetched. 保存下一条要取指的指令的内存地址。 |
| Memory Address Register | 内存地址寄存器 | MAR | Stores the address of the memory location to be accessed (read/write). 存储要访问（读/写）的内存位置的地址。 |
| Memory Data Register | 内存数据寄存器 | MDR | Holds the data just read from or about to be written to memory. 保存刚从内存读取或即将写入内存的数据。 |
| Current Instruction Register | 当前指令寄存器 | CIR | Contains the instruction currently being decoded and executed. 存放正在被译码和执行的指令。 |
| Accumulator | 累加器 | ACC | Stores the results of arithmetic or logic operations carried out by the ALU. 存储 ALU 执行的算术或逻辑运算的结果。 |
During the fetch-decode-execute cycle, the PC supplies the address to the MAR, the instruction is loaded into the MDR, then transferred to the CIR for decoding. The ALU may use the accumulator to hold intermediate results.
在取指-译码-执行周期中，PC 将地址提供给 MAR，指令被加载到 MDR，然后传输到 CIR 进行译码。ALU 可能会使用累加器来保存中间结果。
4. The Fetch-Decode-Execute Cycle | 取指-译码-执行周期
Fetch: The CPU places the address from the Program Counter onto the address bus via the MAR. A read signal is sent to memory. The instruction stored at that address is retrieved from memory and placed into the MDR. The instruction is then copied to the CIR. The PC is incremented to point to the next instruction (usually adding 1, but depending on instruction length).
取指： CPU 通过 MAR 将程序计数器中的地址放到地址总线上。向内存发送读信号。存储在该地址的指令从内存中取出并放入 MDR。然后指令被复制到 CIR。PC 递增以指向下一条指令（通常加 1，但取决于指令长度）。
PC ← PC + 1
Decode: The control unit (CU) decodes the instruction held in the CIR. It identifies the opcode (the operation) and any operands (data or addresses). The CU determines what needs to happen, for example, whether to load data, perform an addition, or store a result.
译码： 控制单元 (CU) 对保存在 CIR 中的指令进行译码。它识别操作码（操作）和任何操作数（数据或地址）。CU 确定需要做什么，例如，是加载数据、执行加法还是存储结果。
Execute: The CU sends control signals to the relevant components to carry out the instruction. If the instruction involves arithmetic or logic, the ALU is activated and may use the accumulator. If data needs to be read from or written to memory, the MAR and MDR are used again. Once the instruction is executed, the cycle repeats starting from the fetch stage using the updated PC.
执行： CU 向有关组件发送控制信号以执行指令。如果指令涉及算术或逻辑运算，则 ALU 被激活并可能使用累加器。如果需要从内存读取或向内存写入数据，则再次使用 MAR 和 MDR。指令执行完毕后，从更新后的 PC 开始重复取指阶段，周而复始。
This cycle is the fundamental process by which a stored-program computer runs a program. You must be able to describe the roles of the registers at each stage.
这个周期是存储程序计算机运行程序的基本过程。你必须能够描述每个阶段寄存器的作用。
5. Buses Connecting the CPU | 连接 CPU 的总线
The CPU communicates with memory and I/O devices via a set of parallel wires called buses. There are three main types: the address bus (carries memory addresses from the CPU, typically to RAM), the data bus (carries the actual data between the CPU and memory), and the control bus (carries control signals, e.g., read/write commands). The width of the address bus determines the maximum addressable memory; the width of the data bus determines how much data can be transferred per cycle.
CPU 通过一组称为总线的并行导线与内存和 I/O 设备通信。主要有三种类型：地址总线（将内存地址从 CPU 传输到 RAM）、数据总线（在 CPU 和内存之间传输实际数据）和控制总线（传输控制信号，如读写命令）。地址总线的宽度决定了最大可寻址内存；数据总线的宽度决定了每个周期可传输的数据量。
Understanding buses helps explain how the CPU fetches instructions. For instance, during a fetch, the MAR places an address on the address bus, and the data from that location is returned on the data bus into the MDR.
理解总线有助于解释 CPU 如何获取指令。例如，取指期间 MAR 将地址放在地址总线上，该位置的数据通过数据总线返回到 MDR。
6. Factors Affecting CPU Performance – Overview | 影响 CPU 性能的因素概述
Several hardware characteristics directly impact CPU performance. In your WJEC exam, you may be asked to describe or explain how each factor affects speed. The three main factors are clock speed, cache size, and the number of cores. You should be able to compare two processors based on these metrics and justify which one would be more suitable for a given task.
一些硬件特性直接影响 CPU 性能。在 WJEC 考试中，你可能会被要求描述或解释每个因素如何影响速度。三个主要因素是时钟速度、缓存大小和核心数。你应当能够根据这些指标比较两个处理器，并证明哪个更适合特定任务。
It is also important to note that improving one factor does not necessarily double performance if other bottlenecks exist, such as slow memory or software limitations. The overall system performance depends on a balance of components.
同样重要的是，如果存在其他瓶颈（如慢速内存或软件限制），改进一个因素并不一定使性能翻倍。整体系统性能取决于组件的平衡。
Published by TutorHao | GCSE Computer Science Revision Series | aleveler.com
更多咨询请联系16621398022（同微信）
屏轩国际教育cambridge primary/secondary checkpoint, cat4, ukiset,ukcat,igcse,alevel,PAT,STEP,MAT, ibdp,ap,ssat,sat,sat2课程辅导，国外大学本科硕士研究生博士课程论文辅导