IB OCR Computer Science: CPU Core Concepts Explained

📚 IB OCR Computer Science: CPU Core Concepts Explained | CPU 考点精讲

The central processing unit (CPU) is the brain of any computer system, executing instructions and managing data flow. For IB and OCR Computer Science students, a deep understanding of CPU architecture, registers, the fetch-decode-execute cycle, and performance factors is essential. This revision guide breaks down every critical concept with clear explanations, comparisons, and exam tips to help you master the topic and achieve top marks.

中央处理器（CPU）是任何计算机系统的大脑，负责执行指令和管理数据流。对于 IB 和 OCR 计算机科学学生来说，深入理解 CPU 架构、寄存器、取指-译码-执行周期以及性能因素至关重要。本篇复习指南通过清晰的解释、对比和考试技巧，为你拆分每一个关键概念，帮助你掌握该主题并获得高分。

1. What is a CPU? | 什么是 CPU？

The CPU, or Central Processing Unit, is a piece of hardware that carries out the instructions of a computer program by performing basic arithmetic, logical, control, and input/output operations. It is often referred to as the “brain” of the computer. In modern systems, the CPU is housed on a single integrated circuit called a microprocessor, which contains millions or billions of transistors.

CPU，即中央处理器，是一种硬件，通过执行基本的算术、逻辑、控制和输入/输出操作来运行计算机程序的指令。它常被称为计算机的“大脑”。在现代系统中，CPU 被集成在称为微处理器的单一集成电路上，其中包含数百万或数十亿个晶体管。

The speed at which a CPU processes instructions is measured in gigahertz (GHz), with one hertz representing one cycle per second. A CPU with a higher clock speed can generally execute more instructions per second, though other factors like architecture also matter.

CPU 处理指令的速度以千兆赫兹（GHz）为单位，一赫兹代表每秒一个周期。时钟频率更高的 CPU 通常每秒可以执行更多指令，不过架构等其他因素同样重要。

2. Von Neumann Architecture | 冯·诺依曼架构

The vast majority of computers today are based on the Von Neumann architecture, which stores both program instructions and data in a single shared memory unit. This means the CPU must fetch instructions from memory one at a time, creating what is known as the “Von Neumann bottleneck” because the bus connecting the CPU to memory can only transfer one piece of data or instruction at a time, limiting system speed.

如今绝大多数计算机都基于冯·诺依曼架构，该架构将程序指令和数据都存储在同一个共享内存单元中。这意味着 CPU 必须一次从内存中取出一条指令，从而产生了所谓的“冯·诺依曼瓶颈”——连接 CPU 和内存的总线一次只能传输一条数据或指令，限制了系统速度。

Key characteristics of Von Neumann architecture include: a single control unit, a single ALU, a single memory system, and sequential instruction processing. This simplicity makes it easier to design and program, but it can suffer from slower performance compared to alternative architectures like Harvard.

冯·诺依曼架构的关键特征包括：单一控制单元、单一 ALU、单一内存系统以及顺序指令处理。这种简单性使其设计和编程更加容易，但与哈佛等替代架构相比，其性能可能较慢。

3. CPU Components: ALU, CU, Registers | CPU 组成：ALU、CU、寄存器

A CPU consists of several core components working together. The Arithmetic Logic Unit (ALU) performs all arithmetic and logical operations, such as addition, subtraction, AND, OR, and NOT. The Control Unit (CU) directs the flow of data and instructions, fetching instructions from memory, decoding them, and coordinating the execution by sending control signals to other components.

CPU 由多个核心组件协同工作而成。算术逻辑单元（ALU）执行所有算术和逻辑运算，例如加法、减法、与、或、非运算。控制单元（CU）指导数据流和指令流，负责从内存取出指令、对指令进行译码，并通过向其他组件发送控制信号来协调执行过程。

Registers are high-speed storage locations within the CPU that temporarily hold data, instructions, or addresses being processed. They are far faster than main memory (RAM) and are critical for the CPU’s ability to operate at high speeds. Common registers include the Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), Current Instruction Register (CIR), and Accumulator (ACC).

寄存器是 CPU 内部的高速存储位置，用于临时存放正在处理的数据、指令或地址。它们比主内存（RAM）快得多，对于 CPU 实现高速运行至关重要。常见的寄存器包括程序计数器（PC）、内存地址寄存器（MAR）、内存数据寄存器（MDR）、当前指令寄存器（CIR）和累加器（ACC）。

4. Key Registers: PC, MAR, MDR, CIR, ACC | 关键寄存器：PC、MAR、MDR、CIR、ACC

The Program Counter (PC) holds the memory address of the next instruction to be fetched. After each fetch operation, the PC is normally incremented by one (or by the instruction length) to point to the subsequent instruction, unless a jump or branch instruction alters the flow.

程序计数器（PC）保存下一条将要取出的指令的内存地址。每次取指操作后，PC 通常会自增一（或增加指令长度）以指向下一条指令，除非跳转或分支指令改变了执行流程。

The Memory Address Register (MAR) stores the address of the memory location that the CPU wants to read from or write to. The Memory Data Register (MDR) holds the actual data value that has been fetched from memory or is about to be written to memory. Together, MAR and MDR act as the interface between the CPU and main memory.

内存地址寄存器（MAR）存储 CPU 想要读取或写入的内存位置的地址。内存数据寄存器（MDR）保存刚从内存中取出的数据值或即将写入内存的数据。MAR 和 MDR 共同充当 CPU 与主内存之间的接口。

The Current Instruction Register (CIR) contains the instruction currently being decoded and executed. The Accumulator (ACC) is a general-purpose register that temporarily holds results from ALU operations, such as intermediate calculation results or data being processed.

当前指令寄存器（CIR）存放当前正在被译码和执行的指令。累加器（ACC）是一个通用寄存器，用于临时保存来自 ALU 运算的结果，例如中间计算结果或正在处理的数据。

5. Buses: Data, Address, Control | 总线：数据、地址、控制

Communication between the CPU, memory, and I/O devices occurs through a set of parallel wires called buses. There are three main types: the Address Bus carries memory addresses from the CPU to memory (unidirectional); the Data Bus transmits actual data between the CPU and memory or I/O (bidirectional); and the Control Bus carries control signals, such as read/write commands and timing clock pulses, and can be bidirectional.

CPU、内存和 I/O 设备之间的通信通过一组称为总线的并行线路进行。主要有三种类型：地址总线将内存地址从 CPU 传送到内存（单向）；数据总线在 CPU 与内存或 I/O 之间传输实际数据（双向）；控制总线携带控制信号，例如读/写命令和定时时钟脉冲，且可以是双向的。

The width of the address bus determines how many memory locations can be addressed. For example, a 32-bit address bus can directly address 2³² memory locations. The width of the data bus affects how many bits can be moved at once, directly impacting performance.

地址总线的宽度决定了可以寻址的内存位置数量。例如，32 位地址总线可以直接寻址 2³² 个内存位置。数据总线的宽度影响一次可以移动多少位数据，这直接影响性能。

6. The Fetch-Decode-Execute Cycle | 取指-译码-执行周期

The fetch-decode-execute cycle is the fundamental process by which the CPU processes instructions. In the fetch stage, the address from the PC is placed into the MAR and a read signal is sent to memory. The instruction stored at that address is then loaded into the MDR and copied to the CIR. The PC is then incremented.

取指-译码-执行周期是 CPU 处理指令的基本过程。在取指阶段，PC 中的地址被放入 MAR，并向内存发送读取信号。该地址处存储的指令随后被加载到 MDR 中并复制到 CIR。然后 PC 自增。

During the decode stage, the control unit interprets the opcode (operation code) and operand(s) of the instruction now held in the CIR, determining what operation must be performed and on which data. In the execute stage, the processor carries out the action required, which may involve ALU operations, memory reads/writes, or I/O operations. Any result is stored back in the appropriate register, often the accumulator. The cycle then repeats for the next instruction.

在译码阶段，控制单元对当前 CIR 中指令的操作码和操作数进行解释，确定必须执行什么操作以及操作的数据。在执行阶段，处理器实施所需动作，这可能涉及 ALU 运算、内存读/写或 I/O 操作。任何结果都会被存回适当的寄存器，通常是累加器。然后循环重复处理下一条指令。

7. Factors Affecting CPU Performance | 影响 CPU 性能的因素

Several interconnected factors determine how fast a CPU can execute programs. Clock speed is the most commonly cited, but it does not tell the whole story. The number of processor cores allows multiple instructions to be processed simultaneously, while cache memory reduces the time the CPU spends waiting for data from main memory.

有几个相互关联的因素决定 CPU 执行程序的速度。时钟频率是最常被提及的因素，但它并不能反映全貌。处理器核心的数量允许多条指令同时处理，而缓存内存则减少了 CPU 等待主内存数据的时间。

Instruction set architecture (ISA) and word size also matter. A richer instruction set can perform complex tasks with fewer instructions, while a wider word size lets the CPU handle larger chunks of data per cycle, improving throughput. Additionally, advanced techniques such as pipelining and superscalar architecture can significantly boost performance.

指令集架构和字长也很重要。更丰富的指令集可以用更少的指令完成复杂任务，而更宽的字长使 CPU 每个周期能处理更大的数据块，从而提高吞吐量。此外，流水线和超标量架构等先进技术也能显著提升性能。

8. Clock Speed, Cores, Cache | 时钟频率、核心、缓存

The system clock generates a continuous sequence of pulses to synchronize the operations of the CPU. Clock speed, measured in GHz, indicates how many pulse cycles occur per second. A 3.5 GHz processor ticks 3.5 billion times per second. However, some instructions require multiple clock cycles, so higher clock speed does not linearly increase performance.

系统时钟产生连续的脉冲序列以同步 CPU 的操作。时钟频率以 GHz 为单位，表示每秒发生的脉冲周期数。一个 3.5 GHz 的处理器每秒嘀嗒 35 亿次。然而，某些指令需要多个时钟周期，因此更高的时钟频率并不会线性地提升性能。

Modern CPUs contain multiple cores, each capable of independently executing instructions. A dual-core processor can theoretically double processing speed for multi-threaded tasks, though software must be designed to take advantage of multiple cores. Cache memory, typically divided into L1, L2, and sometimes L3 levels, stores frequently accessed data and instructions closer to the CPU, drastically reducing access time compared to fetching from RAM.

现代 CPU 包含多个核心，每个核心都能独立执行指令。对于多线程任务，双核处理器理论上可以将处理速度提高一倍，但软件必须被设计成能利用多核。缓存内存通常分为 L1、L2 有时还有 L3 级别，将频繁访问的数据和指令存储在更靠近 CPU 的位置，与从 RAM 取数据相比，能大幅缩短存取时间。

9. Pipelining (Advanced) | 流水线（进阶）

Pipelining is a technique used to increase instruction throughput by overlapping the execution of multiple instructions. Imagine an assembly line: while one instruction is being executed, the next is being decoded, and the one after that is being fetched. This means that in an ideal pipeline, a new instruction can be completed every clock cycle, even though each instruction still takes several cycles from start to finish.

流水线是一种通过重叠多条指令的执行来提高指令吞吐量的技术。想象一条装配线：当一条指令正在执行时，下一条正在译码，再下一条正在取指。这意味着在理想的流水线中，每个时钟周期都可以完成一条新指令，尽管每条指令从开始到完成仍然需要多个周期。

Pipelining introduces challenges such as data hazards (when an instruction depends on the result of a previous instruction still in the pipeline) and branch prediction (guessing the outcome of a conditional branch to keep the pipeline full). CPUs use techniques like forwarding and speculative execution to mitigate these issues, which is a common topic in higher-level IB and OCR syllabi.

流水线也带来了挑战，例如数据冒险（当某条指令依赖于仍在流水线中的前一条指令的结果）和分支预测（猜测条件分支的结果以保持流水线满载）。CPU 使用前递和推测执行等技术来缓解这些问题，这些是 IB 和 OCR 高阶大纲中的常见话题。

10. Harvard Architecture vs Von Neumann | 哈佛架构与冯·诺依曼架构对比

Harvard architecture differs from Von Neumann by having separate memory and signal pathways for instructions and data. This allows the CPU to fetch an instruction and read/write data simultaneously, eliminating the bottleneck found in Von Neumann systems. Harvard architecture is commonly used in embedded systems (e.g., microcontrollers) and digital signal processors (DSPs) where performance predictability is crucial.

哈佛架构与冯·诺依曼架构的不同之处在于，指令和数据拥有独立的内存和信号通路。这使 CPU 能够同时取指和读/写数据，从而消除冯·诺依曼系统中的瓶颈。哈佛架构常用于嵌入式系统（如微控制器）和数字信号处理器（DSP），在这些领域中性能的可预测性至关重要。

Feature	Von Neumann	Harvard
Memory	Single shared memory for data and instructions	Separate memories for data and instructions
Buses	One set of buses	Separate buses for data and instructions
Bottleneck	Von Neumann bottleneck due to shared bus	No bottleneck, higher data throughput
Complexity	Simpler design, cheaper	More expensive, physically larger
Usage	General-purpose computers	Embedded systems, DSPs

While Von Neumann remains dominant in desktops and laptops, many modern CPUs use a modified Harvard architecture internally (with separate L1 caches for data and instructions) to gain the benefits of both designs.

虽然冯·诺依曼架构在台式机和笔记本电脑中仍占主导地位，但许多现代 CPU 内部采用改进的哈佛架构（为数据和指令分别使用独立的 L1 缓存），以兼得两种设计的优点。

11. Assembly Language & Instruction Set | 汇编语言与指令集

Understanding the CPU also means grasping how software interacts with hardware at a low level. An instruction set is the collection of all commands a particular CPU can execute. These commands are represented in machine code (binary) but programmers often use assembly language mnemonics like LDA (load accumulator), ADD (add), or STO (store). A standard assembly instruction consists of an opcode and an operand, such as LDA 5 for loading the value 5 into the accumulator, or ADD 7 for adding 7 to the accumulator’s current value.

理解 CPU 也意味着要掌握软件如何在低层级与硬件交互。指令集是特定 CPU 能执行的所有命令的集合。这些命令以机器码（二进制）表示，但程序员通常使用汇编语言的助记符，如 LDA（加载累加器）、ADD（加法）或 STO（存储）。一条标准汇编指令由操作码和操作数组成，例如 LDA 5 将数值 5 加载到累加器，或 ADD 7 将 7 与累加器的当前值相加。

In IB and OCR examinations, you may be asked to interpret simple assembly programs or trace the values in the accumulator and memory during execution. Key addressing modes include immediate (the operand is the actual value), direct (the operand is an address), and indirect (the operand points to an address containing the final address). Mastery of these basics ensures you can securely answer low-level programming and CPU operation questions.

在 IB 和 OCR 考试中，你可能会被要求解释简单的汇编程序或跟踪累加器和内存在执行过程中的值。关键的寻址模式包括立即寻址（操作数就是实际值）、直接寻址（操作数是地址）和间接寻址（操作数指向包含最终地址的地址）。掌握这些基础知识可确保你稳妥地回答低级编程和 CPU 操作问题。

12. Exam Tips & Common Mistakes | 考试技巧与常见错误

Exam tip 1: Always distinguish clearly between the MAR and MDR. The MAR holds the address, while the MDR holds the data at that address. Mixing them up is a frequent mistake. In the fetch cycle, the address goes to MAR first, then the data comes back to MDR. Be precise in sequencing.

考试提示 1：务必清晰区分 MAR 和 MDR。MAR 保存地址，而 MDR 保存该地址处的数据。混淆二者是常见错误。在取指周期中，地址首先进入 MAR，然后数据返回到 MDR。请精确表述顺序。

Exam tip 2: When explaining the fetch-decode-execute cycle, use a step-by-step approach and name the registers involved at each stage. Use diagrams or flowcharts where possible. For multi-core questions, remember that not all programs can be parallelized; some tasks remain sequential, so doubling cores does not double speed.

考试提示 2：在解释取指-译码-执行周期时，使用分步方法并指明每个阶段涉及的寄存器。尽可能使用图表或流程图。对于多核心问题，记住并非所有程序都能并行化；有些任务仍然是顺序的，因此核心数量翻倍并不等于速度翻倍。

Common mistake: Stating that a higher clock speed always means a faster processor. In reality, modern CPUs with lower clock speeds can outperform older ones with higher speeds due to architectural improvements, pipelining, and larger caches. Always discuss performance holistically.

常见错误：声称时钟频率更高总意味着处理器更快。实际上，由于架构改进、流水线和更大的缓存，时钟频率较低的现代 CPU 可能比频率更高的老型号表现更好。始终要综合讨论性能。

Practice describing the fetch-decode-execute cycle, compare Von Neumann and Harvard architectures, and review assembly code traces. These topics are guaranteed to appear in your IB or OCR exam.

练习描述取指-译码-执行周期，对冯·诺依曼架构与哈佛架构进行比较，并复习汇编代码跟踪。这些主题必定会在你的 IB 或 OCR 考试中出现。

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IB OCR Computer Science: CPU Core Concepts Explained | CPU 考点精讲