📚 Logic Gates CCEA GCSE Computer Science Exam Focus | GCSE CCEA 计算机：逻辑门 考点精讲
Logic gates form the very foundation of digital electronics and computer hardware. For the CCEA GCSE Computer Science specification, understanding how these gates work, how to combine them into circuits, and how to interpret truth tables is essential for success. This revision guide breaks down every core logic gate, Boolean expressions, circuit diagrams, and exam techniques you need to master.
逻辑门是数字电子和计算机硬件的基础。在 CCEA GCSE 计算机科学考试中，理解这些门的工作原理、如何将它们组合成电路以及如何解读真值表是取得好成绩的关键。这本复习指南将逐一剖析每个核心逻辑门、布尔表达式、电路图和应试技巧，助你完全掌握。
1. What Are Logic Gates? | 什么是逻辑门？
A logic gate is a basic building block of digital circuits that takes one or more binary inputs and produces a single binary output based on a logical rule. Binary means the values are either 0 (off, false) or 1 (on, true). In the CCEA GCSE Computer Science course, you need to know seven fundamental gates: AND, OR, NOT, NAND, NOR, XOR, and XNOR.
逻辑门是数字电路的基本构建块，它接收一个或多个二进制输入，并根据逻辑规则产生单个二进制输出。二进制意味着值只能是 0（关、假）或 1（开、真）。在 CCEA GCSE 计算机科学课程中，你需要掌握七种基本门：与门（AND）、或门（OR）、非门（NOT）、与非门（NAND）、或非门（NOR）、异或门（XOR）和同或门（XNOR）。
These gates are physically implemented using transistors arranged in specific configurations. However, for the exam, you focus on their symbols, truth tables, and Boolean algebra representations. You will also be expected to analyse and design simple combinational logic circuits.
这些门在物理上是通过特定配置的晶体管实现的。但在考试中，你只需关注它们的符号、真值表和布尔代数表示。你还需要分析和设计简单的组合逻辑电路。
2. AND Gate | 与门
The AND gate outputs 1 only when all of its inputs are 1. It has two standard inputs (though more are possible), and its operation can be described as logical multiplication. In Boolean notation, the output is written as Q = A · B or simply AB.
与门仅在所有输入均为 1 时才输出 1。它通常有两个输入端，其运算可以描述为逻辑乘法。在布尔表示法中，输出写作 Q = A · B 或简写为 AB。
The truth table for a 2-input AND gate is:
2 输入与门的真值表如下：
| A | B | Q (A AND B) |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Candidates often remember this gate by the phrase ‘all or nothing’ – only when all inputs are true does the output become true. In CCEA papers, you might be asked to draw the AND gate symbol and give its Boolean expression.
考生常用“全1出1”来记忆该门——只有当所有输入为真时，输出才为真。在 CCEA 试卷中，你可能会被要求画出与门符号并给出其布尔表达式。
3. OR Gate | 或门
The OR gate outputs 1 if at least one of its inputs is 1. Its Boolean expression is Q = A + B (note the plus sign does not mean numerical addition). This gate behaves like an inclusive OR: if any input is 1, output is 1.
或门在至少一个输入为 1 时输出 1。其布尔表达式为 Q = A + B（注意加号不代表数学加法）。该门表现为包含性或：只要任一输入为 1，输出即为 1。
| A | B | Q (A OR B) |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
In circuit design problems, OR gates are often used to combine multiple conditions where any single condition being true is sufficient to activate an output, such as a system that triggers an alarm if either a door sensor OR a window sensor is tripped.
在电路设计问题中，或门常用于组合多个条件，只要任一条件为真就足以激活输出，例如当门传感器或窗传感器被触发时警报拉响的系统。
4. NOT Gate | 非门
The NOT gate, also called an inverter, has only one input and one output. Its output is the logical complement of the input. The Boolean expression is Q = NOT A, often written as Q = A with an overbar (we can represent this as Q = A̅ in plain text, but you should use a bar over the letter in handwriting).
非门，也称反相器，只有一个输入和一个输出。它的输出是输入的逻辑补。布尔表达式为 Q = NOT A，通常写作带横线的 A（手写时应在字母上方加上横线）。
| A | Q (NOT A) |
|---|---|
| 0 | 1 |
| 1 | 0 |
A NOT gate is extremely useful for inverting signals. In many combinational circuits, a small triangle symbol at the input or output of another gate indicates inversion. Remember that two NOT gates in series cancel each other out, giving Q = A.
非门非常适用于信号反相。在许多组合电路中，另一个门的输入或输出端的小三角符号表示取反。记住两个非门串联会相互抵消，输出 Q = A。
5. NAND Gate | 与非门
A NAND gate is the exact opposite of an AND gate – its output is 0 only when all inputs are 1. The Boolean expression is Q = NOT (A AND B), written as Q = (A·B)⁻ (the overbar covering both A and B). NAND is considered a universal gate because you can build any other gate using only NAND gates.
与非门是完全相反于与门——仅在所有输入为 1 时输出 0。布尔表达式为 Q = NOT (A AND B)，写作上方加横线的 (A·B)。与非门被认为是通用门，因为仅用与非门就能构建出任何其他门。
| A | B | Q (A NAND B) |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
CCEA exam questions often test your understanding of the NAND gate’s truth table and its role as a universal gate. You may be asked to construct an AND, OR, or NOT function using only NAND gates. This highlights the importance of gate minimisation in chip design.
CCEA 考试题经常测试你对与非门真值表及其作为通用门的理解。你可能被要求仅用与非门构建与、或、非功能。这突出了芯片设计中门最小化的重要性。
6. NOR Gate | 或非门
The NOR gate outputs 1 only when all inputs are 0. It is the complement of the OR gate. Its Boolean expression is Q = NOT (A OR B), with the overbar covering (A+B). Like NAND, NOR is also a universal gate.
或非门仅在所有输入为 0 时输出 1。它是或门的补。其布尔表达式为 Q = NOT (A OR B)，横线覆盖 (A+B)。与与非门一样，或非门也是通用门。
| A | B | Q (A NOR B) |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
When analysing a NOR gate circuit, remember that its output is 1 only in the single case where both inputs are 0. This behaviour is particularly useful for detecting an all‑zero condition, such as in simple digital comparators.
在分析或非门电路时，记住其输出 1 仅在两个输入均为 0 的单一情况下出现。这一行为对于检测全零状态尤其有用，比如在简单的数字比较器中。
7. XOR Gate | 异或门
The XOR (Exclusive OR) gate outputs 1 only when the number of 1 inputs is odd. For a 2‑input XOR gate, the output is 1 when the inputs are different. Its Boolean expression is Q = A XOR B, often written as Q = A ⊕ B.
异或门（XOR）仅在输入中 1 的个数为奇数时输出 1。对于 2 输入异或门，当输入不同时输出为 1。其布尔表达式为 Q = A XOR B，常写作 Q = A ⊕ B。
| A | B | Q (A XOR B) |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
XOR is invaluable in arithmetic circuits, such as half-adders and full-adders, because it can produce the sum bit of binary addition without considering a carry. Many CCEA past papers ask students to recognise or construct an XOR gate from a combination of basic gates.
异或门在算术电路中不可或缺，如半加器和全加器，因为它能产生不考虑进位的二进制加法求和位。许多 CCEA 历年试卷要求学生识别或从基本门组合构建异或门。
8. XNOR Gate | 同或门
The XNOR (Exclusive NOR) gate is the complement of XOR. It outputs 1 only when the two inputs are equal. Its Boolean expression is Q = NOT (A XOR B) or Q = A ⊙ B (sometimes A ⊕ B with an overbar).
同或门（XNOR）是异或门的补。它仅在两输入相等时输出 1。其布尔表达式为 Q = NOT (A XOR B) 或带横线的 A ⊕ B。
| A | B | Q (A XNOR B) |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
In exam questions, XNOR often appears as an equality detector. If you see a circuit where the output is high when A and B are the same, you are looking at an XNOR function. This gate is less common in the earlier GCSE units but still features in higher‑tier problems.
在考试题中，同或门常作为相等检测器出现。如果你看到一个电路，当 A 和 B 相同时输出为高，那么这就是同或功能。该门在 GCSE 前期单元中较少见，但会出现在高难度题目中。
9. Truth Tables and Boolean Expressions | 真值表与布尔表达式
Every logic gate, and indeed every combinational logic circuit, can be fully described by a truth table. A truth table lists all possible combinations of inputs and the corresponding output. For n inputs, there are 2ⁿ rows (excluding headings). In the CCEA specification, you must be able to complete truth tables for up to three inputs.
每个逻辑门，乃至每个组合逻辑电路，都可以用真值表完全描述。真值表列出了所有可能的输入组合及其对应的输出。对于 n 个输入，有 2ⁿ 行（不含表头）。在 CCEA 大纲中，你必须能够完成最多三个输入的真值表。
Boolean expressions are a shorthand way to describe logic circuits algebraically. For example, the expression Q = (A·B) + C combines an AND gate and an OR gate. When constructing a truth table from an expression, evaluate each sub‑expression for all input combinations, following the order of precedence: brackets first, then NOT, then AND, then OR.
布尔表达式是用代数方法描述逻辑电路的简略方式。例如，表达式 Q = (A·B) + C 组合了一个与门和一个或门。在根据表达式构建真值表时，需要遵循优先顺序对所有输入组合求值：先括号，再非，然后与，最后或。
You must also be able to derive a Boolean expression from a given circuit. Trace back from the output toward the inputs, labelling intermediate junctions with their logical functions. This skill is frequently tested in CCEA structured questions.
你还必须能够从给定电路中推导布尔表达式。从输出端向输入端回溯，用逻辑功能标记中间节点。CCEA 结构化题目经常考查此技能。
10. Logic Circuit Diagrams | 逻辑电路图
CCEA GCSE Computer Science expects you to interpret and draw logic circuit diagrams using the standard symbols. Each gate has a distinct shape: AND is a D‑shape with a flat front, OR is a curved front with a pointed back, NOT is a triangle with a small circle (bubble) at its output, and NAND/NOR/XOR add a bubble to their respective basic gates.
CCEA GCSE 计算机科学要求你使用标准符号解读并绘制逻辑电路图。每个门都有独特形状：与门是前端平坦的 D 形，或门是前端弯曲、后端尖的月牙形，非门是一个三角后接小圆圈，而与非/或非/异或则在各自基本门上增加一个小圆圈。
When combining gates, ensure that connections are clear. Draw inputs on the left and output on the right (unless specified otherwise). Label all inputs with letters, and indicate any inverted outputs with a bubble. In exams, marks are awarded for correct shape, correct number of inputs, and proper connection to the rest of the circuit.
组合多个门时，要确保连线清晰。输入端画在左侧，输出端在右侧（除非另有规定）。用字母标注所有输入，并用小圆圈表示反相输出。考试中，形状正确、输入数目正确、与电路其余部分连接正确都可得分。
Often a question provides a logic circuit and asks for its truth table or Boolean expression. Take it step by step: write the output of each gate in terms of the inputs, then combine them using Boolean operations.
经常有题目给出一个逻辑电路，要求写出真值表或布尔表达式。请一步步来：先写出每个门的输出关于输入的表达式，再用布尔运算将它们组合起来。
11. De Morgan’s Laws | 德摩根定律
De Morgan’s laws are two transformations that relate AND and OR operations in Boolean algebra. They are critical for simplifying logic circuits and for understanding how NAND and NOR gates can emulate other gates. The two laws are:
德摩根定律是布尔代数中将与和或运算关联起来的两个变换。它们对简化逻辑电路和理解与非门和或非门如何模拟其他门至关重要。两个定律如下：
- 1st law: NOT (A AND B) = (NOT A) OR (NOT B) → (A·B)⁻ = A⁻ + B⁻
- 2nd law: NOT (A OR B) = (NOT A) AND (NOT B) → (A+B)⁻ = A⁻ · B⁻
In plain English, the complement of a product is the sum of the complements, and the complement of a sum is the product of the complements. You can prove these laws to yourself using truth tables.
通俗来讲，乘积的补等于各补之和，和的补等于各补之积。你可以通过真值表自行验证这些定律。
CCEA exams may ask you to apply De Morgan’s laws to simplify a given expression or to prove that two circuits are equivalent. A popular question is to show that a NAND gate is equivalent to an OR gate with inverted inputs. This directly follows from the first law.
CCEA 考试可能会要求你应用德摩根定律来简化给定表达式，或证明两个电路等效。常见的题目是证明与非门等同于输入取反后的或门，这直接由第一定律得出。
12. Exam Tips and Common Pitfalls | 考试技巧与常见错误
When tackling CCEA logic gate questions, follow these tips to maximise your marks: (1) Always draw truth tables neatly with clear columns for each input and the output. Use binary order (000, 001, 010, etc.) to avoid missing combinations. (2) When simplifying Boolean expressions, check each application of De Morgan’s laws carefully – losing a NOT bar is a frequent mistake. (3) In circuit diagrams, a bubble at the input is not the same as a bubble at the output – understand the effect on logic levels.
在解答 CCEA 逻辑门题目时，请遵循以下建议以最大化得分：（1）绘制真值表时保持整洁，明确列出每个输入和输出的列。使用二进制顺序（000、001、010 等）以避免遗漏组合。（2）简化布尔表达式时，仔细检查德摩根定律的每次应用——漏掉一条非横线是常见错误。（3）在电路图中，输入端的圆圈与输出端的圆圈效果不同——要理解对逻辑电平的影响。
Watch out for questions where you are asked to ‘use only NAND gates’ or ‘use only NOR gates’. Practice converting basic gates into these universal forms. For example, an AND gate is a NAND followed by a NOT, and the NOT can itself be made from a NAND with its inputs tied together.
注意那些要求你“仅用与非门”或“仅用或非门”的题目。练习将基本门转换为这些通用形式。例如，与门可视为一个与非门后接一个非门，而非门本身又可由输入连接在一起的与非门构成。
Time management is crucial: allocate about one minute per mark. If a 6‑mark question asks for a truth table of a 3‑input circuit, quickly construct the 8 rows and fill them systematically. For longer design problems, state your intermediate steps to gain partial credit even if the final circuit contains an error.
时间管理至关重要：大致按“一分钟一分”分配。如果一个 6 分题要求给出三输入电路的真值表，迅速构建 8 行并系统地填满。对于较长的设计题，即使最终电路有误，也要写出中间步骤以获得部分分数。
Finally, always double-check your work. Re‑evaluate the output for one or two random rows of your truth table against the Boolean expression to catch careless errors.
最后，务必复查。针对真值表随机挑一两行对照布尔表达式重新求值，以抓住粗心错误。
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