Logic Gates Exam Focus | 逻辑门考点精讲

📚 Logic Gates Exam Focus | 逻辑门考点精讲

Logic gates are the fundamental building blocks of digital circuits and a core topic in IB and CIE Computer Science. They take one or more binary inputs and produce a single binary output based on a logical function. Mastering logic gates is essential not only for your exams but also for understanding how processors, memory, and control units operate at the hardware level. This revision guide covers everything you need: truth tables, Boolean expressions, universal gates, combinational logic, adders, simplification techniques, and common pitfalls.

逻辑门是数字电路的基本构建块，也是IB和CIE计算机科学中的核心主题。每个逻辑门接收一个或多个二进制输入，并根据某种逻辑功能产生一个二进制输出。掌握逻辑门不仅对考试至关重要，也是理解处理器、内存和控制单元在硬件层面如何工作的基础。本复习指南涵盖了你需要掌握的全部内容：真值表、布尔表达式、通用门、组合逻辑、加法器、化简技巧以及常见易错点。

1. What Are Logic Gates? | 什么是逻辑门？

A logic gate is an idealized or physical device implementing a Boolean function. In digital electronics, inputs and outputs are limited to two voltage levels, typically represented as 0 (low) and 1 (high). The behavior of any logic gate can be fully described by a truth table, which lists all possible input combinations and the resulting output. In IB and CIE syllabi, you are expected to recognise standard gate symbols, construct truth tables, and derive Boolean expressions for simple circuits.

逻辑门是实现布尔函数的理想化或物理器件。在数字电子学中，输入和输出仅限于两个电压电平，通常表示为0（低电平）和1（高电平）。任何逻辑门的行为都可以用真值表完全描述，真值表列出了所有可能的输入组合及其对应的输出。在IB和CIE的教学大纲中，你需要识别标准逻辑门符号、构建真值表，并为简单电路推导布尔表达式。

2. Basic Logic Gates: AND, OR, NOT | 基本逻辑门：与门、或门、非门

The three simplest gates form the basis for all digital logic. The AND gate outputs 1 only when all inputs are 1. For two inputs A and B, the Boolean expression is A · B. The OR gate outputs 1 if at least one input is 1; its expression is A + B. The NOT gate, or inverter, has a single input and outputs the complement; if input is A, output is ¬A or A’.

三个最简单的逻辑门构成了所有数字逻辑的基础。与门仅在所有输入均为1时输出1。对于两个输入A和B，其布尔表达式为A·B。或门在至少一个输入为1时输出1；其表达式为A+B。非门（或反相器）只有一个输入，输出其补码；若输入为A，则输出为¬A或A’。

Here are the truth tables for these gates:

以下是这些门的真值表：

A	B	AND	OR	NOT A
0	0	0	0	1
0	1	0	1	1
1	0	0	1	0
1	1	1	1	0

3. Universal Gates: NAND and NOR | 通用门：与非门和或非门

NAND and NOR are called universal gates because any other logic function can be implemented using only NAND gates or only NOR gates. A NAND gate is an AND followed by a NOT; its output is 0 only when all inputs are 1. The Boolean expression is ¬(A · B) or simply A NAND B. The NOR gate is an OR followed by a NOT; it outputs 1 only when all inputs are 0, expressed as ¬(A + B) or A NOR B.

与非门和或非门被称为通用门，因为仅使用与非门或仅使用或非门就可以实现任何其他逻辑功能。与非门是与门后接非门；仅在所有输入均为1时输出0。其布尔表达式为¬(A·B)或简写为A NAND B。或非门是或门后接非门；仅在所有输入均为0时才输出1，表达式为¬(A+B)或A NOR B。

Exam questions frequently ask you to construct a specific gate (like AND, OR, NOT, XOR) using only NAND or only NOR. For example, a NOT gate can be made by shorting the inputs of a NAND: A NAND A = ¬A. Similarly, AND can be obtained by inverting a NAND output with another NAND configured as NOT. Understanding this universality is crucial for circuit design questions.

考试题目常要求你仅用与非门或仅用或非门来构造特定的门（如与门、或门、非门、异或门）。例如，将与非门的输入端短接即可得到非门：A NAND A = ¬A。类似地，可以利用另一个配置为非门的与非门对与非门的输出进行反相来得到与门。理解这种通用性对于电路设计题至关重要。

4. Exclusive Gates: XOR and XNOR | 异或门和同或门

The XOR (exclusive OR) gate outputs 1 when an odd number of inputs are 1. For two inputs, it gives 1 if the inputs are different. The Boolean expression is A ⊕ B, which can be expanded to (A ∧ ¬B) ∨ (¬A ∧ B). The XNOR (exclusive NOR) gate is the complement of XOR; it outputs 1 when the inputs are equal. Its expression is ¬(A ⊕ B) or A ⊙ B. These gates are fundamental in arithmetic circuits and error detection.

异或门（XOR）在输入中1的个数为奇数时输出1。对于两个输入，如果两个输入不同则输出1。布尔表达式为A ⊕ B，可展开为(A ∧ ¬B) ∨ (¬A ∧ B)。同或门（XNOR）是异或门的补码；当输入相等时输出1。其表达式为¬(A ⊕ B) 或 A ⊙ B。这些门在算术电路和错误检测中非常基础。

You must be able to draw and interpret the truth tables of XOR and XNOR, and derive equivalent circuits using basic gates. A classic exam task is to prove that A ⊕ B = (A NAND (A NAND B)) NAND (B NAND (A NAND B)), demonstrating how XOR can be built from NANDs.

你必须能够绘制和解释XOR和XNOR的真值表，并推导出使用基本门的等效电路。一个经典的考试任务是证明A ⊕ B = (A NAND (A NAND B)) NAND (B NAND (A NAND B))，展示如何用与非门构建异或门。

5. Boolean Expressions and Algebra | 布尔表达式与代数

Boolean expressions describe the logic of a circuit in algebraic form. Variables represent inputs and outputs, and the operators are · (AND), + (OR), and ¬ (NOT). IB and CIE papers require you to simplify expressions using Boolean laws such as commutativity, associativity, distributivity, absorption, and the complement law A + ¬A = 1, A · ¬A = 0. A typical simplification might be: A + A · B = A (absorption).

布尔表达式以代数形式描述电路的逻辑。变量代表输入和输出，运算符包括·（与）、+（或）和¬（非）。IB和CIE试卷要求你使用布尔定律（如交换律、结合律、分配律、吸收律）以及互补律A + ¬A = 1、A · ¬A = 0来化简表达式。一个典型的化简可能是：A + A·B = A（吸收律）。

You must also be able to convert between expression, truth table, and logic diagram. Given a diagram, extract the expression step by step, then simplify. Or, given a problem statement, design an expression and implement it with gates. Practice with identities such as De Morgan’s laws (next section) and the distributive law A · (B + C) = A · B + A · C.

你还必须能够在表达式、真值表和逻辑图之间进行转换。给定逻辑图，逐步提取表达式，然后进行化简。或者，给定问题描述，设计表达式并用门电路实现。练习使用诸如德摩根定律（下一节）和分配律A·(B + C) = A·B + A·C等恒等式。

6. De Morgan’s Theorems | 德摩根定理

De Morgan’s theorems are essential tools for simplifying and transforming logic expressions:

德摩根定理是简化和转换逻辑表达式的基本工具：

¬(A ∧ B) = ¬A ∨ ¬B

¬(A ∨ B) = ¬A ∧ ¬B

These state that the complement of an AND is the OR of the complements, and the complement of an OR is the AND of the complements. In digital circuits, De Morgan’s theorems allow you to convert a NAND gate into an OR gate with inverted inputs, or a NOR into an AND with inverted inputs. This is particularly useful when you must implement a function using only one type of universal gate.

这些定理表明：与的反是或的非，或的反是与的非。在数字电路中，德摩根定理允许你将与非门转换为带反相输入的或门，或将或非门转换为带反相输入的与门。当你只能使用一种通用门来实现功能时，这特别有用。

When simplifying, remember to break the bar and change the operator. A common exam trick is to hide a simplification opportunity: an expression like ¬(¬A · ¬B) can be simplified stepwise to A + B using De Morgan and double negation. Always look for places where De Morgan can reduce the number of gates.

在化简时，记住断线变号。考试中常见的技巧是隐藏化简机会：像¬(¬A·¬B)这样的表达式可以用德摩根和双重否定逐步化简为A+B。始终寻找可以用德摩根减少门数量的地方。

7. Combining Logic Gates | 组合逻辑门

Real circuits combine multiple gates to create complex functions. In an exam, you may be presented with a logic diagram containing several gates and asked to produce the truth table, the Boolean expression, or to identify a simplified equivalent. The approach is always systematic: label intermediate signals, write the expression at each node, and combine them. For example, a circuit with inputs A, B first passes through a NAND gate giving X = ¬(A · B), then an OR gate with C giving Y = X + C. The final output is Y = ¬(A · B) + C.

实际电路中多个门组合在一起创建复杂的功能。在考试中，你可能会看到一个包含数个门的逻辑图，并被要求写出真值表、布尔表达式或找出简化的等效电路。方法总是系统性的：标记中间信号，在每个节点写出表达式，然后组合起来。例如，一个输入为A、B的电路先通过一个与非门得到X = ¬(A·B)，然后与C一起通过一个或门得到Y = X + C。最终输出为Y = ¬(A·B) + C。

Another common question asks you to complete a truth table for a given combinational circuit. Start with the inputs, work through each column for intermediate signals, and finally fill the output column. Double-check rows where your output does not match a simple pattern; an XOR or XNOR might be hiding inside the network.

另一个常见问题是要求你为给定的组合电路完成真值表。从输入开始，逐列填写中间信号，最后填写输出列。仔细检查那些输出与简单模式不匹配的行；电路网络中可能隐藏着XOR或XNOR。

8. Half Adder and Full Adder | 半加器和全加器

Adders illustrate how logic gates perform arithmetic. A half adder adds two single binary digits and produces a sum bit (S) and a carry bit (C). The sum is S = A ⊕ B, the carry is C = A ∧ B. A full adder extends this to accept a carry-in from a previous stage, so it adds A, B, and C_in. The sum is S = A ⊕ B ⊕ C_in, and the carry-out is C_out = (A ∧ B) ∨ (C_in ∧ (A ⊕ B)). These circuits are the foundation of the ALU in a CPU.

加法器展示了逻辑门如何执行算术运算。半加器将两个单二进制位相加，产生一个和位(S)和一个进位位(C)。和为S = A ⊕ B，进位为C = A ∧ B。全加器进一步接受来自前一级的进位输入，因此它对A、B和C_in进行相加。和为S = A ⊕ B ⊕ C_in，进位输出为C_out = (A ∧ B) ∨ (C_in ∧ (A ⊕ B))。这些电路是CPU中ALU的基础。

You may be asked to draw the logic diagram for a full adder from two half adders and an OR gate, or to complete a truth table. Ensure you know that the sum output is 1 when an odd number of inputs are 1, and carry-out is 1 when at least two inputs are 1. This pattern helps you verify the truth table quickly.

你可能会被要求用两个半加器和一个或门画出全加器的逻辑图，或者完成真值表。务必记住：当输入中1的个数为奇数时，和输出为1；当至少有两个输入为1时，进位输出为1。这个模式可以帮助你快速验证真值表。

9. Karnaugh Maps for Simplification | 卡诺图化简

Karnaugh maps (K-maps) provide a visual method to simplify Boolean expressions of up to 4 variables. The cells of a K-map are arranged so that adjacent cells differ by only one variable (Gray code order). You group ones in sizes of 1, 2, 4, 8 (powers of two) to form the minimal sum-of-products expression. In IB and CIE exams, you might be given a truth table and asked to use a K-map to find the simplest expression, or to identify redundant gates in a circuit.

卡诺图提供了一种可视化方法来化简最多包含4个变量的布尔表达式。卡诺图的单元格按照相邻单元仅有一个变量不同的方式进行排列（格雷码顺序）。你需要将1分组，每组大小为1、2、4、8（2的幂），以形成最简的积之和表达式。在IB和CIE考试中，你可能会被给出一个真值表，要求使用卡诺图找出最简表达式，或者识别电路中的冗余门。

For a 2-variable map, the cells correspond to combinations of A, B. A 3-variable map adds C, and a 4-variable map has two input rows and two input columns. Remember to consider the map as toroidal – edges ‘wrap around’, so a group of 1s split across the top/bottom or left/right edges is valid. Always write the simplified expression as a sum of products, and compare it with the original to ensure correctness.

对于2变量卡诺图，单元格对应A、B的组合。3变量图增加C，4变量图有两行输入和两列输入。记住将卡诺图视为环形——边缘是“环绕的”，因此跨顶部/底部或左侧/右侧边缘的1的集合是有效的。始终将化简后的表达式写为积之和形式，并与原始表达式比较以确保正确性。

10. Exam Tips and Common Mistakes | 考试技巧和常见错误

First, always label your logic gates clearly when drawing circuits; use standard symbols for AND (flat back), OR (curved back), NOT (triangle with bubble). In CIE, multiple-input gates can be drawn with additional inputs, but stick to 2-input versions unless specified. Second, when simplifying with Boolean algebra, write each step and state the law used – this gains method marks. A classic mistake is forgetting to apply De Morgan correctly: ¬(A + B) is NOT A · B, but many students wrongly write ¬A + ¬B.

首先，在绘制电路时始终清晰标注逻辑门；使用标准符号：AND（平背）、OR（凹背）、NOT（带小圆圈的三角形）。在CIE中，多输入门可以用额外的输入绘制，但除非特别说明，请坚持使用2输入版本。其次，用布尔代数化简时，写出每一步并注明所使用的定律——这能够获得过程分。一个经典错误是错误地应用德摩根定律：¬(A + B)等于¬A·¬B，但许多学生错误地写成¬A+¬B。

Third, when completing a truth table from a diagram, double-check that you have 2ⁿ rows for n inputs, and do not skip any intermediate signal. Fourth, in K-map questions, always check if the map gives a simpler expression than the one initially provided – this often catches redundant terms. Finally, practice converting between NAND-only and NOR-only implementations, as these are very common in exam paper section B. For CIE specifically, be familiar with logic gate IC numbers and pin configurations if your syllabus includes practical electronics.

第三，在根据逻辑图填写真值表时，反复检查是否为n个输入列出了2ⁿ行，并且不要遗漏任何中间信号。第四，在卡诺图题目中，始终检查卡诺图是否给出了比最初提供的更简单的表达式——这通常能发现冗余项。最后，练习仅使用与非门和仅使用或非门之间的转换，因为这在考试的第二部分非常常见。特别对于CIE，如果你的教学大纲包含实用电子学，请熟悉逻辑门IC编号和引脚配置。

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Logic Gates Exam Focus | 逻辑门 考点精讲