📚 A-Level WJEC Computer Science: Computer Architecture Key Points | A-Level WJEC计算机：计算机体系结构 考点精讲
Computer architecture forms the foundation of understanding how a computer’s processor works, how data flows, and how instructions are executed. This article covers the essential topics for the WJEC A-Level Computer Science specification, including the components of the central processing unit, registers, the fetch-decode-execute cycle, buses, cache memory, pipelining, and factors affecting performance. By mastering these concepts, you’ll be well-prepared for exam questions on the inner workings of a computer system.
计算机体系结构是理解计算机处理器如何工作、数据如何流动以及指令如何执行的基础。本文涵盖了WJEC A-Level计算机科学考试大纲中的核心内容，包括中央处理器各组件、寄存器、取指-译码-执行周期、总线、高速缓存、流水线技术以及影响性能的因素。掌握这些概念，你将能够从容应对有关计算机系统内部运作的考试题目。
1. Overview of the CPU and Its Components | CPU及其组件概述
The Central Processing Unit (CPU) is often referred to as the ‘brain’ of the computer. It carries out instructions provided by programs. The CPU consists of several key components: the Control Unit (CU), the Arithmetic Logic Unit (ALU), registers, and internal buses. The CU directs operations, the ALU performs calculations and logical comparisons, registers provide high-speed temporary storage, and buses connect these parts together.
中央处理器（CPU）常被称为计算机的“大脑”。它执行程序提供的指令。CPU由几个关键组件构成：控制单元（CU）、算术逻辑单元（ALU）、寄存器以及内部总线。控制单元指挥操作，算术逻辑单元执行计算和逻辑比较，寄存器提供高速临时存储，总线将这些部分连接在一起。
A typical CPU also includes a clock that synchronises all operations by generating a steady pulse. The clock speed, measured in gigahertz (GHz), indicates how many cycles per second the CPU can perform, although this is not the only measure of performance.
典型的CPU还包含一个时钟，通过产生稳定的脉冲来同步所有操作。时钟速度以吉赫兹（GHz）为单位，表明CPU每秒可以执行多少个周期，但这并不是衡量性能的唯一标准。
2. The Arithmetic Logic Unit and Control Unit | 算术逻辑单元与控制单元
The Arithmetic Logic Unit (ALU) handles all arithmetic operations (addition, subtraction, etc.) and logical operations (AND, OR, NOT, XOR). It receives operands from registers, performs the operation, and stores the result back into a register. The ALU is fundamental to executing every instruction that involves data manipulation.
算术逻辑单元（ALU）处理所有算术运算（加法、减法等）和逻辑运算（与、或、非、异或）。它从寄存器接收操作数，执行运算，并将结果存回寄存器。ALU是执行每条涉及数据操作的指令的基础。
The Control Unit (CU) manages the execution of instructions. It decodes instructions fetched from memory, generates control signals to coordinate the movement of data through the processor, and directs the ALU as needed. The CU uses the program counter to keep track of the next instruction to execute.
控制单元（CU）管理指令的执行。它对从内存取出的指令进行译码，生成控制信号来协调数据在处理器中的移动，并按要求指挥ALU。控制单元使用程序计数器来跟踪下一条要执行的指令。
Together, the CU and ALU form the core execution engine. While the CU handles the ‘what to do next’, the ALU handles the ‘actual processing’.
CU和ALU共同构成了核心执行引擎。控制单元负责“下一步做什么”，而ALU负责“实际处理”。
3. Essential Registers in the CPU | CPU中的核心寄存器
Registers are small, extremely fast memory locations within the CPU. The most important registers you need to know for WJEC include: Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), Current Instruction Register (CIR), and the Accumulator (ACC).
寄存器是CPU内部容量小、速度极快的存储位置。WJEC考试中需要掌握的最重要的寄存器包括：程序计数器（PC）、内存地址寄存器（MAR）、内存数据寄存器（MDR）、当前指令寄存器（CIR）和累加器（ACC）。
| Register | Abbreviation | Function |
|---|---|---|
| Program Counter | PC | Holds the memory address of the next instruction to be fetched. |
| Memory Address Register | MAR | Stores the address of memory location to be read from or written to. |
| Memory Data Register | MDR | Temporarily holds data just read from memory or data to be written to memory. |
| Current Instruction Register | CIR | Contains the current instruction being executed, split into opcode and operand. |
| Accumulator | ACC | Stores intermediate results of calculations performed by the ALU. |
In the WJEC specification, you may also encounter the Index Register (IX) and Status Register. The Index Register is used for indexed addressing, while the Status Register contains flags (e.g., zero, carry, overflow) that reflect the outcome of the last operation.
在WJEC考试大纲中，你可能会遇到变址寄存器（IX）和状态寄存器。变址寄存器用于变址寻址，而状态寄存器包含标志位（如零、进位、溢出），它们反映上一次操作的结果。
4. The Fetch-Decode-Execute Cycle | 取指-译码-执行周期
The fetch-decode-execute cycle (FDE cycle) is the fundamental process by which the CPU operates. It repeats continuously while the computer is running, executing instructions one after another.
取指-译码-执行周期（FDE周期）是CPU运行的基本过程。它在计算机运行时不断重复，逐条执行指令。
Fetch stage: The address in the PC is copied to the MAR. A read signal is sent to memory. The instruction stored at that address is retrieved and placed in the MDR. The instruction is then copied to the CIR. The PC is incremented to point to the next instruction.
取指阶段：将PC中的地址复制到MAR。向内存发送读信号。该地址处存储的指令被取出并放入MDR。然后指令被复制到CIR。PC递增，指向下一条指令。
Decode stage: The CU decodes the instruction in the CIR. The bit pattern is split into the opcode (operation code) and operand (data or address). The CU identifies what operation is required and prepares the necessary control signals.
译码阶段：CU对CIR中的指令进行译码。位模式被分为操作码（操作代码）和操作数（数据或地址）。CU识别所需执行的操作并准备必要的控制信号。
Execute stage: The operation is carried out. If data movement is required, addresses may be placed on the MAR, data read to or from the MDR. The ALU may be activated to perform a computation, with the result placed in the ACC or another register. Once complete, the cycle starts again with the next fetch.
执行阶段：执行操作。如果需要数据移动，地址可能被放入MAR，数据被读入或写出MDR。可能会激活ALU进行计算，结果放入ACC或其他寄存器。完成后，周期重新开始下一次取指。
5. The System Buses: Data, Address, and Control | 系统总线：数据、地址和控制
Buses are sets of parallel wires that transfer data between the CPU, memory, and I/O devices. There are three main buses: the address bus, the data bus, and the control bus. Each is unidirectional or bidirectional depending on its role.
总线是一组并行导线，用于在CPU、内存和I/O设备之间传输数据。有三种主要总线：地址总线、数据总线和控制总线。每种总线根据其作用可以是单向或双向的。
- Address bus (unidirectional): Carries memory addresses from the CPU to memory or I/O. The width of the address bus determines the maximum addressable memory size. For example, a 32-bit address bus can address 2³² memory locations.
- 地址总线（单向）：将内存地址从CPU传输到内存或I/O。地址总线的宽度决定了可寻址的最大内存容量。例如，32位地址总线可寻址2³²个内存位置。
- Data bus (bidirectional): Transfers data between the CPU and memory or I/O devices. Its width affects the amount of data that can be moved in a single operation. A wider data bus allows more data to be transferred per clock cycle.
- 数据总线（双向）：在CPU与内存或I/O设备之间传输数据。其宽度影响单次操作可移动的数据量。更宽的数据总线允许每个时钟周期传输更多的数据。
- Control bus (bidirectional): Carries control signals such as memory read, memory write, I/O read, I/O write, interrupt request, and clock signals. These signals coordinate activities across the system.
- 控制总线（双向）：传输控制信号，如内存读、内存写、I/O读、I/O写、中断请求和时钟信号。这些信号协调整个系统的活动。
6. Memory Hierarchy and Cache | 存储层次与高速缓存
Memory hierarchy describes the arrangement of storage types based on speed, size, and cost. At the top are registers (fastest, smallest), followed by cache, main memory (RAM), and secondary storage (slowest, largest). The goal is to provide a balance between access speed and storage capacity.
存储层次描述了根据速度、容量和成本排列的存储类型。最顶层是寄存器（最快、最小），其次是高速缓存、主存储器（RAM）和辅助存储器（最慢、最大）。其目标是在访问速度和存储容量之间取得平衡。
Cache memory is a small amount of high-speed SRAM that sits between the CPU and main memory. It stores frequently used instructions and data to reduce the average time to access memory. Modern processors typically have multiple levels of cache: L1 (smallest, fastest, built into CPU core), L2 (larger, slightly slower), and sometimes L3 (shared among cores).
高速缓存是介于CPU和主存之间的一小段高速静态随机存取存储器（SRAM）。它存储频繁使用的指令和数据，以减少访问内存的平均时间。现代处理器通常具有多级缓存：L1（最小、最快，内置于CPU核心）、L2（更大、稍慢），有时还有L3（在核心之间共享）。
When the CPU needs data, it first checks L1 cache (hit or miss). If missed, it checks L2, then main memory. The concept of locality of reference ensures that cache is effective: temporal locality (recently accessed data likely to be accessed again) and spatial locality (data near recently accessed data are likely needed).
当CPU需要数据时，它首先检查L1缓存（命中或未命中）。如果不命中，则检查L2，然后是主存。局部性原理确保了缓存的有效性：时间局部性（最近访问的数据可能再次被访问）和空间局部性（最近访问的数据附近的数据可能会被需要）。
7. Processor Performance Factors | 影响处理器性能的因素
Several factors determine how quickly a processor can execute programs. The main factors include clock speed, number of cores, cache size and levels, and the architecture itself (including pipelining and instruction set design).
有几个因素决定了处理器执行程序的速度。主要因素包括时钟速度、核心数量、缓存大小和级别，以及体系结构本身（包括流水线和指令集设计）。
- Clock speed: A higher clock rate means more cycles per second, so ideally more instructions can be completed. However, this also increases power consumption and heat generation.
- 时钟速度：更高的时钟频率意味着每秒更多周期，因此在理想情况下可完成更多指令。然而，这也会增加功耗和发热。
- Number of cores: A multi-core processor can execute multiple threads or processes simultaneously. True performance improvement depends on whether software can be parallelised effectively.
- 核心数量：多核处理器可同时执行多个线程或进程。真正的性能提升取决于软件是否能够有效并行化。
- Cache size: Larger caches reduce the frequency of accesses to slower main memory, improving performance for repetitive tasks and large data sets.
- 缓存大小：更大的缓存减少了对较慢主存的访问频率，从而提高了重复性任务和大数据集的性能。
- Pipelining: Allows overlapping of instruction stages, so that one instruction is being fetched while another is decoded and another executed. This increases throughput.
- 流水线：允许指令阶段重叠，即在一条指令取指的同时，另一条译码、另一条执行。这提高了吞吐量。
- Word length and bus widths: A processor with a larger word length (e.g., 64-bit) can handle more data per operation and address more memory.
- 字长和总线宽度：字长较大（如64位）的处理器每次操作可以处理更多数据，并可寻址更多内存。
8. Pipelining and Its Challenges | 流水线及其挑战
Pipelining divides the instruction cycle into stages (such as fetch, decode, execute, memory access, write-back), with each stage handled by a separate part of the hardware. Like an assembly line, a new instruction can start before the previous one finishes, ideally producing one instruction result per clock cycle after the pipeline is filled.
流水线将指令周期划分为多个阶段（如取指、译码、执行、内存访问、写回），每个阶段由硬件的不同部分处理。就像装配线一样，新指令可以在前一条指令完成之前启动，在流水线填满后，理想情况下每个时钟周期可产生一个指令结果。
However, pipelining introduces problems such as data hazards, control hazards, and structural hazards. A data hazard occurs when an instruction depends on the result of a previous instruction that is still in the pipeline. Control hazards arise from branch instructions that change the flow of execution, potentially requiring the pipeline to be flushed. Structural hazards occur when hardware resources are insufficient to support all concurrent stages.
然而，流水线带来了数据冒险、控制冒险和结构冒险等问题。数据冒险发生在一条指令依赖于仍在流水线中的前一条指令的结果时。控制冒险源于改变执行流程的分支指令，可能需要清空流水线。结构冒险发生在硬件资源不足以支持所有并发阶段时。
WJEC candidates should be aware of techniques like forwarding (bypassing) and branch prediction used to mitigate these hazards. Stalling (inserting NOPs or bubbles) is the simplest solution but reduces efficiency.
WJEC考生应了解用于缓解这些冒险的技术，如前推（旁路）和分支预测。停顿（插入空操作或气泡）是最简单的解决方法，但会降低效率。
9. CISC vs RISC Architectures | CISC与RISC架构
Processors can be classified by their instruction set architecture. Two common types are CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer). The WJEC specification expects you to compare these.
处理器可根据其指令集架构进行分类。两种常见类型是CISC（复杂指令集计算机）和RISC（精简指令集计算机）。WJEC考试大纲要求对两者进行比较。
| Feature | CISC | RISC |
|---|---|---|
| Instruction set | Large, complex instructions | Small, simple instructions |
| Instruction length | Variable | Fixed |
| Execution time | Many instructions take multiple cycles | Most instructions execute in one clock cycle |
| Hardware emphasis | Complex hardware to decode variable instructions | Complex compiler to optimise simple instructions |
| Addressing modes | Many addressing modes | Few addressing modes |
| Examples | x86-based processors | ARM processors |
RISC designs rely on simple instructions that can be pipelined efficiently, while CISC designs aim to accomplish more with a single instruction, potentially reducing the number of instructions per program. In practice, modern processors often use a hybrid approach, with CISC front-ends translating into RISC-like micro-operations internally.
RISC设计依赖于可被高效流水线处理的简单指令，而CISC设计旨在用单条指令完成更多任务，从而可能减少每个程序的指令数量。实际上，现代处理器常采用混合方法，CISC前端内部转换为类似RISC的微操作。
10. Buses and I/O Communication | 总线与I/O通信
Input/Output (I/O) devices communicate with the CPU and memory via buses. To manage different speeds, I/O controllers or interfaces are used. The control bus coordinates whether data is being transferred to memory or to an I/O port (memory-mapped I/O vs port-mapped I/O). Memory-mapped I/O uses the same address space for memory and I/O devices, while port-mapped I/O uses a separate address space and special instructions.
输入/输出（I/O）设备通过总线与CPU和内存通信。为管理不同速度，使用了I/O控制器或接口。控制总线协调数据是传输到内存还是I/O端口（内存映射I/O与端口映射I/O）。内存映射I/O使用相同的地址空间给内存和I/O设备，而端口映射I/O使用独立的地址空间和专用指令。
Interrupts are signals from hardware or software that cause the CPU to pause its current process and execute an interrupt service routine. Vectored interrupts provide the address of the handler directly, while non-vectored or polled interrupts require the CPU to check each device. This mechanism allows the processor to respond to high-priority events without constant polling, improving efficiency.
中断是来自硬件或软件的信号，使CPU暂停当前进程并执行中断服务例程。向量化中断直接提供处理程序的地址，而非向量化或轮询中断需要CPU检查每个设备。这种机制使处理器无需不断轮询即可响应高优先级事件，从而提高了效率。
11. Parallel Processing and Multi-core Systems | 并行处理与多核系统
Parallel processing involves using multiple processors or cores to execute multiple tasks simultaneously. This can be achieved through multicore processors (several processing units on a single chip) or through symmetric multiprocessing (multiple identical processors sharing the same memory).
并行处理涉及使用多个处理器或核心同时执行多个任务。这可以通过多核处理器（单个芯片上的多个处理单元）或对称多处理（多个相同处理器共享同一内存）来实现。
In a multicore system, each core typically has its own L1 cache but shares L2 or L3 cache. The operating system must schedule threads across cores efficiently. Parallelism can be at the instruction level (pipelining, superscalar) or at the data/task level. Amdahl’s law describes the theoretical speedup possible through parallelism, limited by the sequential portion of any program.
在多核系统中，每个核心通常有自己的L1缓存，但共享L2或L3缓存。操作系统必须有效地在各个核心之间调度线程。并行性可以是指令级并行（流水线、超标量）或数据/任务级并行。阿姆达尔定律描述了通过并行性可能达到的理论加速比，该加速比受到任何程序中串行部分的限制。
WJEC does not require deep calculations, but you should appreciate that a program must be written to take advantage of multiple cores; a sequential program will only use one core.
WJEC不要求深入的计算，但你应该理解程序必须编写成能利用多核优势；顺序程序只会使用一个核心。
12. GPU and Co-processors | 图形处理器与协处理器
While the CPU is designed for general-purpose processing, co-processors such as Graphics Processing Units (GPUs) are specialised for parallel throughput-intensive tasks. A GPU contains hundreds or thousands of simpler cores optimised for data-parallel operations, such as vector and matrix calculations, making it ideal for graphics rendering, machine learning, and scientific simulations.
虽然CPU是为通用处理而设计的，但协处理器如图形处理器（GPU）则专用于并行吞吐量密集型任务。GPU包含数百或数千个更简单的核心，针对数据并行操作（如向量和矩阵计算）进行了优化，使其成为图形渲染、机器学习和科学模拟的理想选择。
In the WJEC context, you need to understand that a GPU offloads graphics processing from the CPU, improving overall system performance for visual tasks. They connect via high-bandwidth interfaces like PCI Express and have their own dedicated memory (VRAM).
在WJEC的语境中，你需要理解GPU将图形处理从CPU中卸载，从而提高了视觉任务的系统整体性能。它们通过高带宽接口（如PCI Express）连接，并拥有自己的专用内存（VRAM）。
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