A-Level WJEC Computer Science: CPU Exam Points Explained | A-Level WJEC 计算机：CPU 考点精讲

📚 A-Level WJEC Computer Science: CPU Exam Points Explained | A-Level WJEC 计算机：CPU 考点精讲

The central processing unit (CPU) is the heart of every computer system, executing instructions and processing data. For the WJEC A-Level Computer Science specification, a deep understanding of CPU architecture, the fetch-decode-execute cycle, factors affecting performance, and contemporary processor technologies is essential. This article breaks down every key concept, common pitfalls, and exam-style insights to help you secure top marks.

中央处理器（CPU）是每台计算机系统的核心，负责执行指令和处理数据。在 WJEC A-Level 计算机科学大纲中，深入理解 CPU 架构、取指-解码-执行循环、影响性能的因素以及当代处理器技术是至关重要的。本文将逐一解析每个关键概念、常见易错点和应试方法，帮助你稳拿高分。

1. The Role of the CPU | CPU 的角色

The CPU processes data by continuously following the fetch-execute cycle. It acts as the brain of the computer, carrying out instructions from programs and managing the flow of data between memory and peripherals.

CPU 通过不断执行取指-执行循环来处理数据。它如同计算机的大脑，执行程序指令并管理内存与外围设备之间的数据流动。

The CPU is responsible for arithmetic and logical operations (ALU), control of data movement (CU), and temporary storage in registers.
CPU 负责算术与逻辑运算（ALU）、数据移动控制（CU）以及寄存器中的临时存储。
It fetches instructions from main memory (RAM) one at a time, decodes them, and executes the necessary operation.
它从主存（RAM）逐条取出指令，进行解码并执行相应操作。

2. The Von Neumann Architecture | 冯·诺依曼架构

The WJEC specification focuses on the Von Neumann architecture, where both data and instructions are stored in the same memory unit. This stored-program concept allows programs to be treated as data, making general-purpose computing possible.

WJEC 大纲聚焦于冯·诺依曼架构，其核心是数据与指令存储在同一内存单元中。这种存储程序概念使程序可以当作数据处理，从而实现了通用计算。

Key components: Control Unit (CU), Arithmetic Logic Unit (ALU), registers, memory unit, and input/output interfaces.
关键组件：控制单元（CU）、算术逻辑单元（ALU）、寄存器、内存单元和输入/输出接口。
Instructions and data share the same bus system, which can become a bottleneck (the Von Neumann bottleneck).
指令和数据共享相同的总线系统，这可能导致瓶颈（冯·诺依曼瓶颈）。
Exam tip: be prepared to compare Von Neumann with Harvard architecture (separate memory for instructions and data).
应试提示：准备好比较冯·诺依曼与哈佛架构（指令和数据使用分离的内存）。

3. Fetch-Decode-Execute Cycle | 取指-解码-执行循环

This is the fundamental operation of the CPU. WJEC exam questions frequently ask you to describe the cycle in detail, naming specific registers and buses at each stage.

这是 CPU 的基本运作方式。WJEC 考题常要求详细描述该循环，在每一阶段指定具体的寄存器和总线。

Fetch: The address in the Program Counter (PC) is placed on the address bus; the instruction at that address is fetched from RAM into the Memory Data Register (MDR), and then copied to the Current Instruction Register (CIR). The PC is incremented.
取指：程序计数器（PC）中的地址送至地址总线；从 RAM 中取出该地址处的指令送至内存数据寄存器（MDR），然后复制到当前指令寄存器（CIR）。PC 增加以指向下一条指令。
Decode: The Control Unit decodes the instruction in the CIR, splitting it into opcode and operand if present.
解码：控制单元对 CIR 中的指令进行解码，将其拆分为操作码和操作数（如有）。
Execute: The instruction is carried out; this may involve the ALU for arithmetic/logic operations, memory read/write, or I/O operations. Data may be transferred between registers via the internal data bus.
执行：执行指令；这可能涉及 ALU 进行算术/逻辑运算、内存读写或 I/O 操作。数据可能通过内部数据总线在寄存器之间传输。
The cycle repeats, with the PC now pointing to the next instruction (unless a jump/branch occurred).
循环重复进行，此时 PC 已指向下一条指令（除非发生了跳转/分支）。

4. The Control Unit (CU) | 控制单元（CU）

The CU orchestrates all activities within the CPU. It controls the flow of data between registers and the execution of instructions through timing signals.

控制单元协调 CPU 内部的所有活动。它通过时序信号控制寄存器之间的数据流动和指令的执行。

The CU decodes instructions and generates control signals to manage the ALU, memory reads/writes, and I/O requests.
CU 解码指令并生成控制信号，以管理 ALU、内存读写以及 I/O 请求。
It uses a clock to synchronise operations; one instruction may take multiple clock cycles.
它使用时钟同步操作；一条指令可能需要多个时钟周期。
The CU contains the decoder and sequencing logic. It does not store user data.
CU 包含解码器和时序逻辑。它不存储用户数据。

5. The Arithmetic Logic Unit (ALU) | 算术逻辑单元（ALU）

The ALU performs all arithmetic and logical operations. It takes operands from registers, applies the operation specified by the CU, and stores the result in the accumulator or a general-purpose register.

ALU 执行所有算术和逻辑运算。它从寄存器获取操作数，执行由 CU 指定的操作，并将结果存入累加器或通用寄存器。

Arithmetic operations: addition, subtraction, multiplication, division (often via shift/add algorithms).
算术运算：加、减、乘、除（通常通过移位/加法算法实现）。
Logic operations: AND, OR, NOT, XOR, comparisons, and bitwise shifts.
逻辑运算：AND、OR、NOT、XOR、比较以及按位移位。
The ALU’s status flags (e.g., zero, carry, overflow, negative) are stored in the Program Status Word (PSW) or flag register, used for conditional branching.
ALU 的状态标志（如零、进位、溢出、负号）存储在程序状态字（PSW）或标志寄存器中，用于条件分支。

6. Registers and Their Roles | 寄存器及其作用

Registers are small, extremely fast memory locations within the CPU. WJEC expects you to know the purpose of each major register.

寄存器是 CPU 内部极小且极快的存储位置。WJEC 要求你掌握各个主要寄存器的用途。

Register	Role	寄存器	作用
Program Counter (PC)	Holds the address of the next instruction to be fetched.	程序计数器	存放下一条要取指指令的地址。
Current Instruction Register (CIR)	Holds the instruction currently being decoded and executed.	当前指令寄存器	存放正在被解码和执行的指令。
Memory Address Register (MAR)	Holds the address of the memory location to be read from or written to.	内存地址寄存器	存放要读或写的内存地址。
Memory Data Register (MDR)	Holds data fetched from or to be written to memory (also called Memory Buffer Register, MBR).	内存数据寄存器	存放从内存读取或要写入内存的数据（也称内存缓冲寄存器 MBR）。
Accumulator (ACC)	Stores the results of ALU operations temporarily.	累加器	暂存 ALU 的运算结果。
Index Register (IX)	Used for indexed addressing; holds a base offset for array access.	变址寄存器	用于变址寻址；存放数组访问的基地址偏移量。
Status Register (SR)	Contains flag bits that reflect the outcome of operations (carry, zero, overflow, negative).	状态寄存器	包含反映运算结果的标志位（进位、零、溢出、负号）。

WJEC often tests the movement of data between specific registers during the fetch-execute cycle. Be precise: PC → MAR, MAR → address bus, RAM → data bus → MDR, MDR → CIR, then decode.

WJEC 常考查取指-执行循环中特定寄存器之间的数据移动。要精确描述：PC → MAR，MAR → 地址总线，RAM → 数据总线 → MDR，MDR → CIR，然后解码。

7. Buses: Data, Address, and Control | 总线：数据、地址与控制

Three buses connect the CPU to memory and I/O devices. Understanding bus widths and their implications is a common WJEC exam topic.

三组总线将 CPU 连接到内存和 I/O 设备。理解总线宽度及其影响是 WJEC 常见的考题。

Data bus: Carries data between CPU and memory/peripherals. Its width (e.g., 8-bit, 16-bit, 32-bit) determines how many bits can be transferred simultaneously; a wider data bus can improve performance.
数据总线：在 CPU 与内存/外设之间传输数据。其宽度（如 8 位、16 位、32 位）决定了每次可同时传输的位数；更宽的数据总线可以提升性能。
Address bus: Carries memory addresses from the CPU to specify which location is being accessed. Its width determines the maximum addressable memory (e.g., 32-bit address bus can address 2³² locations).
地址总线：从 CPU 传输内存地址，指定要访问的存储单元。其宽度决定了最大可寻址内存空间（如 32 位地址总线可寻址 2³² 个单元）。
Control bus: Carries control signals such as read/write, clock, interrupt requests, and bus grant. Each line performs a specific function.
控制总线：传输读写、时钟、中断请求、总线授权等控制信号。每条线路负责一项特定功能。
Exam favourite: explain why increasing address bus width does not automatically speed up the CPU (it only expands memory capacity).
常考内容：解释为何增加地址总线宽度并不会自动提升 CPU 速度（它只是扩展了内存容量）。

8. CPU Performance Factors | CPU 性能因素

Performance is not just about clock speed. WJEC expects balanced analysis across multiple factors.

性能不仅仅关乎时钟频率。WJEC 期望多方面的均衡分析。

Factor	Effect on Performance	因素	对性能的影响
Clock Speed	More cycles per second → more instructions executed per second (assuming same IPC). However, higher clocks generate more heat and may be limited by the physics of transistor switching.	时钟速度	每秒更多周期 → 每秒执行更多指令（假定 IPC 相同）。但更高频率产生更多热量，并受晶体管开关物理极限的限制。
Number of Cores	Multiple cores allow true parallel execution of threads/processes. Speedup depends on software parallelism; Amdahl’s Law limits gains.	核心数量	多核心允许真正的并行执行线程/进程。加速效果取决于软件并行度；阿姆达尔定律限制了提升空间。
Cache Memory	Small, fast memory located close to the CPU. Larger cache (L1, L2, L3) reduces the average time to access data, mitigating the Von Neumann bottleneck.	高速缓存	靠近 CPU 的小型快速内存。更大的缓存（L1、L2、L3）减少了访问数据的平均时间，缓解了冯·诺依曼瓶颈。
Word Length / Bus Width	A CPU with a 64-bit word length can process larger chunks of data per cycle and access wider memory addresses, improving throughput.	字长/总线宽度	64 位字长的 CPU 每周期可处理更大块的数据并访问更宽的内存地址，从而提高吞吐量。
Instruction Set Architecture (RISC/CISC)	RISC processors use simpler instructions, generally one per clock cycle, allowing efficient pipelining; CISC processors have complex instructions that may take multiple cycles but reduce the number of instructions per task.	指令集架构（RISC/CISC）	RISC 处理器使用简单指令，一般每周期一条，便于高效流水线；CISC 处理器包含复杂指令，可能耗时多个周期但减少了任务所需指令数。

WJEC answers should always link the factor to the fetch-execute cycle: e.g., higher clock speed means each stage completes faster; more cache reduces wait states.

WJEC 的答案务必将该因素与取指-执行循环关联起来：例如，更高的时钟速度意味着每个阶段完成更快；更大的缓存减少了等待状态。

9. Pipelining and Parallelism | 流水线与并行处理

Pipelining is an instruction-level parallelism technique used in modern CPUs. It overlaps the fetch, decode, and execute stages for multiple instructions, improving throughput without increasing clock speed.

流水线是现代 CPU 中采用的一种指令级并行技术。它重叠多条指令的取指、解码和执行阶段，在不提高时钟频率的情况下提高吞吐量。

In a five-stage pipeline (fetch, decode, execute, memory, write-back), up to five instructions can be processed simultaneously at different stages.
在五级流水线（取指、解码、执行、访存、写回）中，最多可有五条指令同时在各级处理。
Hazards: Data hazards (dependencies between instructions), control hazards (branch mispredictions), and structural hazards (resource conflicts) can stall the pipeline. WJEC may ask about branch prediction or pipeline bubbles.
冒险：数据冒险（指令间依赖性）、控制冒险（分支预测错误）和结构冒险（资源冲突）会导致流水线停顿。WJEC 可能涉及分支预测或流水线气泡。
Parallelism also extends to SIMD (Single Instruction, Multiple Data) and superscalar architectures, where multiple instructions are issued per clock cycle.
并行性还扩展到 SIMD（单指令多数据流）和超标量架构，后者支持每个时钟周期发射多条指令。

10. Cache Memory and the Memory Hierarchy | 高速缓存与内存层次

Cache bridges the speed gap between the fast CPU and relatively slow main memory. WJEC expects you to describe the levels of cache and their role in the memory hierarchy.

缓存弥补了快速 CPU 与相对较慢的主存之间的速度差距。WJEC 要求你描述各级缓存及其在内存层次中的作用。

L1 cache (Level 1): smallest and fastest, usually split into instruction cache and data cache, built into the CPU core.
L1 缓存：最小且最快，通常分为指令缓存和数据缓存，内置于 CPU 核心内部。
L2 cache: larger and slightly slower, often unified (both instructions and data), may be shared among cores.
L2 缓存：较大且稍慢，通常为统一缓存（指令和数据共用），可能在核心之间共享。
L3 cache: even larger, shared across all cores on the chip, improves performance for multi-threaded workloads.
L3 缓存：更大，为芯片上所有核心共享，能提升多线程工作负载的性能。
The principle of locality: temporal locality (recently accessed data likely to be accessed again) and spatial locality (nearby addresses likely to be accessed soon) make caching highly effective.
局部性原理：时间局部性（最近访问的数据很可能再次访问）和空间局部性（邻近地址很可能即将被访问）使缓存非常高效。
Cache hit and miss: a hit avoids main memory access; a miss fetches an entire cache line from RAM, replacing existing data based on a replacement policy (e.g., LRU).
缓存命中与缺失：命中无需访问主存；缺失则从 RAM 获取整条缓存行，依据替换策略（如 LRU）替换现有数据。

11. RISC and CISC Architectures | RISC 与 CISC 架构

WJEC candidates must compare Reduced Instruction Set Computers (RISC) and Complex Instruction Set Computers (CISC) in detail.

WJEC 考生必须详细比较精简指令集计算机（RISC）和复杂指令集计算机（CISC）。

RISC	CISC	RISC	CISC
Small instruction set, simple instructions, fixed length (e.g., 32-bit).	Large instruction set, complex instructions, variable length.	指令集小，指令简单，定长（如 32 位）。	指令集大，指令复杂，变长。
One instruction per clock cycle (ideally); easy pipelining.	Instructions can take multiple clock cycles; harder to pipeline efficiently.	每条指令一个时钟周期（理想情况）；易于流水线。	指令可耗时多个时钟周期；难以高效流水线。
Load/store architecture: only LOAD and STORE instructions access memory; others operate on registers.	Many instructions can access memory directly (register-memory operations).	加载/存储架构：只有 LOAD 和 STORE 指令访问内存；其他指令操作寄存器。	很多指令可直接访问内存（寄存器-内存操作）。
Requires more RAM for program code (higher instruction count for the same task).	Programs can be smaller (fewer instructions) because of complex instructions.	程序代码需更多 RAM（同一任务的指令数更多）。	程序可能更小（指令数更少），因为指令复杂。
Examples: ARM, RISC-V.	Example: x86.	例子：ARM、RISC-V。	例子：x86。

Modern CPUs often use CISC front-end with RISC-like back-end micro-operations. WJEC may ask for an evaluation: which is “better” depends on the application environment.

现代 CPU 常采用 CISC 前端配合类 RISC 后端微操作。WJEC 可能要求进行评估：何者更优取决于应用环境。

12. Multicore and Parallel Processing | 多核与并行处理

Multicore processors integrate two or more independent cores on a single chip, sharing some resources like L3 cache and memory interfaces. WJEC expects you to discuss the benefits and limitations.

多核处理器在单个芯片上集成两个或更多独立核心，共享 L3 缓存和内存接口等资源。WJEC 期望你探讨其优势和局限性。

True parallelism: each core can execute its own thread or process independently.
真正的并行性：每个核心可独立执行各自的线程或进程。
Coherency and consistency: caches must be kept consistent across cores (MESI protocol).
一致性与连贯性：缓存必须在核心间保持一致性（MESI 协议）。
Amdahl’s Law limits speedup: even with infinite cores, the sequential portion of a program restricts maximum acceleration. Speedup = 1 / (s + (1-s)/p), where s is sequential fraction and p is number of cores.
阿姆达尔定律限制加速比：即便有无限核心，程序的串行部分仍会限制最大加速。加速比 = 1 / (s + (1-s)/p)，其中 s 为串行比例，p 为核心数。
WJEC questions often link multicore to multitasking operating systems and the ability to run multiple applications smoothly.
WJEC 题目常将多核与多任务操作系统及流畅运行多个应用程序的能力联系起来。

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A-Level WJEC Computer Science: CPU Exam Points Explained | A-Level WJEC 计算机：CPU 考点精讲