Computer Architecture - Core Concepts for IB & CCEA | 计算机体系结构

📚 Computer Architecture – Core Concepts for IB & CCEA | 计算机体系结构 – IB 与 CCEA 核心考点精讲

This article distills the essential topics in computer architecture for IB and CCEA Computer Science syllabi. We explore the von Neumann model, CPU components, the fetch-execute cycle, memory hierarchy, and factors affecting system performance. Each section pairs concise English explanations with Chinese translations, ensuring you grasp both the terminology and the underlying principles. Use this as your revision companion for exam success.

本文提炼了 IB 与 CCEA 计算机科学大纲中计算机体系结构的核心考点。我们将逐一讲解冯·诺依曼模型、CPU 组成、取指–执行周期、存储层次以及影响系统性能的因素。每节均提供简洁的英文解释与中文翻译，帮助你同时掌握专业术语和底层原理。请将本文作为备考伴侣，助你冲刺高分。

1. The Von Neumann Architecture | 冯·诺依曼体系结构

The von Neumann architecture is the foundational design for most modern computers. It stores both program instructions and data in a single, shared memory unit, and processes them sequentially through a central processing unit (CPU). Key components include the control unit (CU), arithmetic logic unit (ALU), memory, input/output devices, and the system bus that connects them.

冯·诺依曼体系结构是大多数现代计算机的基础设计。它将程序指令和数据存放在同一个共享内存单元中，并通过中央处理器 (CPU) 顺序处理。关键部件包括控制单元 (CU)、算术逻辑单元 (ALU)、存储器、输入/输出设备以及连接它们的数据总线。

A defining feature is the stored-program concept: instructions are fetched from memory, decoded, and executed one after another. This sequential model, while simple, creates the ‘von Neumann bottleneck’ because the same bus carries both instructions and data, limiting the speed at which they can be transferred.

其标志性特征是存储程序概念：指令从内存中取出、译码然后逐条执行。这种顺序模型虽然简单，却产生了“冯·诺依曼瓶颈”——因为同一条总线既要传输指令又要传输数据，限制了传输速度。

2. CPU Components and Their Roles | CPU 主要部件及其作用

The CPU is the ‘brain’ of the computer. Its primary components are the control unit (CU), which directs operations by sending timing and control signals; the arithmetic logic unit (ALU), which performs calculations and logical comparisons; and a set of registers that provide high-speed temporary storage during execution.

CPU 是计算机的“大脑”。其主要部件包括：控制单元 (CU)，通过发送时序和控制信号指挥操作；算术逻辑单元 (ALU)，执行计算与逻辑比较；以及一组寄存器，在执行期间提供高速临时存储。

Key registers include the program counter (PC) – holds the address of the next instruction; the memory address register (MAR) – holds the address being accessed in memory; the memory data register (MDR) – holds the data transferred to or from memory; the current instruction register (CIR) – holds the instruction currently being executed; and the accumulator (ACC) – stores results from the ALU.

关键寄存器有：程序计数器 (PC) – 存放下一条指令的地址；内存地址寄存器 (MAR) – 存放当前正在访问的内存地址；内存数据寄存器 (MDR) – 存放与内存之间传输的数据；当前指令寄存器 (CIR) – 存放正在执行的指令；累加器 (ACC) – 暂存 ALU 的运算结果。

3. The Fetch-Decode-Execute Cycle | 取指–译码–执行周期

The fetch-decode-execute cycle is the heartbeat of the CPU. In the fetch phase, the address in the PC is copied to the MAR, a read signal is sent to memory, and the instruction is loaded into the MDR, then transferred to the CIR. The PC is then incremented to point to the next instruction.

取指–译码–执行周期是 CPU 的“心跳”。在取指阶段，PC 中的地址被复制到 MAR，随即向内存发出读信号，指令被加载到 MDR，然后传送至 CIR。随后 PC 递增，指向下一条指令。

During decode, the control unit interprets the instruction held in the CIR, breaking it into opcode (operation to perform) and operand (the data or address involved). In the execute phase, the CU activates the necessary circuits – if a calculation is needed, the ALU is engaged; if data movement is required, the appropriate registers and buses are enabled.

在译码阶段，控制单元解释 CIR 中的指令，将其拆分为操作码（要执行的操作）和操作数（涉及的数据或地址）。在执行阶段，CU 激活所需电路——若需计算则调用 ALU；若需数据移动则启用相应寄存器和总线。

This cycle repeats billions of times per second in a modern processor. The clock speed, measured in hertz, determines how many cycles can occur each second. Overlapping parts of the cycle (pipelining) can improve throughput.

在现代处理器中，该周期每秒重复数十亿次。以赫兹为单位的时钟频率决定了每秒可执行多少个周期。将周期各阶段重叠（流水线技术）可以提高吞吐量。

4. The System Bus and Data Pathways | 系统总线与数据通路

The system bus is a collection of parallel wires that carry information between the CPU, memory, and I/O devices. It is logically divided into three types: the address bus (carries memory addresses, unidirectional from CPU), the data bus (carries actual data, bidirectional), and the control bus (carries command and timing signals).

系统总线是一组并行导线，在 CPU、内存和 I/O 设备之间传递信息。逻辑上分为三类：地址总线（传输内存地址，由 CPU 发出，单向）、数据总线（传输实际数据，双向）、控制总线（传输命令和时序信号）。

The width of the address bus determines the maximum addressable memory (e.g., 32 lines can address 2³² unique locations). The width of the data bus affects how many bits can be transferred in one cycle. A wider data bus generally improves performance but increases hardware cost.

地址总线的宽度决定了最大可寻址内存（例如 32 条线可寻址 2³² 个单元）。数据总线的宽度影响一个周期内可传输的位数。更宽的数据总线通常会提升性能，但会增加硬件成本。

5. Memory Hierarchy: From Registers to Secondary Storage | 存储层次：从寄存器到辅助存储器

Computer memory is organised as a hierarchy to balance speed, cost, and capacity. At the top are CPU registers – the fastest but smallest. Next comes cache memory (L1, L2, often L3), followed by main memory (RAM), and finally secondary storage (hard disk, SSD). Each level is larger and slower than the one above it.

计算机内存按层次结构组织，以平衡速度、成本和容量。顶层是 CPU 寄存器——最快但容量最小。接下来是高速缓存（L1、L2，常有 L3），然后是主存 (RAM)，最后是辅助存储器（硬盘、固态硬盘）。每一层都比上一层容量更大但速度更慢。

The principle of locality underpins the effectiveness of this hierarchy. Programs tend to access the same data and instructions repeatedly (temporal locality) and adjacent memory locations (spatial locality). Caching exploits this by keeping frequently or soon-to-be-used data close to the processor.

局部性原理是这一层次结构有效的理论基础。程序倾向于重复访问相同的数据和指令（时间局部性）以及相邻的内存位置（空间局部性）。缓存利用这一点，将频繁或即将使用的数据存放在靠近处理器的地方。

6. Cache Memory – Speed Bridge | 高速缓存——速度桥梁

Cache is a small, high-speed memory placed between the CPU and main memory. It stores copies of frequently accessed data and instructions. When the CPU needs data, it first checks the cache (a ‘hit’). If the data is not found (a ‘miss’), a block is fetched from slower main memory, often together with nearby data to exploit spatial locality.

高速缓存是置于 CPU 与主存之间的小容量高速存储器。它保存频繁访问的数据和指令的副本。当 CPU 需要数据时，首先检查缓存（“命中”）。如果未找到（“缺失”），则从较慢的主存中取出一整个块，通常还会将相邻数据一并取入，以利用空间局部性。

Cache mapping determines how memory blocks are placed into cache lines. Common schemes include direct mapping (each block goes to a single line), fully associative (a block can go anywhere), and set-associative (a compromise using a small set of lines). The hit rate and access time directly affect the average memory access time.

缓存映射方式决定了内存块如何放入缓存行。常见方案包括直接映射（每个块仅能放入一行）、全相联映射（块可放入任意行）和组相联映射（折中方案，使用一个小集合）。命中率和访问时间直接决定平均内存访问时间。

7. Primary Memory: RAM and ROM | 主存储器：RAM 与 ROM

Random Access Memory (RAM) is volatile memory used to store the currently running operating system, application programs, and data. It is directly accessible by the CPU. Two main types are SRAM (static RAM, faster, used for cache) and DRAM (dynamic RAM, slower, used for main memory, needs refreshing). Data is lost when power is turned off.

随机存取存储器 (RAM) 是易失性存储器，用于存放正在运行的操作系统、应用程序和数据，CPU 可直接访问。主要分为 SRAM（静态 RAM，更快，用于缓存）和 DRAM（动态 RAM，较慢，用于主存，需要刷新）。断电后数据丢失。

Read Only Memory (ROM) is non-volatile and retains its contents when the computer is off. It typically stores the BIOS or firmware needed to boot the computer. Variants like PROM, EPROM, and EEPROM allow varying degrees of re-programming.

只读存储器 (ROM) 是非易失性的，关机后仍保留内容。通常存储启动计算机所需的 BIOS 或固件。PROM、EPROM 和 EEPROM 等变体允许不同程度的重新编程。

8. Secondary Storage – Hard Disks, SSDs, and Optical Media | 辅助存储器——硬盘、固态盘与光介质

Secondary storage provides permanent, large-capacity storage. Hard disk drives (HDDs) use spinning magnetic platters and read/write heads; access time depends on seek time and rotational latency. Solid-state drives (SSDs) use NAND flash memory with no moving parts, offering much faster access, lower power consumption, and greater shock resistance, albeit at higher cost per gigabyte.

辅助存储器提供永久性的大容量存储。硬盘驱动器 (HDD) 使用旋转的磁性盘片和读写头；访问时间取决于寻道时间和旋转延迟。固态硬盘 (SSD) 采用 NAND 闪存，无活动部件，访问速度更快、功耗更低、抗震性更强，但每 GB 成本更高。

Optical media like CDs, DVDs, and Blu-ray discs store data using pits and lands read by a laser. They are durable but slow and are now largely replaced by flash storage and cloud services. The choice of secondary storage impacts boot times, file transfer speed, and overall system responsiveness.

CD、DVD 和蓝光光盘等光介质通过激光读取凹坑与平面来存储数据。它们耐久但速度慢，如今已被闪存和云服务大量取代。辅助存储的选择会影响启动时间、文件传输速度和系统总体响应能力。

9. Instruction Set Architecture (ISA) | 指令集体系结构 (ISA)

An ISA defines the set of instructions a processor understands, including the opcodes, addressing modes, register set, and data types. It forms the boundary between hardware and software. Two dominant design philosophies are RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer).

ISA 定义了处理器能够理解的指令集，包括操作码、寻址方式、寄存器组和数据类型。它是硬件与软件之间的接口。两种主流设计哲学是 RISC（精简指令集计算机）和 CISC（复杂指令集计算机）。

RISC processors use a small, fixed-length set of simple instructions that execute in a single clock cycle, relying on software to combine them for complex tasks. CISC processors support a large, variable-length set of instructions, some of which can perform multi-step operations in hardware. RISC is common in mobile devices (ARM); CISC is typical in desktops (x86).

RISC 处理器使用少量、定长的简单指令，每条指令尽量在一个时钟周期内完成，复杂任务由软件组合指令实现。CISC 处理器支持大量、变长的指令，其中一些可在硬件中完成多步操作。RISC 常用于移动设备 (ARM)；CISC 多见于桌面计算机 (x86)。

10. Processor Performance Factors | 处理器性能影响因素

Performance is not solely about clock speed. Key metrics include instruction throughput, cycles per instruction (CPI), and execution time. The performance equation is often expressed as:

Execution Time = (Instruction Count × CPI) / Clock Rate

性能并不仅仅取决于时钟频率。关键指标包括指令吞吐量、每指令周期数 (CPI) 以及执行时间。性能方程通常表示为：

执行时间 = (指令总数 × CPI) / 时钟频率

Thus, improving performance can involve reducing the number of instructions (better compiler, more powerful ISA), lowering CPI (efficient pipeline, superscalar design), or increasing clock rate (limited by heat and power). Multi-core processors achieve parallelism by integrating multiple processing units on a single chip, sharing caches and memory controllers.

因此，提升性能可以通过减少指令数（更好的编译器、更强的 ISA）、降低 CPI（高效流水线、超标量设计）或提高时钟频率（受制于发热和功耗）来实现。多核处理器通过在一块芯片上集成多个处理单元来实现并行，它们共享缓存和内存控制器。

Other factors include memory latency and bandwidth, I/O throughput, and the efficiency of the operating system’s scheduler. In modern systems, the memory wall – the widening gap between CPU speed and memory speed – is often the real bottleneck.

其他因素包括内存延迟与带宽、I/O 吞吐量以及操作系统调度器的效率。在现代系统中，内存墙——即 CPU 速度与内存速度之间不断扩大的差距——往往是真正的瓶颈。

11. Input/Output Techniques | 输入/输出技术

I/O devices communicate with the CPU through three main methods. Programmed I/O uses the CPU to poll device status registers repeatedly, wasting cycles. Interrupt-driven I/O allows a device to signal the CPU when it needs attention, improving efficiency by freeing the CPU for other tasks.

I/O 设备通过三种主要方式与 CPU 通信。程序控制 I/O 让 CPU 反复轮询设备状态寄存器，浪费周期。中断驱动 I/O 则让设备在需要处理时向 CPU 发出信号，将 CPU 解放出来处理其他任务，从而提升效率。

Direct Memory Access (DMA) is the most advanced method: a dedicated DMA controller transfers data blocks between peripheral and memory without involving the CPU for every byte. The CPU sets up the transfer parameters and then continues executing other instructions, receiving an interrupt only when the block transfer completes. DMA is essential for high-speed devices like disk drives and network cards.

直接存储器访问 (DMA) 是最先进的方法：专用 DMA 控制器在外设与内存之间传输数据块，CPU 不必逐字节参与。CPU 设定传输参数后继续执行其他指令，仅在整块传输完成后接收中断。DMA 对于磁盘驱动器和网卡等高速设备至关重要。

12. The Operating System’s Role in Architecture | 操作系统在体系结构中的角色

Although often considered software, the operating system (OS) is deeply tied to computer architecture. The OS manages hardware resources through drivers and interrupts, provides memory management (virtual memory, paging), and schedules processes to maximise CPU utilisation. It communicates with the CPU’s privileged instructions to enforce security and isolation between user programs.

虽然操作系统通常被视为软件，但它与计算机体系结构紧密相连。OS 通过驱动程序和中断管理硬件资源，提供内存管理（虚拟内存、分页），并调度进程以最大化 CPU 利用率。它利用 CPU 的特权指令在用户程序之间实施安全隔离。

The OS relies on the memory management unit (MMU) in modern CPUs to translate virtual addresses to physical addresses. This allows each process to have its own address space, preventing one program from corrupting another’s memory. Architecture support for dual-mode operation (user mode vs. kernel mode) is essential for system stability.

OS 依赖现代 CPU 中的内存管理单元 (MMU) 将虚拟地址转换为物理地址。这使得每个进程拥有自己的地址空间，防止程序间相互破坏内存。体系结构对双模式操作（用户态 vs. 内核态）的支持是系统稳定性的基础。

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Computer Architecture – Core Concepts for IB & CCEA | 计算机体系结构 – IB 与 CCEA 核心考点精讲