Computer Architecture Revision | 计算机体系结构考点精讲

📚 Computer Architecture Revision | 计算机体系结构考点精讲

Understanding computer architecture is fundamental to GCSE Computer Science. It explains how a computer’s hardware components are organised and how they work together to execute instructions. This revision guide covers all the key concepts required for the WJEC specification, from the Von Neumann model to the fetch-decode-execute cycle, and from memory hierarchy to embedded systems. Think of it as your concise, bilingual cheat sheet for exam success.

理解计算机体系结构是GCSE计算机科学的基础。它解释了计算机硬件组件是如何组织的，以及它们如何协同工作来执行指令。这份考点精讲涵盖了WJEC考纲要求的所有关键概念，从冯·诺依曼模型到取指-译码-执行周期，从存储层次结构到嵌入式系统。把它看作是你考试成功的双语简明宝典。

1. Overview of Computer Architecture | 计算机体系结构概述

Computer architecture refers to the logical design and functional behaviour of a computer system. It defines how the central processing unit (CPU) interacts with memory and input/output devices. In GCSE terms, we focus on the internal components of the processor, the flow of data, and the principles that govern how instructions are carried out.

计算机体系结构指的是计算机系统的逻辑设计和功能行为。它定义了中央处理器（CPU）如何与存储器和输入/输出设备交互。在GCSE层面，我们重点关注处理器内部组件、数据流动以及指令执行所遵循的原理。

The architecture we study is primarily the Von Neumann architecture, named after John von Neumann, which uses a single shared memory space for both instructions and data. This is the foundation of almost all modern computers.

我们学习的主要是冯·诺依曼体系结构，以约翰·冯·诺依曼的名字命名，它使用单一的共享存储器空间来存放指令和数据。这是几乎所有现代计算机的基础。

2. The Von Neumann Architecture | 冯·诺依曼体系结构

The Von Neumann architecture is built around the stored program concept. Both program instructions and data are stored in the same main memory (RAM). The CPU processes these instructions sequentially, each cycle involves fetching an instruction from memory, decoding it, and then executing it.

冯·诺依曼体系结构建立在存储程序概念之上。程序指令和数据都存储在同一主存储器（RAM）中。CPU顺序处理这些指令，每个周期都包含从存储器取出一条指令、译码、然后执行它。

Key features include:

Separate CPU and memory units connected by buses.
A single control unit to manage execution.
Registers inside the CPU for temporary data and addresses.

关键特征包括：

CPU和存储器通过总线相连，但二者分离。
单一控制单元负责管理执行过程。
CPU内部设有寄存器，用于暂存数据和地址。

This architecture leads to the ‘Von Neumann bottleneck’ because the same bus is used for both instructions and data, limiting the speed at which data can be moved.

这种架构会导致“冯·诺依曼瓶颈”，因为同一条总线既要传输指令又要传输数据，限制了数据移动的速度。

3. CPU Components and Their Roles | CPU组件及其作用

The CPU, often called the ‘brain’ of the computer, contains several essential components. Each plays a specific role in processing instructions.

CPU常被称为计算机的“大脑”，它包含几个关键组件。每个组件在处理指令时都扮演特定角色。

Control Unit (CU): The CU directs operations within the CPU. It decodes instructions and sends control signals to coordinate the other parts of the processor, such as the ALU and memory.

控制单元（CU）：控制单元指导CPU内部的操作。它对指令进行译码，并发出控制信号以协调处理器的其他部分，如ALU和存储器。

Arithmetic Logic Unit (ALU): The ALU performs arithmetic operations (addition, subtraction, etc.) and logical operations (AND, OR, NOT, comparisons). It is where the actual computation happens.

算术逻辑单元（ALU）：ALU执行算术运算（加法、减法等）和逻辑运算（与、或、非、比较）。这是实际发生计算的地方。

Registers: These are extremely fast, small storage locations inside the CPU. The main registers are:

Program Counter (PC) – holds the address of the next instruction.
Memory Address Register (MAR) – holds the address of the memory location to be read from or written to.
Memory Data Register (MDR) – holds the data being transferred between the CPU and memory (or its destination).
Accumulator (ACC) – holds the results of ALU operations.

寄存器：这些是CPU内部极其快速的小容量存储位置。主要的寄存器有：

程序计数器（PC）——存放将要执行的下一条指令的地址。
存储器地址寄存器（MAR）——存放将要读取或写入的存储器单元的地址。
存储器数据寄存器（MDR）——存放CPU与存储器之间传输的数据（或指令）。
累加器（ACC）——存放ALU运算的结果。

4. The Fetch-Decode-Execute Cycle | 取指-译码-执行周期

This is the fundamental process by which a CPU processes instructions. It is a continuous loop that repeats billions of times per second, driven by the system clock.

这是CPU处理指令的基本过程。它是一个持续不断的循环，在系统时钟的驱动下每秒重复数十亿次。

Fetch: The address in the PC is copied to the MAR. The PC is incremented to point to the next instruction. The instruction from the memory address in the MAR is placed onto the data bus and copied into the MDR. Then the instruction is moved from the MDR to the Control Unit.

取指：PC中的地址被复制到MAR。PC递增，指向下一条指令。位于MAR所指地址的指令被放到数据总线上，并复制到MDR中。然后指令从MDR传送到控制单元。

Decode: The Control Unit interprets or ‘decodes’ the instruction. It determines what operation needs to be performed and on what data. It may break the instruction down into opcode (operation) and operand (address/data).

译码：控制单元解释或称“译码”指令。它确定需要执行什么操作以及操作什么数据。它可能会把指令分解为操作码和操作数。

Execute: The Control Unit sends signals to the appropriate components. If a calculation is needed, the ALU is activated. If a memory read/write is required, the MAR and MDR are used to transfer data. The result may be stored in the ACC or a memory location.

执行：控制单元向相应部件发送信号。如果需要计算，ALU会被激活。如果需要存储器读写，则MAR和MDR用于传输数据。结果可能存储到ACC或某个存储单元中。

The cycle then repeats, starting again from the new PC value.

然后循环重复，从新的PC值重新开始。

5. Factors Affecting CPU Performance | 影响CPU性能的因素

Several factors influence how fast a processor can execute instructions. For the exam, you need to be able to explain the effect of clock speed, number of cores, and cache memory.

有几个因素会影响处理器执行指令的速度。在考试中，你需要能够解释时钟速度、核心数量和高速缓存的影响。

Factor (因素)	Explanation (解释)	Impact on Performance (对性能的影响)
Clock Speed (时钟速度)	Measured in GHz (gigahertz), it is the number of cycles the CPU can perform per second. Each cycle can process an instruction (or part of one).	Higher clock speed means more fetch-decode-execute cycles per second, so the CPU processes instructions faster.
Number of Cores (核心数量)	A core is a complete processing unit capable of executing its own instructions. A multi-core CPU contains two or more cores on a single chip.	More cores can execute multiple instructions simultaneously. However, software must be written to take advantage of parallel processing.
Cache Memory (高速缓存)	A small amount of very fast memory located inside or very close to the CPU. It stores frequently used instructions and data.	Larger cache reduces the time the CPU spends waiting for data from slower RAM, speeding up overall execution.

6. Primary Memory: RAM and ROM | 主存储器：RAM和ROM

Primary memory is directly accessible by the CPU. It consists of two main types: RAM and ROM. They differ in volatility, speed, and purpose.

主存储器是CPU可以直接访问的存储器。它主要包含两种类型：RAM和ROM。它们在易失性、速度和用途上有所不同。

RAM (Random Access Memory):

Volatile – loses its content when power is turned off.
Used to store the operating system, running programs, and data currently in use.
Read and write capabilities.
Larger RAM capacity allows more applications to run simultaneously without slowing down.

RAM（随机存取存储器）：

易失性——断电后内容丢失。
用于存储操作系统、正在运行的程序以及当前使用的数据。
具备读写能力。
更大的RAM容量允许同时运行更多应用程序而不降低速度。

ROM (Read Only Memory):

Non-volatile – retains its content even without power.
Stores the BIOS (Basic Input/Output System) or firmware, which contains the boot-up instructions for the computer.
Normally read-only; writing to ROM requires special procedures.

ROM（只读存储器）：

非易失性——没有电源也能保留内容。
存储BIOS（基本输入/输出系统）或固件，其中包含计算机的启动指令。
通常是只读的；向ROM写入需要特殊程序。

7. Cache Memory | 高速缓存

Cache is a small but extremely fast type of memory that sits between the CPU and main memory (RAM). Its purpose is to reduce the average time to access data from the main memory. It is more expensive per byte than RAM, so sizes are limited.

高速缓存是一种容量小但速度极快的存储器，位于CPU和主存储器（RAM）之间。其目的是减少从主存储器访问数据的平均时间。它的每字节成本比RAM高，因此容量有限。

When the CPU needs data, it first checks the cache. If found (a cache hit), it is accessed quickly. If not found (a cache miss), the data is fetched from the slower RAM. Modern CPUs use multiple levels of cache (L1, L2, L3) with L1 being the smallest and fastest, often split into instruction and data caches.

当CPU需要数据时，它首先检查高速缓存。如果找到（缓存命中），则可以快速访问。如果没有找到（缓存未命中），则从较慢的RAM中获取数据。现代CPU使用多级缓存（L1、L2、L3），其中L1最小最快，通常分为指令缓存和数据缓存。

Increasing cache size can improve performance, but there are diminishing returns and physical size/cost constraints.

增大缓存容量可以提升性能，但存在边际效益递减以及物理尺寸和成本的限制。

8. Secondary Storage and Its Types | 辅助存储器及其类型

Secondary storage is non-volatile memory used for long-term data retention. Unlike RAM, it retains data without power. It is not directly accessed by the CPU; data must first be loaded into RAM.

辅助存储器是非易失性存储器，用于长期保存数据。与RAM不同，它无需电源即可保留数据。CPU并不直接访问它；数据必须先加载到RAM中。

Three main technologies are examined at GCSE:

Magnetic storage (e.g., hard disk drives, HDD) – uses magnetic platters and a read/write head. High capacity but slower with moving parts; susceptible to shock.
Optical storage (e.g., CD, DVD, Blu-ray) – uses lasers to read/write data on reflective surfaces. Low cost per disc but limited capacity and slow.
Solid-state storage (e.g., SSD, USB flash drives) – uses flash memory with no moving parts, fast data access, low power consumption, but higher cost per gigabyte compared to HDDs.

GCSE考试涉及三种主要技术：

磁存储（例如：硬盘驱动器HDD）——使用磁性盘片和读写头。容量大，但因有移动部件速度较慢；易受冲击影响。
光存储（例如：CD、DVD、蓝光）——使用激光在反射表面上读写数据。每张光盘成本低，但容量有限且速度慢。
固态存储（例如：SSD、USB闪存驱动器）——使用闪存，无移动部件，数据访问快，功耗低，但每GB成本比HDD高。

Choosing appropriate secondary storage depends on capacity, speed, portability, durability, and cost.

选择适当的辅助存储器取决于容量、速度、便携性、耐用性和成本。

9. Embedded Systems | 嵌入式系统

An embedded system is a computer system with a dedicated function within a larger mechanical or electronic system. It is typically built into the device it controls and is not intended to be reprogrammed by the end user. Examples include washing machine controllers, microwave ovens, engine management systems in cars, and traffic lights.

嵌入式系统是一种在较大型机械或电子系统中具有特定功能的计算机系统。它通常内置于它所控制的设备中，并不打算由最终用户重新编程。例子包括洗衣机控制器、微波炉、汽车引擎管理系统和交通信号灯。

Characteristics of embedded systems:

Specific, dedicated task.
Often real-time operation, meaning they must respond to inputs within a strict time frame.
Limited resources (low power, small memory).
Cost-effective and reliable.
Often firmware-based; the program is stored in ROM or flash memory.

嵌入式系统的特征：

特定的、专用的任务。
通常是实时操作，意味着它们必须在严格的时间范围内对输入做出响应。
资源有限（低功耗，内存小）。
成本效益高且可靠。
通常基于固件；程序存储在ROM或闪存中。

Unlike general-purpose computers, embedded systems do not have unnecessary components like a keyboard or monitor; they focus on input from sensors and output to actuators.

与通用计算机不同，嵌入式系统没有键盘或显示器等不必要的组件；它们专注于来自传感器的输入和去往执行器的输出。

10. Buses: Data, Address, and Control | 总线：数据总线、地址总线和控制总线

Buses are sets of parallel wires that carry data, addresses, and control signals between the CPU, memory, and I/O devices. A typical Von Neumann system uses three separate buses.

总线是一组并行导线，用于在CPU、存储器和I/O设备之间传输数据、地址和控制信号。典型的冯·诺依曼系统使用三条独立的总线。

Data Bus: Bi-directional. It carries the actual data or instructions between the CPU and memory/I/O. The width (number of bits) determines how much data can be transferred at once, e.g., 32-bit data bus can move 32 bits in one operation.

数据总线：双向。它在CPU和存储器/I/O之间传输实际数据或指令。其宽度（位数）决定了每次可以传输多少数据，例如32位数据总线一次可移动32位。

Address Bus: Unidirectional (from CPU to memory). It carries the address of the memory location that the CPU wants to read from or write to. The width of the address bus determines the maximum addressable memory space. A 24-bit address bus can address 2²⁴ (16,777,216) memory locations.

地址总线：单向（从CPU到存储器）。它传输CPU想要读取或写入的存储器单元的地址。地址总线的宽度决定了最大可寻址的内存空间。24位地址总线可以寻址2²⁴（16,777,216）个存储单元。

Control Bus: A collection of individual lines (each carrying a specific signal) that coordinates activities. Examples include read/write signals, clock signal, interrupt requests, and bus grants.

控制总线：是一组单独的信号线（每条线传输特定信号），用于协调各种活动。例如：读/写信号、时钟信号、中断请求和总线授权。

The three buses work together to perform the fetch-decode-execute cycle, with the control bus managing the timing and direction.

三条总线协同工作以执行取指-译码-执行周期，控制总线负责管理时序和方向。

11. Exam Tips and Common Misunderstandings | 考试技巧与常见误解

Here are some quick pointers to help you pick up marks and avoid losing them unnecessarily in your WJEC Computer Science exam.

这里有一些快速提示，可以帮助你在WJEC计算机科学考试中得分并避免不必要的失分。

Use precise terminology: Say ‘Program Counter holds the address of the next instruction’, not ‘PC points to the next thing’. Examiners look for correct technical terms.
Differentiate between RAM and ROM clearly: Don’t confuse volatility; RAM loses data, ROM keeps it. RAM is for temporary data, ROM for permanent startup instructions.
Explain performance factors in context: For example, ‘Higher clock speed means more cycles per second, so instructions are processed faster’ – always link the factor to the outcome.
Avoid fuzzy definitions of cache: Cache is NOT RAM; it’s a separate very fast memory. Saying ‘cache is memory that speeds up the computer’ is insufficient.
Embedded systems: Remember that an embedded system is a computer system built for a specific purpose. Do not describe a desktop PC or laptop as an embedded system.
Draw the fetch-execute cycle diagram if asked: Be able to label PC, MAR, MDR, and buses, and describe the flow of data.

使用准确的术语：要说“程序计数器存放下一条指令的地址”，而不是“PC指向下一个东西”。考官看重正确的技术术语。
清楚区分RAM和ROM：不要混淆易失性；RAM会丢失数据，ROM保留数据。RAM用于临时数据，ROM用于永久启动指令。
在具体情境中解释性能因素：例如“更高的时钟速度意味着每秒更多周期，因此指令处理更快”——始终将因素与结果关联起来。
避免对高速缓存的模糊定义：高速缓存不是RAM；它是一种独立的非常快的存储器。说“缓存是加速计算机的内存”是不够的。
嵌入式系统：记住嵌入式系统是为特定目的而构建的计算机系统。不要将台式电脑或笔记本电脑描述为嵌入式系统。
如果被要求，画出取指-执行周期图：要能够标注PC、MAR、MDR和总线，并描述数据流动。

A strong answer shows understanding of how components work together, not just isolated facts. Practice linking concepts: how clock speed, cache, and buses interact during the fetch-execute cycle.

一个出色的答案展示了对各组件如何协同工作的理解，而不仅仅是孤立的事实。练习将概念联系起来：时钟速度、高速缓存和总线在取指-执行周期中是如何相互作用的。

Published by TutorHao | Computer Science Revision Series | aleveler.com

更多咨询请联系16621398022（同微信）

Computer Architecture Revision | 计算机体系结构考点精讲