📚 CPU Architecture and Performance: Key Exam Focus for IB & WJEC | IB/WJEC 计算机 CPU 考点精讲
The Central Processing Unit (CPU) is often called the ‘brain’ of the computer. Understanding its internal components, how they interact during the instruction cycle, and what factors influence its speed is fundamental for both IB Computer Science and WJEC specifications. This article breaks down every key concept, from registers to pipelining, with clear bilingual explanations to help you master exam questions.
中央处理器（CPU）常被称为计算机的“大脑”。理解其内部组件、它们在指令周期中如何交互以及哪些因素影响其速度，是IB计算机科学和WJEC考试的基础。本文从寄存器到流水线，逐项拆解每个关键概念，配以清晰的中英双语解释，助你攻克考题。
1. The Central Processing Unit: An Overview | 中央处理器概述
The CPU processes instructions and data. It consists of the Control Unit (CU), Arithmetic Logic Unit (ALU), and a set of high-speed storage locations called registers. All these components work together to fetch, decode, and execute instructions stored in main memory.
CPU负责处理指令和数据。它由控制单元（CU）、算术逻辑单元（ALU）和一组称为寄存器的高速存储位置组成。所有这些组件协同工作，完成对主存中指令的取指、译码和执行。
Modern CPUs also incorporate cache memory on the same chip to reduce the time needed to access frequently used data and instructions. The architecture determines how the processor communicates with memory, input/output devices, and storage.
现代CPU还在同一芯片上集成了高速缓存，以减少访问常用数据和指令所需的时间。CPU架构决定了处理器如何与内存、输入/输出设备以及存储器通信。
2. The Von Neumann Architecture | 冯·诺依曼架构
Most general-purpose computers follow the Von Neumann architecture, where both instructions and data share the same memory space and bus system. This means the CPU fetches an instruction from memory, then may read or write data over the same pathways.
大多数通用计算机遵循冯·诺依曼架构，其中指令和数据共享相同的存储空间和总线系统。这意味着CPU从内存中取出一条指令，然后可能通过同一通道读取或写入数据。
A key characteristic is the sequential execution of instructions, one after another, unless a branch instruction alters the flow. The stored-program concept allows programs to be easily changed by loading different instructions into memory.
一个关键特征是顺序执行指令，一条接一条，除非分支指令改变流程。存储程序概念允许通过将不同指令加载到内存中来轻松更换程序。
The bottleneck known as the ‘Von Neumann bottleneck’ arises from the shared bus, limiting the speed at which data and instructions can be transferred simultaneously.
所谓的“冯·诺依曼瓶颈”源于共享总线，限制了数据和指令同时传输的速度。
3. Key Registers in the CPU | CPU中的关键寄存器
Registers are extremely fast memory locations inside the CPU. The most important ones for the instruction cycle are:
寄存器是CPU内部极为快速的存储位置。对指令周期最重要的寄存器有：
- Program Counter (PC) – holds the memory address of the next instruction to be fetched.
- 程序计数器 (PC) – 存放下一条要取出的指令的内存地址。
- Memory Address Register (MAR) – contains the address of the memory location to be read from or written to.
- 内存地址寄存器 (MAR) – 存放要读取或写入的内存位置的地址。
- Memory Data Register (MDR) – temporarily holds the data that has been read from or is to be written to memory.
- 内存数据寄存器 (MDR) – 临时存放从内存读取的或将要写入内存的数据。
- Current Instruction Register (CIR) – stores the instruction currently being decoded and executed.
- 当前指令寄存器 (CIR) – 存储当前正在译码和执行的指令。
- Accumulator (ACC) – holds the results of calculations performed by the ALU.
- 累加器 (ACC) – 存放ALU执行计算的结果。
Understanding what each register does at every stage of the fetch-decode-execute cycle is essential for exams.
理解每个寄存器在取指-译码-执行周期的每个阶段的作用对考试至关重要。
4. The Control Unit and Arithmetic Logic Unit | 控制单元与算术逻辑单元
The Control Unit (CU) directs the operation of the processor. It decodes instructions and generates control signals that orchestrate data movement between registers, the ALU, and memory. It ensures the correct sequence of steps is carried out.
控制单元（CU）指挥处理器的操作。它译码指令并产生控制信号，协调寄存器、ALU和内存之间的数据移动。它确保执行正确的步骤序列。
The Arithmetic Logic Unit (ALU) performs all arithmetic operations (addition, subtraction, multiplication, division) and logical operations (AND, OR, NOT, XOR). It takes inputs from registers, performs the operation, and stores the result, typically in the Accumulator.
算术逻辑单元（ALU）执行所有算术运算（加、减、乘、除）和逻辑运算（与、或、非、异或）。它从寄存器获取输入，执行运算，并将结果通常存储到累加器中。
5. The System Clock and Clock Speed | 系统时钟与时钟速度
The system clock generates a continuous stream of electronic pulses at a constant frequency. Each pulse triggers a step in the CPU’s operation, synchronising all components. The clock speed is measured in Hertz (Hz), typically gigahertz (GHz) for modern processors (1 GHz = 10⁹ cycles per second).
系统时钟以恒定频率产生连续的电脉冲流。每个脉冲触发CPU操作的一个步骤，同步所有组件。时钟速度以赫兹（Hz）为单位，现代处理器通常以吉赫（GHz）计量（1 GHz = 每秒10⁹个周期）。
A higher clock speed generally means more instructions can be executed per second, but it also generates more heat and consumes more power. The clock period, which is the time for one cycle, is the reciprocal of the frequency: for a 3 GHz CPU, the period is about 0.33 nanoseconds.
较高的时钟速度通常意味着每秒可执行更多指令，但也会产生更多热量并消耗更多功率。时钟周期，即一个周期的时间，是频率的倒数：对于3 GHz的CPU，周期约为0.33纳秒。
6. The Fetch-Decode-Execute Cycle | 取指-译码-执行周期
This is the fundamental cycle by which a CPU processes each instruction. It repeats indefinitely while the computer is running.
这是CPU处理每条指令的基本周期，在计算机运行时不断重复执行。
Fetch step: The address from the PC is copied to the MAR; the PC is incremented. A read signal is sent to main memory, and the instruction at that address is loaded into the MDR, then copied to the CIR.
取指步骤：PC中的地址被复制到MAR；PC递增。向主存发送读信号，该地址处的指令被加载到MDR，然后复制到CIR。
Decode step: The CIR’s contents are decoded by the CU to determine what operation to perform and which operands are needed.
译码步骤：CIR中的内容由CU译码，以确定要执行什么操作以及需要哪些操作数。
Execute step: The CU sends signals to the relevant components. If an ALU operation is needed, data is sent to the ALU and the result stored in ACC. If a memory access is required, the address is placed in MAR and data transferred via MDR.
执行步骤：CU向相关组件发送信号。如果需要ALU操作，数据被送入ALU，结果存入ACC。如果需要访问内存，地址放入MAR，数据通过MDR传输。
Exam questions often ask you to describe the role of registers during this cycle or trace the changes for a given set of instructions.
考题常要求你描述在此周期中寄存器的作用，或针对给定指令集追踪变化。
7. Cache Memory: Purpose and Levels | 高速缓存：作用与层级
Cache is a small amount of very fast memory located on or close to the CPU. It stores frequently accessed instructions and data to reduce the average time to access memory. When the CPU needs data, it first checks the cache; if found (a ‘cache hit’), it avoids slower main memory access.
高速缓存是位于CPU内部或附近的一小部分非常快速的内存。它存储频繁访问的指令和数据，以减少平均内存访问时间。当CPU需要数据时，首先检查缓存；若找到（称为“缓存命中”），则避免了较慢的主存访问。
Cache is organised in levels: Level 1 (L1) is the fastest and smallest, often split into instruction cache and data cache. Level 2 (L2) is larger but slightly slower, and Level 3 (L3) is shared among cores, larger still. Effective caching significantly improves CPU performance.
缓存按层级组织：一级缓存（L1）最快且最小，通常分为指令缓存和数据缓存。二级缓存（L2）更大但稍慢，三级缓存（L3）在核心间共享，容量更大。有效的缓存显著提升CPU性能。
8. Factors Affecting CPU Performance | 影响CPU性能的因素
Three primary factors influence how fast a CPU can execute programs:
三个主要因素影响CPU执行程序的速度：
- Clock Speed: A higher frequency means more cycles per second, so more instructions can potentially be executed.
- 时钟速度：更高的频率意味着每秒更多周期，因此可能执行更多指令。
- Number of Cores: Multiple cores allow true parallelism; each core can run its own fetch-decode-execute cycle independently, so multiple instructions are processed simultaneously.
- 核心数量：多核允许真正的并行处理；每个核可独立运行自己的取指-译码-执行周期，因此同时处理多条指令。
- Cache Size and Type: Larger, more efficient cache reduces the number of times the CPU must wait for main memory, improving throughput.
- 缓存大小与类型：更大、更高效的缓存减少CPU等待主存的次数，提高吞吐量。
Other factors include the instruction set architecture, pipelining depth, and thermal management.
其他因素包括指令集架构、流水线深度和热管理。
9. Pipelining: How It Boosts Throughput | 流水线技术如何提升吞吐量
Pipelining is a technique that overlaps the execution of multiple instructions. While one instruction is being executed, the next is being decoded, and the one after that is being fetched. This reduces the idle time of CPU components and increases the number of instructions completed per unit time (throughput).
流水线是一种重叠执行多条指令的技术。当一条指令正在执行时，下一条正在译码，再下一条正在取指。这减少了CPU组件的空闲时间，提高了单位时间内完成的指令数（吞吐量）。
However, hazards such as data dependencies, control hazards (branches), and structural hazards can stall the pipeline and require special handling, such as forwarding or branch prediction.
然而，数据依赖、控制冒险（分支）和结构冒险等风险可能使流水线停顿，需要特殊处理，例如数据前推或分支预测。
10. CISC and RISC Architectures | CISC与RISC架构
CISC (Complex Instruction Set Computer) processors use a large set of complex instructions, where a single instruction may perform multiple low-level operations. They often use fewer lines of assembly code but require complex decoding logic. Example: x86.
CISC（复杂指令集计算机）处理器使用大量复杂指令，单条指令可能执行多个低级操作。它们通常使用较少的汇编代码行，但需要复杂的译码逻辑。例如：x86。
RISC (Reduced Instruction Set Computer) processors employ a small, highly optimised set of simple instructions. Each instruction executes in roughly one clock cycle, enabling efficient pipelining. The compiler has a greater burden to optimise code. Example: ARM.
RISC（精简指令集计算机）处理器使用一小套经过高度优化的简单指令。每条指令大致在一个时钟周期内执行，使流水线高效。编译器承担更大的优化代码的负担。例如：ARM。
Exam questions may ask you to compare them in terms of power consumption, use in embedded systems, and performance efficiency.
考题可能会要求你从功耗、嵌入式系统应用和性能效率方面比较二者。
11. Multicore and Parallel Processing | 多核与并行处理
A multicore processor contains two or more independent processing units (cores) on a single chip. Each core can execute its own thread, enabling true parallel execution of multiple programs or threads of the same program.
多核处理器在单个芯片上包含两个或更多独立的处理单元（核）。每个核可以执行自己的线程，从而实现多个程序或同一程序多个线程的真正并行执行。
To take full advantage of multiple cores, software must be written to split workloads into concurrent tasks. Not all programs can be effectively parallelised, and there is overhead in coordinating tasks.
要充分利用多核，软件必须编写为将工作负载拆分成并发任务。并非所有程序都能有效并行化，而且协调任务存在开销。
The operating system schedules tasks across cores, improving multitasking and responsiveness. Modern CPUs also support simultaneous multithreading (SMT), where each core can handle multiple threads by duplicating certain registers.
操作系统将任务调度到各核，改善多任务处理和响应速度。现代CPU还支持同步多线程（SMT），每个核可通过复制某些寄存器处理多个线程。
12. Exam Tips and Common Mistakes | 应试技巧与常见错误
When answering CPU questions, always refer to specific register names precisely. Avoid confusing the MAR (holds address) with MDR (holds data). Clearly label the direction of data flow when drawing diagrams of the FDE cycle.
回答CPU问题时，始终准确使用特定寄存器名称。避免混淆MAR（存地址）与MDR（存数据）。绘制FDE周期图时，清晰标出数据流方向。
For performance questions, don’t simply state ‘higher clock speed is better’. Explain that it increases the number of cycles per second, enabling more instructions to be executed, but also mention trade-offs like heat. When discussing multicore, highlight that gains depend on software parallelism.
对于性能问题，不要简单地说“时钟速度越高越好”。要解释它增加了每秒周期数，从而能执行更多指令，但也要提及热量等权衡。讨论多核时，强调性能提升取决于软件的并行性。
Be prepared to compare CISC and RISC in terms of power efficiency and use cases. Use correct units: clock speed in Hz, cache size in bytes, and avoid misusing register acronyms. Practising with past paper questions will reinforce these details.
做好准备从能效和用例方面比较CISC与RISC。使用正确单位：时钟速度用Hz，缓存大小用字节，并避免误用寄存器缩写。通过练习历年真题来巩固这些细节。
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