📚 IGCSE AQA Computer Science: Logic Gates Exam Essentials | IGCSE AQA 计算机：逻辑门 考点精讲
Logic gates form the backbone of digital circuits and are a core topic in IGCSE AQA Computer Science. Understanding how each gate functions, how to interpret truth tables, and how to combine gates into more complex circuits is essential for success in the exam. This article covers key concepts, common pitfalls, and worked examples to help you master logic gates.
逻辑门是数字电路的基础，也是 IGCSE AQA 计算机科学的核心考点。理解每种门的功能、掌握真值表的解读以及将门组合成更复杂电路的能力，是考试成功的关键。本文涵盖关键概念、常见易错点及实例分析，助你彻底攻克逻辑门。
1. Introduction to Logic Gates | 逻辑门简介
Logic gates are electronic devices that perform basic logical functions on one or more binary inputs to produce a single binary output. The inputs and outputs can only take two values: 0 (low, false) and 1 (high, true). In the AQA IGCSE specification, you must be familiar with seven fundamental gates: NOT, AND, OR, NAND, NOR, XOR, and XNOR.
逻辑门是一种电子器件，对于一个或多个二进制输入执行基本的逻辑运算，产生单一的二进制输出。输入和输出只能取两种值：0（低电平，假）和 1（高电平，真）。在 AQA IGCSE 考纲中，你必须熟练掌握七种基本门：非门、与门、或门、与非门、或非门、异或门和同或门。
2. The NOT Gate | 非门
The NOT gate, also called an inverter, has only one input. It outputs the opposite of the input. If the input is 1, the output is 0, and vice versa. The logical expression is written as Q = ¬A or Q = A’. The symbol is a triangle followed by a small circle (bubble).
非门，也称反相器，只有一个输入端。它输出与输入相反的值。若输入为 1，输出为 0，反之亦然。逻辑表达式写作 Q = ¬A 或 Q = A’。其电路符号为一个三角形后跟一个小圆圈（气泡）。
| Input A | Output Q = A’ |
|---|---|
| 0 | 1 |
| 1 | 0 |
In boolean algebra, the NOT operation is often represented by an overbar or a prime symbol. You will frequently use it when simplifying expressions using De Morgan’s laws.
在布尔代数中，非运算常用上划线或撇号表示。在应用德摩根定律化简表达式时，你会频繁用到它。
3. The AND Gate | 与门
The AND gate has two or more inputs. The output is 1 only when all inputs are 1. For a 2-input AND gate, the boolean expression is Q = A · B (or simply AB). The symbol is shaped like a D with a flat left side.
与门有两个或更多输入端。只有当所有输入均为 1 时，输出才为 1。对于两输入与门，布尔表达式为 Q = A · B（或简写为 AB）。电路符号形状像一个左侧扁平的 D。
| A | B | Q = A·B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
The AND gate is useful for data masking and enabling signals. In exam questions, you may need to combine AND with other gates to construct a logic circuit for a given problem.
与门常用于数据掩码和信号使能。在考试题中，你可能需要将 AND 门与其他门组合，为特定问题构建逻辑电路。
4. The OR Gate | 或门
The OR gate also has two or more inputs. Its output is 1 if at least one input is 1. The expression is Q = A + B. The symbol is a shield-like shape curving to a point on the right.
或门同样有两个或更多输入端。只要至少一个输入为 1，输出即为 1。表达式为 Q = A + B。电路符号像一个盾形，右侧收聚成尖角。
| A | B | Q = A + B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
Note that the OR gate represents logical addition. In circuit design, cascading OR gates allows checking multiple conditions simultaneously.
注意，或门代表逻辑加法。在电路设计中，级联或门可以同时检查多个条件。
5. The NAND Gate | 与非门
A NAND gate is simply an AND gate followed by a NOT gate. Its output is the inverse of the AND output. Hence, the output is 0 only when all inputs are 1. The boolean expression is Q = (A · B)’. The symbol is identical to the AND gate but with a bubble at the output.
与非门就是一个与门后跟一个非门。其输出是与门输出的反转。因此，仅当所有输入均为 1 时，输出为 0。布尔表达式为 Q = (A · B)’。电路符号与与门相同，但在输出端有一个气泡。
| A | B | Q = (A·B)’ |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The NAND gate is called a universal gate because any other logic function can be implemented using only NAND gates. The exam may ask you to construct circuits using NAND-only logic.
与非门被称为通用门，因为仅用与非门就可以实现任何其他逻辑功能。考试可能会要求你仅用与非门构建电路。
6. The NOR Gate | 或非门
A NOR gate is an OR gate followed by a NOT. The output is 1 only when all inputs are 0. The expression is Q = (A + B)’. The symbol combines the OR shape with a bubble on the output.
或非门是一个或门后跟非门。仅当所有输入均为 0 时，输出才为 1。表达式为 Q = (A + B)’。电路符号结合了或门的外形和输出端的气泡。
| A | B | Q = (A+B)’ |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
Like NAND, NOR is also a universal gate. Understanding NOR can help you appreciate how all digital circuits can be built from a single gate type.
与 NAND 类似，NOR 也是通用门。理解 NOR 能帮助你理解如何仅用一种门构建所有数字电路。
7. The XOR Gate | 异或门
The Exclusive OR (XOR) gate gives an output of 1 when an odd number of inputs are 1. For two inputs, it outputs 1 if the inputs are different. The expression is Q = A ⊕ B, which is equivalent to (A · B’) + (A’ · B). The symbol is similar to OR but with an extra curved line on the input side.
异或（XOR）门当输入中 1 的个数为奇数时输出 1。对于两输入，若输入不同则输出 1。表达式为 Q = A ⊕ B，等价于 (A · B’) + (A’ · B)。电路符号类似于或门，但在输入端多一条弧线。
| A | B | Q = A⊕B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
XOR is crucial in arithmetic circuits such as half adders and full adders. It also appears in parity generation and error detection.
异或门在半加器和全加器等算术电路中至关重要，也用于奇偶校验生成和错误检测。
8. The XNOR Gate | 同或门
The Exclusive NOR (XNOR) gate is the complement of XOR. It outputs 1 when the inputs are equal. The expression is Q = A ⊙ B, also written as Q = (A ⊕ B)’. The symbol is an XOR gate with a bubble at the output.
同或（XNOR）门是异或门的反相。当输入相等时输出 1。表达式为 Q = A ⊙ B，也可写作 Q = (A ⊕ B)’。电路符号为异或门在输出端加一个气泡。
| A | B | Q = A⊙B |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
XNOR gates are often used in equality comparators. For instance, to check if two binary numbers match, an XNOR on each bit followed by an AND can be employed.
同或门常用于相等比较器。例如，要检查两个二进制数是否匹配，可以对每个位使用同或门，然后用与门汇总。
9. Truth Tables and Logic Expressions | 真值表与逻辑表达式
A truth table lists all possible input combinations and the corresponding output for a logic circuit. Constructing truth tables systematically is a key exam skill. Start with the inputs on the left, state all intermediate points, and finally the output. For n inputs, there are 2ⁿ rows. The order of rows usually follows binary counting from 0 to 2ⁿ-1.
真值表列出了逻辑电路所有可能的输入组合及其对应的输出。系统性地构建真值表是一项关键考试技能。从左侧的输入开始，标出所有中间节点，最后是输出。对于 n 个输入，共有 2ⁿ 行。行的顺序通常按二进制计数从 0 到 2ⁿ-1 排列。
Logic expressions can be derived from truth tables using the sum-of-products method. Take each row where output is 1, AND the inputs (with inversion where the input is 0), then OR all these product terms. For example, the XOR truth table gives Q = A’·B + A·B’.
逻辑表达式可以通过“积之和”方法从真值表推导。选取输出为 1 的每一行，将与输入对应的项（输入为 0 时取反）进行 AND 运算，然后将所有这些乘积项进行 OR 运算。例如，异或的真值表得出 Q = A’·B + A·B’。
10. Combining Gates – Simple Circuits | 组合逻辑门电路
Real-world logic problems require combining multiple gates. For instance, a burglar alarm may sound if the alarm is enabled AND (door is opened OR window is opened). This translates to Q = Enable · (Door + Window). You need to practice drawing and interpreting such circuits.
现实世界中的逻辑问题需要组合多个门。例如，如果报警器使能且（门打开或窗打开），则触发报警。这转化为 Q = Enable · (Door + Window)。你需要练习绘制和解读此类电路。
When evaluating a combined circuit, trace the signal from inputs to output, writing intermediate values. The exam may provide a diagram and ask for its truth table or logic expression. Alternatively, you might be given a scenario and must design the circuit.
当评估组合电路时，从输入到输出追踪信号，记录中间值。考试可能提供电路图，要求写出其真值表或逻辑表达式，也可能给出场景，让你设计电路。
11. De Morgan’s Laws | 德摩根定律
De Morgan’s laws allow you to transform expressions and simplify circuits. The two laws are: (A · B)’ = A’ + B’ and (A + B)’ = A’ · B’. These equivalences are tested frequently. They show that a NAND gate is equivalent to an OR gate with inverted inputs, and a NOR gate equals an AND with inverted inputs.
德摩根定律允许你变换表达式并化简电路。两条定律为：(A · B)’ = A’ + B’ 和 (A + B)’ = A’ · B’。这些等价关系经常被考查。它们表明，与非门等效于输入端取反的或门，而或非门等效于输入端取反的与门。
Use bubble pushing: moving the bubble from output to inputs changes the gate type. This technique is helpful in circuit analysis. Exam questions often ask you to rewrite a logic statement using only NAND or NOR gates by applying De Morgan’s laws.
使用“推气泡”法：将气泡从输出移到输入会改变门类型。此技巧在电路分析中很有用。考试题常要求你应用德摩根定律，仅用与非门或或非门重写逻辑语句。
12. Half Adder and Full Adder | 半加器与全加器
A half adder adds two single binary digits and produces a sum bit (S) and a carry bit (C). The sum is S = A ⊕ B, and the carry is C = A · B. This circuit uses one XOR and one AND gate. Half adders cannot handle a carry input from a previous stage.
半加器将两个单个二进制数字相加，产生和位 (S) 和进位位 (C)。和为 S = A ⊕ B，进位为 C = A · B。该电路使用一个异或门和一个与门。半加器不能处理来自前级的进位输入。
A full adder extends this by including a carry input (Cin). The equations are S = A ⊕ B ⊕ Cin, and Cout = (A · B) + (Cin · (A ⊕ B)). The full adder can be built from two half adders and an OR gate. Understanding this structure is important for multi-bit addition.
全加器扩展了该功能，包含进位输入 (Cin)。等式为 S = A ⊕ B ⊕ Cin，Cout = (A · B) + (Cin · (A ⊕ B))。全加器可以由两个半加器和一个或门构成。理解这一结构对于多比特加法至关重要。
In the exam, you may be required to draw a half-adder circuit, complete a truth table for a full adder, or explain how a full adder can be cascaded to build a 4-bit ripple-carry adder.
在考试中，你可能被要求绘制半加器电路，完成全加器的真值表，或者说明如何级联全加器来构建 4 位行波进位加法器。
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