📚 Kirchhoff’s Laws for IB and CIE Physics: Exam Preparation | 基尔霍夫定律 IB CIE 物理考点精讲
Kirchhoff’s laws are fundamental tools in circuit analysis, underpinning everything from simple series and parallel circuits to complex multi-loop networks. For IB and CIE Physics students, a solid grasp of both the current law and the voltage law is essential for problem-solving and experimental design. This guide breaks down each law, explains sign conventions, and walks through typical exam-style questions to help you secure top marks.
基尔霍夫定律是电路分析的基本工具，支撑着从简单串并联电路到复杂多回路网络的所有内容。对于 IB 和 CIE 物理学生来说，牢固掌握电流定律和电压定律对于解决问题和实验设计至关重要。本指南将拆解每条定律，解释符号规则，并逐步解析典型的考试题型，助你取得高分。
1. Kirchhoff’s Current Law (KCL) | 基尔霍夫电流定律
Kirchhoff’s first law states that the total current entering a junction equals the total current leaving it. This is a direct consequence of charge conservation — no charge can be created or destroyed in a circuit node.
基尔霍夫第一定律指出，进入一个节点的总电流等于离开该节点的总电流。这是电荷守恒的直接结果——电荷在电路节点处既不能被创造也不能被消灭。
Mathematically, for any junction, ∑I_in = ∑I_out, or equivalently ∑I = 0 when currents entering are taken as positive and leaving as negative. You must assign direction consistently.
数学上，对任意节点，∑I入 = ∑I出，或者当规定流入电流为正、流出为负时，∑I = 0。必须一致地规定电流方向。
In practical terms, if 3.0 A flows into a point where the path splits into two branches, and one branch carries 1.2 A, the other must carry 1.8 A. KCL is readily tested using ammeters at different points in a parallel network.
实际中，如果 3.0 A 流入一个分为两条支路的节点，其中一条支路电流为 1.2 A，那么另一条支路必定流过 1.8 A。在并联网络中的不同点使用安培计可以轻松验证 KCL。
2. Kirchhoff’s Voltage Law (KVL) | 基尔霍夫电压定律
Kirchhoff’s second law states that the sum of the electromotive forces (emfs) around any closed loop equals the sum of the potential differences (p.d.s) across the components in that loop. It reflects the conservation of energy — the energy gained by a charge passing through a source must equal the energy transferred to components.
基尔霍夫第二定律指出，沿任意闭合回路的电动势之和等于该回路中各元件两端电势差之和。这反映了能量守恒——电荷通过电源获得的能量必须等于传递给元件的能量。
In equation form: ∑ε = ∑IR, where ε is the emf and IR is the voltage drop across a resistor. The direction of the loop traversal must be assigned, and voltage rises and drops are signed accordingly.
方程形式为：∑ε = ∑IR，其中 ε 为电动势，IR 为电阻两端的电压降。必须规定回路绕向，并据此标记电压升和电压降的符号。
For a simple series circuit with a cell of 6.0 V and two resistors of 2.0 Ω and 4.0 Ω, KVL gives 6.0 = I×2.0 + I×4.0, giving I = 1.0 A. The voltage drop across the 4.0 Ω resistor is 4.0 V, confirming that the sum of p.d.s equals the supply emf.
对于一个简单的串联电路，包含一个 6.0 V 的电池以及 2.0 Ω 和 4.0 Ω 的两个电阻，由 KVL 可得 6.0 = I×2.0 + I×4.0，解得 I = 1.0 A。4.0 Ω 电阻两端的电压降为 4.0 V，确认了各电势差之和等于电源电动势。
3. Sign Conventions in Loop Analysis | 回路分析中的符号规则
A consistent sign convention is critical for applying KVL correctly. The ‘battery rule’: when travelling through a cell from negative to positive terminal, the emf is taken as positive (+ε); from positive to negative, it is negative (−ε). This is independent of current direction.
一致的符号规则对正确应用 KVL 至关重要。“电池法则”：当从电池的负端走向正端穿过电池时，电动势取正值（+ε）；从正端到负端则取负值（−ε）。这与电流方向无关。
The ‘resistor rule’: if the loop traversal is in the same direction as the assumed current through a resistor, the potential change is −IR (voltage drop); if opposite, it is +IR. Always mark assumed current directions before writing equations.
“电阻法则”：如果回路绕行方向与假设的流过电阻的电流方向一致，则电势变化为 −IR（电压降）；如果相反，则为 +IR。在书写方程之前务必标记假设的电流方向。
If your final calculated current is negative, it simply means the actual direction is opposite to your assumption. The magnitude remains correct. Exam mark schemes reward clearly stated current arrows and signed equation steps.
如果最终计算出的电流值为负，这仅意味着实际方向与你假设的方向相反。其大小仍然正确。考试评分方案会奖励清晰标出的电流箭头以及带符号的方程步骤。
4. Applying KCL and KVL to Series and Parallel Networks | 将 KCL 和 KVL 应用于串并联网络
For a purely series circuit, the current is the same everywhere (KCL is trivially satisfied). KVL then directly yields the total resistance: R_total = R₁ + R₂ + R₃ + … The voltage divides in proportion to resistance.
对于纯串联电路，各处电流相同（KCL 自然满足）。KVL 可直接得出总电阻：R总 = R₁ + R₂ + R₃ + … 电压按电阻比例分配。
In a parallel network, KCL governs the current splits. The potential difference across each branch is the same (KVL along any loop consisting of one branch and back through the source). The total current from the source equals the sum of branch currents.
在并联网络中，KCL 决定电流分配。各支路两端的电势差相同（沿任一支路并通过电源返回的回路，KVL 均成立）。电源提供的总电流等于各支路电流之和。
Combining these laws allows the derivation of the parallel resistance formula: 1/R_total = 1/R₁ + 1/R₂. Use KCL at the junction and KVL to equate branch voltages, then solve for the total resistance seen by the source.
结合这两条定律可以推导出并联电阻公式：1/R总 = 1/R₁ + 1/R₂。在节点使用 KCL，并利用 KVL 令各支路电压相等，然后求解电源所看到的总电阻。
5. Multi-Loop Circuits and Simultaneous Equations | 多回路电路与联立方程组
When a circuit contains more than one loop, you need multiple equations. Label each branch current (I₁, I₂, I₃) and write KCL equations at each junction. Then apply KVL to independent loops, choosing loops that cover every branch at least once.
当电路含有多于一个回路时，需要多个方程。标记各支路电流（I₁，I₂，I₃），并在每个节点写出 KCL 方程。然后对独立回路应用 KVL，所选回路需至少覆盖每条支路一次。
For a typical two-loop circuit with two sources and three resistors, you will obtain three equations (one KCL and two KVLs). Solve the system by substitution or elimination to find each current. IB and CIE exams often present such ‘bridged’ or multi-source networks.
对于一个含有两个电源和三个电阻的典型两回路电路，你将得到三个方程（一个 KCL 和两个 KVL）。通过代入法或消元法求解方程组，得出每条电流。IB 和 CIE 考试中常出现此类“桥式”或多电源网络。
Use matrix method or standard algebraic manipulation. Always check if the calculated current values satisfy the original KCL equation and that voltages in any loop sum to zero, verifying the solution.
使用矩阵方法或常规代数运算。务必检查计算出的电流值是否满足原始 KCL 方程，并且任意回路中的电压总和为零，以验证解答。
6. Worked Example: Two-Source Network | 实例解析：双电源网络
Consider a circuit with a 12 V battery and a 6 V battery connected in a loop with three resistors: R₁ = 2.0 Ω in series with the 12 V source, R₂ = 3.0 Ω in the common branch, and R₃ = 4.0 Ω in series with the 6 V source. Assume currents I₁ leaving the 12 V positive, I₂ leaving the 6 V positive, and I₃ through R₂ as the combined return.
考虑一个电路，其中 12 V 电池和 6 V 电池与三个电阻相连：R₁ = 2.0 Ω 与 12 V 电源串联，R₂ = 3.0 Ω 位于公共支路，R₃ = 4.0 Ω 与 6 V 电源串联。假设电流 I₁ 从 12 V 正极流出，I₂ 从 6 V 正极流出，I₃ 为流过 R₂ 的汇合返回电流。
KCL at the top junction: I₁ + I₂ = I₃. Loop 1 (12 V, R₁, R₂): 12 = 2I₁ + 3I₃. Loop 2 (6 V, R₃, R₂): 6 = 4I₂ + 3I₃. Substitute I₃ from KCL into the loops, then solve. The result: I₁ = 1.5 A, I₂ = 0 A, I₃ = 1.5 A. This shows the 6 V battery is not delivering current — it is being charged.
顶部节点的 KCL：I₁ + I₂ = I₃。回路 1（12 V，R₁，R₂）：12 = 2I₁ + 3I₃。回路 2（6 V，R₃，R₂）：6 = 4I₂ + 3I₃。将 KCL 中的 I₃ 代入回路方程，然后求解。结果：I₁ = 1.5 A，I₂ = 0 A，I₃ = 1.5 A。这表明 6 V 电池并未输出电流——它正在被充电。
Such outcomes illustrate why the sign convention matters. A zero or negative current for a source is physically meaningful and must be reported as found. Exams often include a source that opposes the main current flow.
这类结果说明了符号规则为何重要。电源电流为零或负值具有物理意义，必须按计算结果如实报告。考试中经常包含一个与主电流方向相反的电源。
7. Kirchhoff’s Laws and Internal Resistance | 基尔霍夫定律与内阻
Real cells have internal resistance r. When drawing the circuit, include r as a small resistor in series with the ideal emf. KVL for a simple loop: ε = I(R + r) where R is the external load. This explains terminal p.d. dropping as current increases.
真实的电池存在内阻 r。画电路图时，将 r 画为一个与理想电动势串联的小电阻。对简单回路应用 KVL：ε = I(R + r)，其中 R 为外接负载。这解释了端电压随电流增大而下降的现象。
In multi-loop circuits with internal resistances, treat each cell as an ideal emf in series with its r. Write KVL as usual, incorporating r voltage drops. You may be asked to find r given terminal p.d. and current.
在含内阻的多回路电路中，将每个电池视为理想电动势与其内阻 r 串联。像往常一样书写 KVL，将 r 上的电压降纳入。可能会要求根据端电压和电流求出 r。
For two cells with internal resistances connected in parallel to a load, KCL and KVL equations become slightly longer, but the method is unchanged. Use the terminal voltage V expressed as ε – Ir for each branch.
对于两个带内阻的电池并联连接到一个负载的情况，KCL 和 KVL 方程会稍长一些，但方法不变。使用端电压 V 表示为 ε – Ir（每条支路均如此）。
8. Kirchhoff’s Laws and Potential Dividers | 基尔霍夫定律与分压器
A potential divider consists of two resistors in series across a supply. KVL gives V_out = V_in × (R₂/(R₁+R₂)). This is a direct consequence of the fact that the same current flows through both resistors and the sum of p.d.s equals the supply emf.
分压器由两个电阻串联跨接在电源两端构成。由 KVL 可得 V出 = V入 × (R₂/(R₁+R₂))。这是相同电流流过两个电阻且各电势差之和等于电源电动势这一事实的直接结果。
When a load is connected across the output, KCL at the junction splits the current, altering the division ratio. The loaded potential divider is a classic exam problem that requires applying both KCL and KVL to analyse.
当输出端跨接负载时，节点处的 KCL 将电流分流，改变了分压比例。加载后的分压器是典型的考题，需要同时应用 KCL 和 KVL 进行分析。
First, calculate the Thévenin equivalent or solve the full network using loop equations. A common approach is to find the total resistance seen by the source, the main current, and then use KCL to find branch currents and output voltage.
首先计算戴维南等效电路，或利用回路方程求解完整网络。常见的做法是先求出电源所看到的总电阻以及干路电流，然后利用 KCL 求支路电流和输出电压。
9. Experimental Verification | 实验验证
KVL and KCL are empirically testable using simple apparatus: a power supply, resistors, connecting wires, ammeters, and voltmeters. For KCL, measure currents entering and leaving a junction; they should sum to zero within experimental uncertainty.
KVL 和 KCL 可用简单器材进行实验检验：电源、电阻、导线、安培计和伏特计。对于 KCL，测量流入和流出节点的电流；在实验误差范围内它们之和应为零。
For KVL, connect a voltmeter across components in a closed loop and record potential differences. The sum of these voltages, with appropriate signs, should equal zero. Discrepancies arise from contact resistance and meter internal resistance.
对于 KVL，在闭合回路中将伏特计跨接于各元件两端，记录电势差。这些电压按适当符号求和后应等于零。接触电阻和电表内阻会引起偏差。
IB and CIE examinations may ask you to describe a procedure, list potential sources of error, or suggest improvements. Emphasise using high-impedance voltmeters and zeroing meters before measurement.
IB 和 CIE 考试可能要求你描述实验步骤、列出可能的误差来源或提出改进建议。要强调使用高阻抗伏特计并在测量前对仪表调零。
10. Common Mistakes and How to Avoid Them | 常见错误及避免方法
One frequent error is failing to assign current directions consistently, leading to sign errors in KVL. Always draw arrows for every branch current before writing any equation, and stick to a chosen loop direction.
一个常见错误是未能一致地规定电流方向，导致 KVL 中出现符号错误。在书写任何方程前，务必为每条支路电流画上箭头，并坚持所选回路方向。
Another pitfall is mixing up emf polarity. Remember: emf is a rise when moving from − to +. If you traverse the source the ‘wrong’ way, its contribution is negative. Use the ‘plus near the long line’ cell symbol as a reminder.
另一个陷阱是混淆电动势的极性。请记住：当从 − 走向 + 时，电动势是升高的。如果你按“错误”方向穿过电源，其贡献为负。可使用电池符号“长线为正”的特征来提醒自己。
Students sometimes forget to include internal resistance in the KVL loop, especially when a question asks for terminal p.d. or power dissipated inside the cell. Always check if internal resistance is mentioned or implied by ‘real cell’.
学生有时会忘记在 KVL 回路中包含内阻，尤其是当题目问及端电压或电池内部的耗散功率时。务必检查题目是否提及内阻，或由“真实电池”暗示内阻存在。
Finally, do not assume that current directions you choose must be correct. A negative answer is perfectly acceptable and represents opposite physical flow. Stating ‘current is -0.5 A’ is better than arbitrarily flipping assumptions halfway.
最后，不要假设你所选的电流方向必须正确。负的答案完全可接受，代表物理流向相反。写出“电流为 -0.5 A”比中途随意颠倒假设要好得多。
11. Exam-Style Question Walkthrough | 考试题型精练
Question: A circuit contains a 9.0 V battery with internal resistance 1.0 Ω, connected in series with a parallel combination of 6.0 Ω and 3.0 Ω resistors. Find the terminal p.d. and the current through the 3.0 Ω resistor. (a) Calculate the total external resistance. (b) Use KVL to find the total current. (c) Apply KCL to find branch currents.
题目：一个电路包含一个 9.0 V 的电池（内阻 1.0 Ω），与 6.0 Ω 和 3.0 Ω 电阻的并联组合串联。求端电压以及流过 3.0 Ω 电阻的电流。（a）计算外电阻总阻值。（b）利用 KVL 求总电流。（c）应用 KCL 求支路电流。
External parallel resistance: R_parallel = (6×3)/(6+3) = 2.0 Ω. Total circuit resistance: R_total = 2.0 + 1.0 = 3.0 Ω. KVL: 9.0 = I×3.0 ⇒ I = 3.0 A (total current). Terminal p.d.: V_terminals = ε – Ir = 9.0 – (3.0×1.0) = 6.0 V.
外并联电阻：R并 = (6×3)/(6+3) = 2.0 Ω。总电路电阻：R总 = 2.0 + 1.0 = 3.0 Ω。KVL：9.0 = I×3.0 ⇒ I = 3.0 A（总电流）。端电压：V端 = ε – Ir = 9.0 – (3.0×1.0) = 6.0 V。
KCL at the parallel junction: the total current I splits into I₆ and I₃. Since the voltage across parallel branches is the same: V_parallel = 6.0 V (the terminal p.d.). Then I₃ = V_parallel / 3.0 = 2.0 A. I₆ = V_parallel / 6.0 = 1.0 A. Check: I₃ + I₆ = 3.0 A, matching KCL.
并联节点的 KCL：总电流 I 分为 I₆ 和 I₃。由于并联支路电压相同：V并 = 6.0 V（即端电压）。于是 I₃ = V并 / 3.0 = 2.0 A，I₆ = V并 / 6.0 = 1.0 A。验证：I₃ + I₆ = 3.0 A，符合 KCL。
This systematic approach — simplify network, apply KVL, then KCL — will handle most single- and dual-loop problems. Always perform a sanity check on the results.
这种系统方法——简化网络、应用 KVL、然后 KCL——将处理大多数单回路和双回路问题。始终对结果进行合理性检查。
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