Systems Software, Machine Architecture, Databases, Programming Paradigms and Integrated Information Systems | 系统软件机制、机器架构、数据库理论、编程范式与集成信息系统

📚 Systems Software, Machine Architecture, Databases, Programming Paradigms and Integrated Information Systems | 系统软件机制、机器架构、数据库理论、编程范式与集成信息系统

This article provides a consolidated Cambridge A Level Computer Science revision guide covering systems software mechanisms, machine architecture, database theory, programming paradigms and integrated information systems. It explains key concepts, common exam command terms and practical links between topics.

本文提供剑桥A Level计算机科学综合复习指南，涵盖系统软件机制、机器架构、数据库理论、编程范式与集成信息系统。文章解释核心概念、常见考试指令词及各主题之间的实际联系。

1. Systems Software and Operating System Roles | 系统软件与操作系统角色

System software is the layer of programs that manages hardware resources and provides a platform for application software. It includes the operating system, utility programs, language translators and library routines. The operating system (OS) performs process management, memory management, file management, device management and security enforcement.

系统软件是管理硬件资源并为应用软件提供平台的程序层，包括操作系统、实用程序、语言翻译器和库例程。操作系统负责进程管理、内存管理、文件管理、设备管理和安全实施。

Key OS roles include providing a user interface, handling interrupts, scheduling processes and managing input/output through device drivers. Utility software performs maintenance tasks such as disk defragmentation, backup, compression and antivirus scanning.

操作系统的关键角色包括提供用户界面、处理中断、调度进程以及通过设备驱动程序管理输入输出。实用软件执行维护任务，例如磁盘碎片整理、备份、压缩和病毒扫描。

2. Interrupts, Scheduling and Process States | 中断、调度与进程状态

An interrupt is a signal that causes the CPU to suspend its current instruction sequence and transfer control to an interrupt service routine (ISR). Hardware interrupts come from devices such as keyboards or timers; software interrupts are generated by programs or errors such as division by zero.

中断是一种信号，使CPU暂停当前指令序列并将控制权转移到中断服务程序（ISR）。硬件中断来自键盘或定时器等设备；软件中断由程序或错误（如除零）产生。

Scheduling algorithms decide which process runs next. Round robin gives each process a fixed time slice; first come first served is simple but can cause long waiting times; shortest job first minimises average waiting time but requires knowing process length; priority scheduling may starve low-priority jobs.

调度算法决定下一个运行的进程。轮转法为每个进程分配固定时间片；先来先服务简单但可能造成长等待时间；最短作业优先使平均等待时间最小但需预知进程长度；优先级调度可能使低优先级作业饥饿。

Process states move from ‘ready’ to ‘running’ when selected by the scheduler, and from ‘running’ to ‘blocked’ when waiting for I/O or an event, then back to ‘ready’ when the event completes.

进程状态在被调度器选中时从 ‘就绪’ 变为 ‘运行’，在等待I/O或事件时从 ‘运行’ 变为 ‘阻塞’，事件完成后再回到 ‘就绪’。

3. Memory Management and Virtual Memory | 内存管理与虚拟内存

Memory management allocates RAM to processes and protects each process’s address space. Paging divides physical memory into fixed-size page frames and logical memory into pages of the same size; segmentation divides programs into variable-sized logical segments such as code, data and stack.

内存管理将RAM分配给进程并保护各进程的地址空间。分页将物理内存划分为固定大小的页框，将逻辑内存划分为相同大小的页；分段将程序划分为可变大小的逻辑段，如代码段、数据段和栈段。

Virtual memory allows a process to use more memory than physically available by moving pages or segments to secondary storage. If the system spends excessive time swapping pages instead of executing instructions, thrashing occurs and performance collapses.

虚拟内存通过将页或段移至辅助存储器，使进程可使用超过物理内存的空间。如果系统花费过多时间换页而不是执行指令，就会发生抖动，性能急剧下降。

The memory management unit (MMU) translates logical addresses to physical addresses using page tables or segment tables, enabling relocation and protection.

内存管理单元（MMU）使用页表或段表将逻辑地址转换为物理地址，从而实现重定位和保护。

4. Machine Architecture: CPU Components and Buses | 机器架构：CPU组件与总线

The central processing unit (CPU) contains the arithmetic logic unit (ALU), the control unit (CU) and registers such as the program counter (PC), memory address register (MAR), memory data register (MDR), current instruction register (CIR) and accumulator (ACC).

中央处理器（CPU）包含算术逻辑单元（ALU）、控制单元（CU）以及寄存器，如程序计数器（PC）、内存地址寄存器（MAR）、内存数据寄存器（MDR）、当前指令寄存器（CIR）和累加器（ACC）。

Three buses connect the CPU to memory and I/O: the address bus carries memory locations and is unidirectional; the data bus carries data and is bidirectional; the control bus carries timing and control signals such as read, write and interrupt requests.

三条总线将CPU与内存和I/O连接：地址总线传输内存位置，是单向的；数据总线传输数据，是双向的；控制总线传输时序和控制信号，如读、写和中断请求。

Von Neumann architecture uses a single memory for both instructions and data, causing the von Neumann bottleneck; Harvard architecture separates instruction and data memory, allowing simultaneous access and improved speed in embedded systems.

冯·诺依曼架构使用单一存储器同时存放指令和数据，导致冯·诺依曼瓶颈；哈佛架构将指令存储器和数据存储器分离，允许同时访问，在嵌入式系统中速度更快。

5. The Fetch-Decode-Execute Cycle and Assembly Language | 取指-译码-执行周期与汇编语言

The fetch-decode-execute cycle is the fundamental operation of a CPU. Fetch copies the address from PC to MAR, reads the instruction into MDR and then CIR while PC increments. Decode interprets the opcode and operand. Execute carries out the operation using the ALU or data transfer.

取指-译码-执行周期是CPU的基本工作

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