Computer Architecture & The Fetch-Execute Cycle | 计算机体系结构与取指执行周期

📚 Computer Architecture & The Fetch-Execute Cycle | 计算机体系结构与取指执行周期

Computer architecture is the blueprint of how a computer system is designed and how its components work together to process data. For CIE A-Level Computer Science, a deep understanding of the central processing unit (CPU), memory organisation, and the fetch-execute cycle is essential for exam success.

计算机体系结构是计算机系统设计的蓝图，它描述了各个组件如何协同工作以处理数据。在CIE A-Level计算机科学中，深入理解中央处理单元（CPU）、存储器组织以及取指执行周期，是取得考试成功的关键。

1. The Von Neumann Architecture | 冯·诺依曼体系结构

The Von Neumann architecture is the foundational model on which most modern computers are based. It was proposed by John von Neumann in 1945 and introduced the concept of the stored-program computer, where both data and instructions are stored in the same memory unit.

冯·诺依曼体系结构是现代大多数计算机所基于的基础模型。它由约翰·冯·诺依曼于1945年提出，引入了”存储程序”计算机的概念，即数据和指令都存储在同一个存储器单元中。

In this architecture, the CPU fetches instructions from memory, decodes them, and executes them sequentially. The key components include the arithmetic logic unit (ALU), the control unit (CU), registers, and memory. The system uses a single shared bus for data, instruction, and address transfers, which is known as the Von Neumann bottleneck.

在该体系结构中，CPU从存储器中取指令，进行译码，然后按顺序执行。关键组件包括算术逻辑单元（ALU）、控制单元（CU）、寄存器和存储器。系统使用单一共享总线来传输数据、指令和地址，这被称为冯·诺依曼瓶颈。

2. Central Processing Unit (CPU) Components | 中央处理单元（CPU）组件

The CPU is often referred to as the ‘brain’ of the computer. It is responsible for executing instructions by performing arithmetic, logical, control, and input/output operations. The CPU is composed of several key components that work together to process data.

CPU通常被称为计算机的”大脑”。它负责通过执行算术、逻辑、控制和输入/输出操作来处理指令。CPU由多个关键组件组成，这些组件协同工作以处理数据。

The Arithmetic Logic Unit (ALU) performs all arithmetic operations such as addition, subtraction, multiplication, and division, as well as logical operations such as AND, OR, NOT, and XOR. The ALU also handles comparisons between values by setting flag bits.

算术逻辑单元（ALU）执行所有算术运算，如加、减、乘、除，以及逻辑运算，如AND、OR、NOT和XOR。ALU还通过设置标志位来处理数值之间的比较。

The Control Unit (CU) coordinates the activities of all hardware components. It fetches instructions from memory, decodes them, and generates control signals that direct the operation of the ALU, registers, and input/output devices.

控制单元（CU）协调所有硬件组件的活动。它从存储器中取出指令，对其进行译码，并生成控制信号来指导ALU、寄存器和输入/输出设备的操作。

Registers are high-speed storage locations within the CPU. They store intermediate data, instructions, addresses, and control information. The CPU also contains internal buses that allow data to move between registers and other components efficiently.

寄存器是CPU内部的高速存储位置。它们存储中间数据、指令、地址和控制信息。CPU还包含允许数据在寄存器和其他组件之间高效移动的内部总线。

3. Harvard Architecture | 哈佛体系结构特征

The Harvard architecture is an alternative computer design that physically separates instruction storage from data storage. Unlike the Von Neumann architecture, where instructions and data share the same memory and bus, the Harvard architecture uses separate memory units and dedicated buses for each.

哈佛体系结构是一种替代性的计算机设计，它在物理上将指令存储与数据存储分开。与指令和数据共享同一存储器和总线的冯·诺依曼体系结构不同，哈佛体系结构为指令和数据使用各自的存储器和专用总线。

This separation allows the CPU to fetch an instruction and read or write data simultaneously, which improves overall performance. However, it is more complex and costly to implement because of the duplicated memory and bus infrastructure.

这种分离允许CPU同时取指令和读写数据，从而提高了整体性能。然而，由于存储器和总线基础设施的重复，实现起来更加复杂和昂贵。

Harvard architecture is commonly used in embedded systems and digital signal processors (DSPs), where speed and efficiency are critical. Some modern processors, such as the ARM Cortex series, use a modified Harvard architecture that combines features of both designs.

哈佛体系结构通常用于嵌入式系统和数字信号处理器（DSP），这些场景对速度和效率要求较高。一些现代处理器（如ARM Cortex系列）采用改良型哈佛体系结构，结合了两种设计的优点。

4. Main Memory & Addressing | 主存储器与寻址

Main memory is a crucial component in computer architecture. It stores the data and instructions that the CPU needs to access quickly. In the Von Neumann model, main memory is a linear array of addressable cells, each capable of storing one byte of data.

主存储器是计算机体系结构中的关键组件。它存储CPU需要快速访问的数据和指令。在冯·诺依曼模型中，主存储器是可以寻址的线性单元数组，每个单元可以存储一个字节的数据。

Each memory cell has a unique address, starting from zero. When the CPU needs to read or write data, it sends the address of the desired memory cell to the memory unit via the address bus. The memory unit then responds by placing the data on the data bus, or by storing the data provided by the CPU.

每个存储单元都有一个从零开始的唯一地址。当CPU需要读写数据时，它通过地址总线将目标存储单元的地址发送到存储器单元。然后，存储器单元通过将数据放到数据总线上来响应，或者存储CPU提供的数据。

Memory addresses in a typical modern system are represented in hexadecimal. For example, a memory address of 148 in decimal may be written as 0x94 in hexadecimal notation. The width of the address bus determines the maximum addressable memory space.

典型现代系统中的内存地址以十六进制表示。例如，十进制中的148可以写为十六进制的0x94。地址总线的宽度决定了最大可寻址的存储空间。

Maximum Memory = 2ⁿ bytes, where n = address bus width

最大内存 = 2ⁿ 字节，其中 n = 地址总线宽度

5. The System Bus | 系统总线

The system bus is a set of parallel wires or pathways that connect the CPU, memory, and input/output devices. It provides a communication channel for transferring data, addresses, and control signals between the components of a computer system.

系统总线是一组连接CPU、存储器和输入/输出设备的并行导线或通路。它提供了一个用于在计算机系统各组件之间传输数据、地址和控制信号的通信通道。

The address bus is unidirectional and carries memory addresses from the CPU to memory or I/O devices. The width of the address bus determines the maximum number of addressable memory locations.

地址总线是单向的，用于将存储地址从CPU传送到存储器或I/O设备。地址总线的宽度决定了可寻址存储位置的最大数量。

The data bus is bidirectional and carries actual data between the CPU, memory, and I/O devices. A wider data bus allows more data to be transferred at once. For instance, a 64-bit data bus can transfer 8 bytes in a single operation.

数据总线是双向的，用于在CPU、存储器和I/O设备之间传输实际数据。更宽的数据总线允许一次传输更多数据。例如，64位数据总线可以在单次操作中传输8个字节。

The control bus carries control signals generated by the control unit. These signals coordinate activities such as read/write operations, timing signals, and interrupt requests, ensuring that all components operate synchronously.

控制总线传输由控制单元生成的控制信号。这些信号协调各种活动，如读/写操作、时序信号和中断请求，确保所有组件同步运行。

6. Key Registers in the CPU | CPU中的关键寄存器

Registers are small, high-speed storage locations within the CPU that temporarily hold data and instructions during processing. In the fetch-execute cycle, several specific registers play critical roles. Understanding these registers is vital for answering exam questions on computer architecture.

寄存器是CPU内小型、高速的存储位置，在处理器操作期间临时保存数据和指令。在取指执行周期中，几个特定的寄存器扮演着关键角色。理解这些寄存器对于回答计算机体系结构相关的考试题目至关重要。

The Program Counter (PC) holds the address of the next instruction to be fetched. After an instruction is fetched, the PC is updated to point to the next instruction in sequence, unless a branch or jump occurs.

程序计数器（PC）保存下一条要取出的指令的地址。在一条指令被取出后，PC会被更新以指向序列中的下一条指令，除非发生分支或跳转。

The Memory Address Register (MAR) holds the address of the memory location that is currently being accessed, either for reading or writing. It is connected to the address bus.

存储器地址寄存器（MAR）保存当前正在访问的存储位置的地址，无论是读取还是写入。它与地址总线相连。

The Memory Data Register (MDR), also known as the Memory Buffer Register (MBR), holds the data that has been read from memory or the data that is about to be written to memory. It is connected to the data bus.

存储器数据寄存器（MDR），也称为存储缓冲寄存器（MBR），保存已从存储器读取的数据或即将写入存储器的数据。它与数据总线相连。

The Current Instruction Register (CIR) holds the instruction that is currently being decoded and executed. The Instruction Decoder within the control unit examines the opcode stored in the CIR to determine what action should be taken.

当前指令寄存器（CIR）保存当前正在被译码和执行的指令。控制单元中的指令译码器检查CIR中存储的操作码，以确定应执行什么操作。

7. The Fetch-Execute Cycle | 取指执行周期（取指-译码-执行周期）

The fetch-execute cycle, also known as the instruction cycle, is the fundamental process by which the CPU retrieves and executes instructions. It consists of three main phases: fetch, decode, and execute. This cycle repeats continuously for every instruction in a program.

取指执行周期，也称为指令周期，是CPU检索并执行指令的基本过程。它包含三个主要阶段：取指、译码和执行。该周期对程序中的每条指令连续重复。

In the fetch phase, the control unit transfers the contents of the Program Counter (PC) to the Memory Address Register (MAR). The address in the MAR is then sent out on the address bus, and the memory unit returns the instruction stored at that address to the Memory Data Register (MDR).

在取指阶段，控制单元将程序计数器（PC）的内容传输到存储器地址寄存器（MAR）。MAR中的地址被发送到地址总线上，存储器单元将存储在该地址的指令返回到存储器数据寄存器（MDR）。

Once the instruction is in the MDR, it is moved to the Current Instruction Register (CIR). At this point, the PC is incremented so that it points to the next instruction in sequence. This ensures that the CPU knows where to fetch the subsequent instruction from.

一旦指令进入MDR，它会被移动到当前指令寄存器（CIR）。此时，PC递增，使其指向序列中的下一条指令。这确保CPU知道从何处取后续指令。

In the decode phase, the Instruction Decoder interprets the opcode in the CIR and determines which operation the CPU must perform. It also identifies the operand addresses, which may be in memory or in registers, so that the execution unit can retrieve the required data.

在译码阶段，指令译码器解释CIR中的操作码，确定CPU必须执行什么操作。它还识别操作数地址，这些地址可能在存储器中或寄存器中，以便执行单元可以检索所需的数据。

In the execute phase, the control unit sends control signals to the ALU or other components to carry out the operation. This may involve arithmetic calculations, logical comparisons, storing data to memory, or reading from an input/output device.

在执行阶段，控制单元向ALU或其他组件发送控制信号以执行操作。这可能涉及算术计算、逻辑比较、向存储器存储数据或从输入/输出设备读取数据。

PC → MAR → Address Bus → Memory → MDR → CIR → Increment PC → Decode → Execute

PC → MAR → 地址总线 → 存储器 → MDR → CIR → PC递增 → 译码 → 执行

8. Detailed Steps of the Fetch Stage | 取指阶段的详细步骤

The fetch stage is the first phase of the instruction cycle. Its purpose is to read an instruction from memory and bring it into the CPU. The steps of the fetch stage are precise and must be understood in the correct order for exam questions that ask students to describe the process.

取指阶段是指令周期的第一阶段。其目的是从存储器读取指令并将其带入CPU。取指阶段的步骤是精确的，必须以正确的顺序理解，以应对考试中要求描述该过程的问题。

The address of the next instruction is copied from the PC to the MAR.

下一条指令的地址从PC复制到MAR中。
The address held in the MAR is placed on the address bus.

MAR中保存的地址被放到地址总线上。
The control unit sends a read signal on the control bus.

控制单元在控制总线上发送读取信号。
The memory unit locates the address and places the instruction at that address on the data bus.

存储器单元定位该地址，并将位于该地址的指令放到数据总线上。
The instruction is loaded from the data bus into the MDR.

该指令从数据总线加载到MDR中。
The instruction is then moved from the MDR to the CIR for decoding.

该指令随后从MDR移动到CIR进行译码。
Simultaneously, the PC is incremented (PC ← PC + 1) to point to the next instruction.

同时，PC递增（PC ← PC + 1）以指向下一条指令。

9. Interrupts and the Fetch-Execute Cycle | 中断与取指执行周期

An interrupt is a signal sent to the CPU that temporarily suspends the current program and causes the CPU to execute a special routine called the interrupt service routine (ISR). Interrupts are essential for allowing the CPU to respond to real-time events, such as a key press or a hardware timer.

中断是发送给CPU的一种信号，它会暂时挂起当前程序，并导致CPU执行一个称为中断服务例程（ISR）的特殊例程。中断对于允许CPU响应实时事件（如按键或硬件定时器）至关重要。

Between each instruction in the fetch-execute cycle, the CPU checks whether an interrupt has been received. If an interrupt is pending and interrupts are enabled, the CPU finishes the current instruction, saves the context of the current process (including the PC), and then loads the address of the appropriate ISR into the PC.

在取指执行周期的每条指令之间，CPU会检查是否收到中断。如果有一个挂起的中断且中断已启用，CPU完成当前指令，保存当前进程的上下文（包括PC），然后将相应的ISR地址加载到PC中。

After the ISR has been completed, the CPU restores the saved context, and the original program resumes executing from where it left off. This mechanism allows the CPU to handle multiple tasks efficiently without losing track of the current execution state.

在ISR完成后，CPU恢复保存的上下文，原始程序从其中断的位置继续执行。这种机制允许CPU高效地处理多个任务，而不会丢失当前执行状态。

10. Comparing Von Neumann and Harvard Architectures | 冯·诺依曼体系与哈佛体系结构对比

Understanding the differences between Von Neumann and Harvard architectures is a common exam topic. The table below summarises the key distinctions between the two designs. The primary difference lies in how each architecture treats instruction and data memory.

理解冯·诺依曼体系结构与哈佛体系结构之间的差异是常见的考试主题。下表总结了两种设计之间的主要区别。主要区别在于每种体系结构如何处理指令和数据存储器。

Feature \| 特征	Von Neumann \| 冯·诺依曼	Harvard \| 哈佛
Memory \| 存储器	Single shared memory for data & instructions 数据和指令共享单一存储器	Separate memory for data & instructions 数据和指令有各自独立的存储器
Buses \| 总线	One shared bus system 单一共享总线系统	Dedicated buses for data and instructions 数据和指令有专用总线
Speed \| 速度	Slower due to bottleneck 因瓶颈效应而较慢	Faster, simultaneous access 更快，可同时访问
Complexity \| 复杂度	Simpler, cheaper 较简单、较便宜	More complex, more expensive 较复杂、较昂贵
Typical use \| 典型用途	General-purpose computers 通用计算机	Embedded systems, DSPs 嵌入式系统、数字信号处理器

It is important to note that modern processors often use a modified Harvard architecture. This design keeps the instruction and data caches separate to gain speed benefits while still using a unified main memory. This hybrid approach balances performance and cost.

需要注意的是，现代处理器通常采用改良型哈佛体系结构。这种设计将指令缓存和数据缓存分离以获得速度优势，同时仍使用统一的主存储器。这种混合方法在性能和成本之间取得了平衡。

11. Exam Focus: Common Questions & Tips | 考试重点：常见问题与提示

Examination questions on this topic often require students to describe the stages of the fetch-execute cycle, explain the functions of CPU components, and compare different architectures. Many students lose marks by mixing up the order of operations or by failing to mention the PC being incremented.

关于该主题的考试问题通常要求学生描述取指执行周期的各个阶段，解释CPU组件的功能，并比较不同的体系结构。许多学生因混淆操作顺序或未提及PC递增而失分。

A common question is: “Describe with the aid of a diagram, the fetch-execute cycle.” When answering this, always begin with the PC holding the address of the next instruction, then follow the sequence systematically: PC to MAR, MAR to address bus, memory read, data to MDR, MDR to CIR, increment PC, decode, execute.

一个常见的问题是：”借助图示描述取指执行周期。”回答这个问题时，始终从PC保存下一条指令的地址开始，然后系统地遵循该顺序：PC到MAR，MAR到地址总线，存储器读取，数据到MDR，MDR到CIR，PC递增，译码，执行。

Another common question concerns the width of the address bus. Remember that the maximum memory size is equal to 2 raised to the power of the number of address lines. For example, if the address bus is 32 bits wide, the CPU can address 2³² = 4,294,967,296 memory locations, which is 4 GiB.

另一个常见问题涉及地址总线的宽度。请记住，最大存储容量等于2的地址线数次方。例如，如果地址总线为32位宽，CPU可以寻址2³² = 4,294,967,296个存储器位置，即4 GiB。

Students should also be comfortable with binary and hexadecimal notation, as they may be asked to determine the contents of the PC or MAR after a certain number of instructions. Practising numbered step-by-step descriptions is strongly recommended for achieving full marks on these questions.

学生还应熟练掌握二进制和十六进制表示法，因为考试可能要求确定在若干条指令后PC或MAR的内容。强烈建议练习按编号分步骤的描述方式，以便在这些问题上获得满分。

12. Summary of the Fetch-Execute Cycle | 取指执行周期总结

The fetch-execute cycle is the heart of computer processing. It must be memorised in sequence, with the role of each register clearly understood. The cycle is continuous: after the execute phase, the entire cycle begins again with the next instruction’s fetch.

取指执行周期是计算机处理的核心。必须按顺序记忆它，并清楚理解每个寄存器的作用。该周期是连续循环的：在执行阶段之后，整个周期从取指下一条指令重新开始。

For the CIE exam, focus on accurate terminology and precise sequencing. Use the standard register names such as PC, MAR, MDR, and CIR without confusion. Always mention that the PC is incremented during the fetch stage, not after execution.

对于CIE考试，重点关注准确的术语和精确的顺序。使用标准寄存器名称，如PC、MAR、MDR和CIR，请不要混淆。始终提及PC在取指阶段递增，而不是在执行之后。

By combining a solid understanding of the Von Neumann architecture, the function of each register, and the exact steps of the fetch, decode, and execute phases, you will be well-prepared for any examination question on this topic.

通过将冯·诺依曼体系结构的扎实理解、每个寄存器的功能以及取指、译码和执行阶段的准确步骤相结合，您将为任何关于该主题的考试问题做好充分准备。

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Computer Architecture & The Fetch-Execute Cycle | 计算机体系结构与取指执行周期