📚 Logic Circuits, Boolean Expressions and Truth Tables | 逻辑电路、布尔表达式与真值表
In CIE A Level Computer Science, logic circuits are one of the key foundations of digital systems. Candidates are expected to interpret circuit diagrams, write Boolean expressions, construct truth tables, and simplify expressions using Boolean algebra and De Morgan’s theorems. These skills are tested directly in examination questions that ask for a circuit output, an equivalent expression, or a complete truth table.
在 CIE A Level 计算机科学中，逻辑电路是数字系统的重要基础之一。考生需要能够解读逻辑电路图、写出布尔表达式、构造真值表，并运用布尔代数与摩根定律进行化简。这些技能通常直接出现在考题中，要求考生判断电路输出、写出等价表达式或补全真值表。
1. Basic Logic Gates | 基本逻辑门
Every logic circuit is built from a small set of gates. In the CIE syllabus, you need to know the behaviour of AND, OR, NOT, NAND, NOR, XOR and XNOR gates. Each gate performs a Boolean operation on one or more inputs and produces a single output.
任何逻辑电路都由少量基本逻辑门构成。在 CIE 考纲中，你需要掌握与门、或门、非门、与非门、或非门、异或门和同或门的逻辑行为。每个逻辑门对一个或多个输入执行布尔运算，并产生唯一输出。
The three simplest gates are AND, OR and NOT. For an AND gate, the output is 1 only when all inputs are 1. For an OR gate, the output is 1 when at least one input is 1. A NOT gate, also called an inverter, outputs the opposite of its single input.
最简单的三种逻辑门是与门、或门和非门。与门在所有输入均为 1 时输出 1；或门在至少一个输入为 1 时输出 1；非门又称反相器，其输出与单一输入相反。
AND: Q = A · B
OR: Q = A + B
NOT: Q = A’
The symbol A’ is used for “NOT A” in many examination papers. You may also see this written as NOT A or using a bar above the letter. In this article, A’ means the complement of A.
A’ 在很多试卷中表示“非 A”。你也可以见到 NOT A 或字母上方加横线的写法。本文统一使用 A’ 表示 A 的补运算。
| A | B | Q = A · B | Q = A + B |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 |
2. Universal Gates: NAND and NOR | 通用逻辑门：与非门和或非门
A NAND gate is an AND gate followed by a NOT gate. Its output is 0 only when both inputs are 1. A NOR gate is an OR gate followed by a NOT gate. Its output is 1 only when both inputs are 0.
与非门就是与门后接一个非门，只有两个输入均为 1 时输出 0。或非门就是或门后接一个非门，只有两个输入均为 0 时输出 1。
NAND: Q = (A · B)’
NOR: Q = (A + B)’
NAND and NOR gates are called universal gates because any other logic gate can be constructed by using only NAND gates or only NOR gates. For example, connecting the two inputs of a NAND gate together gives a NOT gate: Q = (A · A)’ = A’.
与非门和或非门被称为通用门，因为仅使用与非门或仅使用或非门就能构造出其他所有逻辑门。例如，将与非门的两个输入端连接在一起，就得到非门：Q = (A · A)’ = A’。
| A | B | A + B | NAND (A · B)’ | NOR (A + B)’ |
|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 1 |
| 0 | 1 | 1 | 1 | 0 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 |
3. Exclusive Gates: XOR and XNOR | 异或门与同或门
The XOR gate, written as A ⊕ B, outputs 1 when the two inputs are different. The XNOR gate, often written as A ⊙ B, outputs 1 when the two inputs are equal. XOR and XNOR are particularly common in addition circuits and parity checking.
异或门记作 A ⊕ B，当两个输入不同时输出 1。同或门通常记作 A ⊙ B，当两个输入相同时输出 1。异或门和同或门常见于加法电路与奇偶校验中。
XOR: Q = A ⊕ B = A’B + AB’
XNOR: Q = A ⊙ B = A · B + A’B’
The XNOR output is the complement of the XOR output. If XOR gives 0, XNOR gives 1, and if XOR gives 1, XNOR gives 0.
同或门输出是异或门输出的相反值。若异或输出为 0，则同或输出为 1；若异或输出为 1，则同或输出为 0。
| A | B | A ⊕ B | A ⊙ B |
|---|---|---|---|
| 0 | 0 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
4. From Circuit to Boolean Expression | 从电路图到布尔表达式
To write a Boolean expression from a circuit, work from left to right and label the output of each gate with a temporary letter. Then combine these temporary outputs according to how the gates are connected.
要从电路图写出布尔表达式，应从左到右分析，并用临时字母标记每个逻辑门的输出，再根据门之间的连接方式组合这些临时输出。
Consider a circuit where A and B enter an AND gate, C enters a NOT gate, and the outputs of those two gates enter an OR gate. Let P be the output of the AND gate and Q be the output of the NOT gate.
例如，一个电路中 A 和 B 接入与门，C 接入非门，两个门的输出再接入或门。设 P 为与门输出，Q 为非门输出。
P = A · B
Q = C’
X = P + Q = (A · B) + C’
The parentheses in (A · B) are not strictly necessary because AND has higher precedence than OR, but they make the grouping clear. Many mark schemes accept both A · B + C’ and (A · B) + C’.
这里的括号 (A · B) 并非必须，因为与运算优先于或运算，但括号能更清楚地表示分组。多数评分标准同时接受 A · B + C’ 与 (A · B) + C’ 两种写法。
5. From Boolean Expression to Logic Circuit | 从布尔表达式到电路
To draw a circuit from a Boolean expression, identify the operations and their order. The usual precedence is NOT first, then AND, then OR. Parentheses should be followed before ordinary precedence.
要根据布尔表达式画电路，需要先确定运算及其先后顺序。通常的优先级是：先非运算，再与运算，最后或运算。如果表达式中存在括号，则应优先处理括号内的部分。
For the expression X = A · B + C’, there are three sub-expressions: A · B, C’, and the final OR operation. You would draw one AND gate for A and B, one NOT gate for C, and one OR gate for the two intermediate outputs.
对于表达式 X = A · B + C’，有三个子表达式：A · B、C’ 和最后的或运算。你应该画一个与门处理 A 和 B，一个非门处理 C，再用一个或门连接两个中间输出。
Now consider X = A · (B + C’). Here the parentheses indicate that B and C’ must be ORed first. The result of that OR gate is then ANDed with A. This expression is not equivalent to A · B + C’.
再考虑 X = A · (B + C’)。括号表示 B 和 C’ 必须先进行或运算，然后再把或门的结果与 A 进行与运算。该表达式与 A · B + C’ 并不等价。
X = A · (B + C’)
Notice how the position of the parentheses changes the entire structure of the circuit. Always match each gate to the operation it performs in the expression.
注意，括号的位置会改变整个电路的结构。在画图时，必须让每个逻辑门对应表达式中一次具体的布尔运算。
6. Constructing Truth Tables from Expressions | 由表达式构造真值表
A truth table shows the output of a circuit for every possible combination of inputs. For n inputs, there are 2ⁿ rows. For example, two inputs give 4 rows, three inputs give 8 rows, and four inputs give 16 rows.
真值表展示电路在所有可能输入组合下的输出。对于 n 个输入，共有 2ⁿ 行。例如，两个输入对应 4 行，三个输入对应 8 行，四个输入对应 16 行。
Let us build the truth table for X = (A + B) · C’. This expression has three inputs, so there are 8 rows. A reliable method is to add a column for each intermediate result.
下面我们为 X = (A + B) · C’ 构造真值表。该表达式有三个输入，因此共有 8 行。可靠的方法是先为每个中间结果增加一列。
| A | B | C | A + B | C’ | X = (A + B) · C’ |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 更多咨询请联系16621398022（同微信）
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