Microcomputer Principles: Key Difficulties Explained | 微机原理重难点解析

📚 Microcomputer Principles: Key Difficulties Explained | 微机原理重难点解析

Microcomputer principles form the theoretical foundation of computer science and engineering. Understanding the internal architecture, memory management, interrupts, and instruction execution of a microprocessor is essential for both written examinations and practical system design. This article systematically explains the core concepts and high-frequency examination points in a bilingual format.

微机原理是计算机科学与工程的理论基石。理解微处理器的内部结构、存储器管理、中断系统以及指令执行过程，对于笔试和实际系统设计都至关重要。本文以中英双语形式，系统讲解核心概念与高频考点。

1. Number Systems and Data Representation | 数制与数据表示

Microprocessors process binary data internally. However, to make binary values easier for humans to read and write, hexadecimal notation is widely used in assembly language programming and memory dump analysis. Each hexadecimal digit corresponds to exactly four binary bits, making conversion straightforward.

微处理器内部以二进制处理数据。然而，为了让二进制数值更易于人读写，十六进制在汇编语言编程和内存转储分析中被广泛使用。每个十六进制数字恰好对应四位二进制数，因此转换十分直接。

Decimal to binary: Repeatedly divide by 2 and record the remainders from bottom to top.
十进制转二进制：反复除以2，从下往上记录余数。
Binary to hexadecimal: Group bits in fours, starting from the binary point outward.
二进制转十六进制：从小数点向两侧每四位一组进行分组。

For signed numbers, the two’s complement representation is the most important concept. In two’s complement, the most significant bit (MSB) acts as the sign bit: 0 for positive and 1 for negative. To negate a number, invert all bits and add 1.

对于有符号数，补码是最重要的概念。在补码中，最高有效位用作符号位：0为正，1为负。对某数取负的方法是：按位取反后加1。

−N = (NOT N) + 1

For an n-bit two’s complement number, the representable range is from −2ⁿ⁻¹ to +2ⁿ⁻¹ − 1. For example, an 8-bit value can represent −128 to +127. Note that an overflow occurs when the result of an arithmetic operation exceeds this range.

对于n位补码数，可表示范围为−2ⁿ⁻¹ 至 +2ⁿ⁻¹ − 1。例如，8位数可表示−128至+127。注意，当算术运算结果超过此范围时发生溢出。

2. 8086 Microprocessor Architecture | 8086微处理器结构

The Intel 8086 is a 16-bit microprocessor with a 20-bit address bus, enabling it to address 2²⁰ = 1 MB of memory. Its architecture is divided into two main units: the Bus Interface Unit (BIU) and the Execution Unit (EU).

Intel 8086是一款16位微处理器，具有20位地址总线，可寻址2²⁰ = 1 MB的内存。其结构分为两大单元：总线接口单元（BIU）和执行单元（EU）。

BIU: Responsible for fetching instructions, reading and writing memory operands, and managing the instruction queue. It contains segment registers, the instruction pointer (IP), and the address adder.
BIU（总线接口单元）：负责取指令、读写内存操作数和指令队列管理，包含段寄存器、指令指针（IP）和地址加法器。
EU: Responsible for decoding and executing instructions. It contains the ALU, general-purpose registers, the flag register, and control logic. The EU operates independently once an instruction is fetched.
EU（执行单元）：负责指令译码与执行，包含ALU、通用寄存器、标志寄存器和控制逻辑。指令取入后，EU独立运行。

The BIU and EU work in a pipeline fashion: while the EU executes the current instruction, the BIU fetches the next instruction into the queue. This overlapping improves overall system throughput without requiring an advanced superscalar design.

BIU与EU以流水线方式协同工作：EU执行当前指令时，BIU将下一条指令取入队列。这种重叠操作无需先进超标量设计即可提高系统整体吞吐量。

3. Register Organization | 寄存器组织

The 8086 contains 14 internal 16-bit registers, classified into four categories: data registers, pointer/index registers, segment registers, and the instruction pointer.

8086包含14个16位内部寄存器，分为四类：数据寄存器、指针/变址寄存器、段寄存器以及指令指针。

Category \| 类别	Registers \| 寄存器	Primary Function \| 主要功能
Data \| 数据	AX, BX, CX, DX	Arithmetic, logic, I/O operations; each byte-addressable (e.g., AH/AL)
Pointer/Index \| 指针/变址	SP, BP, SI, DI	Stack addressing, data transfer, string operations
Segment \| 段寄存器	CS, DS, SS, ES	Code, data, stack, extra segment base addresses
Instruction Pointer \| 指令指针	IP	Points to the next instruction to be executed within the code segment

The status flags in the flag register include CF (carry), PF (parity), AF (auxiliary carry), ZF (zero), SF (sign), and OF (overflow). Control flags include IF (interrupt enable), DF (direction), and TF (trap). Examinations frequently ask which flag is set or cleared after a specific arithmetic instruction.

标志寄存器中的状态标志包括CF（进位）、PF（奇偶）、AF（辅助进位）、ZF（零）、SF（符号）和OF（溢出）。控制标志包括IF（中断允许）、DF（方向）和TF（陷阱）。考试中常考查特定算术指令执行后哪些标志被置1或清零。

4. Memory Segmentation and Physical Address Calculation | 内存分段与物理地址计算

The 8086 uses a segmented memory model. A 20-bit physical address is generated by combining a 16-bit segment address and a 16-bit offset address. The fundamental formula is:

8086采用分段内存模型。20位物理地址由16位段地址和16位偏移地址组合生成。基本公式为：

Physical Address = Segment Base × 16 + Offset

物理地址 = 段基址 × 16 + 偏移地址

Segment values are shifted left by 4 bits (equivalent to multiplying by 16 in decimal) before addition.
段值在相加前左移4位（相当于十进制乘以16）。
For example, CS = 2000H and IP = 3412H produce the physical address 2000H × 10H + 3412H = 23412H.
例如，CS = 2000H，IP = 3412H，则物理地址 = 2000H × 10H + 3412H = 23412H。
Overlapping segments are allowed; two different logical addresses can map to the same physical address.
允许段重叠；两个不同的逻辑地址可以映射到同一个物理地址。

The four segment registers serve distinct purposes: CS defines the code segment, DS defines the default data segment, SS defines the stack segment, and ES provides an extra data segment for string operations. Default segment–offset pairing is a common exam question: for example, BP and SP default to SS, while SI and DI default to DS unless otherwise overridden with a segment override prefix.

四个段寄存器各司其职：CS定义代码段，DS定义默认数据段，SS定义堆栈段，ES为字符串操作提供附加数据段。默认段-偏移配对是常见考题：例如，BP和SP默认使用SS，而SI和DI默认使用DS，除非使用段覆盖前缀另行指定。

5. Addressing Modes | 寻址方式

Addressing modes define how the processor calculates the effective address of an operand. The 8086 supports a rich set of addressing modes, which can be broadly divided into data addressing modes and branch addressing modes.

寻址方式定义了处理器如何计算操作数的有效地址。8086支持丰富的寻址方式，大致可分为数据寻址方式和分支寻址方式。

Immediate addressing: The operand is part of the instruction itself. Example: MOV AX, 0100H.
立即寻址：操作数包含在指令本身中。示例：MOV AX, 0100H。
Register addressing: The operand is held in a register. Example: MOV AX, BX.
寄存器寻址：操作数存放在寄存器中。示例：MOV AX, BX。
Direct addressing: The instruction provides the 16-bit offset directly. Example: MOV AX, [2000H].
直接寻址：指令直接给出16位偏移地址。示例：MOV AX, [2000H]。
Register indirect addressing: The offset is held in SI, DI, BX, or BP. Example: MOV AX, [BX].
寄存器间接寻址：偏移地址存放在SI、DI、BX或BP中。示例：MOV AX, [BX]。
Based addressing: EA = base register (BX or BP) + displacement.
基址寻址：有效地址 EA = 基址寄存器（BX或BP）+ 位移量。
Indexed addressing: EA = index register (SI or DI) + displacement.
变址寻址：有效地址 EA = 变址寄存器（SI或DI）+ 位移量。
Based-indexed addressing: EA = base + index + displacement.
基址加变址寻址：有效地址 EA = 基址 + 变址 + 位移量。

Students should memorize which base register pairs with which segment by default, as mistakes here lead to incorrect physical addresses in both exams and real programs.

学生应牢记哪些基址寄存器默认配合哪个段寄存器，因为此处出错将导致考试和实际程序中的物理地址计算错误。

6. Instruction Set and Programming Essentials | 指令系统与编程要点

The 8086 instruction set includes data transfer, arithmetic, logic, shift/rotate, string, control transfer, and processor control instructions. Examination questions frequently ask learners to identify the addressing mode, the effect on flags, or the result of a short sequence of instructions.

8086指令系统包括数据传送、算术运算、逻辑运算、移位/循环、字符串、控制转移和处理器控制指令。考试题目常要求识别寻址方式、判断对标志位的影响，或分析短指令序列的执行结果。

MOV AX, 8000H
ADD AX, 8000H

After executing these two instructions, AX = 0000H, CF = 1, and OF = 1, because +32768 added to +32768 exceeds +32767, producing an overflow. ZF = 1 because the result is zero.

执行以上两条指令后，AX = 0000H，CF = 1，OF = 1，因为+32768加上+32768超过了+32767，产生溢出。ZF = 1，因为结果为零。

LEA vs MOV: LEA computes the effective address and loads it into a register; MOV transfers the value at that address.
LEA与MOV的区别：LEA计算有效地址并装入寄存器；MOV传送该地址处的值。
TEST instruction: Performs a logical AND but discards the result, updating flags only. It is commonly used for bit-testing with conditional jumps.
TEST指令：执行逻辑与但丢弃结果，仅更新标志位。常用于与条件跳转配合进行位测试。
CMP instruction: Subtracts operands without storing the result; flags reflect the comparison.
CMP指令：执行减法但不保存结果，仅通过标志反映比较结果。

Knowledge of the flag set and reset behavior after SUB, CMP, and ADD instructions is among the highest-yield topics in the exam.

掌握SUB、CMP和ADD指令后标志位的置位与复位行为，是考试中性价比最高的考点之一。

7. Stack Operations and Subroutine Calls | 堆栈操作与子程序调用

The stack is a last-in-first-out (LIFO) memory region pointed to by the stack pointer SP. In the 8086, the stack grows downward from high addresses to low addresses. When a word is pushed, SP is decremented by 2; when a word is popped, SP is incremented by 2.

堆栈是一种后进先出（LIFO）存储区域，由堆栈指针SP指向。在8086中，堆栈从高地址向低地址增长。压入一个字时，SP减2；弹出一个字时，SP加2。

PUSH AX: SP ← SP − 2; [SS : SP] ← AX.
PUSH AX（压栈）： SP ← SP − 2；[SS : SP] ← AX。
POP AX: AX ← [SS : SP]; SP ← SP + 2.
POP AX（弹栈）： AX ← [SS : SP]；SP ← SP + 2。

The CALL instruction pushes the current IP (and CS for far calls) onto the stack, then loads the subroutine’s entry address into IP. The RET instruction restores the address from the stack and returns control to the caller. Interrupt service routines use IRET, which additionally restores the flag register.

CALL指令将当前IP（远调用还需压入CS）压入堆栈，然后将子程序入口地址装入IP。RET指令从堆栈恢复地址并将控制返回调用者。中断服务程序使用IRET，额外恢复标志寄存器。

A common examination trap: the stack pointer should always be restored to its original value after a subroutine returns; otherwise, the stack will overflow or underflow on repeated calls. Pay attention to the order of POP instructions, which must reverse the order of PUSH instructions.

一个常见考试陷阱：子程序返回后，堆栈指针应恢复原值；否则多次调用后堆栈将上溢或下溢。注意POP指令的顺序必须与PUSH指令的顺序相反。

8. Interrupt System and Priority Management | 中断系统与优先级管理

An interrupt is an asynchronous event that temporarily suspends the main program so the processor can service a special routine. The 8086 supports two types of interrupts: hardware interrupts (maskable INTR and non-maskable NMI) and software interrupts (INT n instructions).

中断是一种异步事件，它暂时挂起主程序，使处理器能够执行特定服务程序。8086支持两类中断：硬件中断（可屏蔽INTR和不可屏蔽NMI）和软件中断（INT n指令）。

NMI: Triggered by a rising edge on the NMI pin; cannot be masked by IF. It is used for critical events such as power failure.
NMI（不可屏蔽中断）：由NMI引脚上升沿触发，无法通过IF屏蔽，用于电源故障等关键事件。
INTR: Level-triggered and maskable using IF. The processor responds by issuing two INTA cycles, during which an external device supplies an interrupt vector type.
INTR（可屏蔽中断）：电平触发且可通过IF屏蔽。处理器通过两个INTA周期响应，外部设备在此期间提供中断类型码。
INT n: A software instruction that directly specifies the interrupt vector type; it does not depend on IF.
INT n（软件中断）：一种直接在指令中指定中断类型码的软件指令，不受IF的影响。

The interrupt vector table in the 8086 resides at the first 1 KB of memory (addresses 00000H to 003FFH). Each of the 256 possible vectors occupies 4 bytes: the first two bytes store the IP, and the next two store the CS of the service routine. The formula is:

8086的中断向量表位于内存最低1 KB区域（地址00000H至003FFH）。256个可能的中断向量各占4字节：前两个字节存放服务程序的IP，后两个字节存放CS。计算公式为：

Vector Address = Interrupt Type × 4

向量地址 = 中断类型号 × 4

When an interrupt occurs, the 8086 first pushes the flag register, then clears IF and TF, then pushes CS and IP of the next instruction, and finally loads the new CS and IP from the vector table. This sequence is a classic long-answer question in exams.

中断发生时，8086首先压入标志寄存器，然后清除IF和TF，再压入下一条指令的CS和IP，最后从向量表中装入新的CS和IP。这一流程是考试中的经典论述题。

9. Timing and the Bus Cycle | 时序与总线周期

The microprocessor executes instructions by coordinating data transfers over the system bus, which consists of the address bus, data bus, and control bus. The basic units of timing are the clock cycle, bus cycle, and instruction cycle.

微处理器通过协调系统总线上的数据传输来执行指令，系统总线由地址总线、数据总线和控制总线组成。时间的基本单位包括时钟周期、总线周期和指令周期。

Clock cycle (T state): The smallest unit of time, determined by the oscillator frequency.
时钟周期（T状态）：由振荡器频率决定的最小时间单位。
Bus cycle: The time required to read or write one word/byte of data, typically four T states (T1 to T4).
总线周期：完成一次数据读写所需的时间，通常为四个T状态（T1至T4）。
Instruction cycle: The time required to fetch, decode, and execute one complete instruction; it contains one or more bus cycles.
指令周期：取指、译码并执行一条完整指令所需的时间，包含一个或多个总线周期。

In the T1 state, the 8086 sends the 20-bit physical address and a status signal ALE (address latch enable) to latch the address. During T2, the address bus is released and becomes the data bus for read/write transfers. This multiplexing of address and data lines is a hallmark of the 8086 design, and examinations often require students to explain why address latches are necessary.

在T1状态，8086输出20位物理地址和地址锁存允许信号ALE。在T2状态，地址总线释放并转变为数据总线用于读写传输。这种地址与数据线复用是8086设计的标志性特征，考试常要求学生解释为何需要地址锁存器。

10. Common Pitfalls and Exam Strategies | 常见易错点与应试策略

After reviewing many past papers, we have identified several recurring mistakes that students make in microcomputer principles exams. Avoiding these traps is just as important as understanding the underlying theory.

通过分析历年真题，我们总结出学生在微机原理考试中反复出现的几类错误。避免这些陷阱与理解基础理论同等重要。

Pitfall \| 易错点	Correct Understanding \| 正确理解
Confusing physical vs logical address	Physical = segment × 16 + offset; logical is the segment:offset pair
物理地址与逻辑地址混淆	物理地址 = 段 × 16 + 偏移；逻辑地址是段：偏移对
Forgetting the direction of stack growth	The 8086 stack grows downward; PUSH decrements SP by 2
忘记堆栈增长方向	8086堆栈向下增长；PUSH使SP减2
Incorrect flag changes after ADD/SUB	Always check CF for unsigned, OF for signed; ZF for zero
ADD/SUB后标志判断错误	无符号看CF，有符号看OF，零结果看ZF

For calculation problems, always write down the binary representation of every operand before performing arithmetic, especially when two’s complement negatives are involved. For programming questions, trace the state of registers and flags step by step in a table. This systematic approach prevents careless mistakes and makes your answer easy for examiners to mark.

对于计算题，在执行运算前务必写出每个操作数的二进制表示，特别是涉及补码负数时。对于编程题，用表格逐步追踪寄存器和标志位的状态。这种系统化方法既能防止粗心错误，也便于阅卷评分。

11. Summary of Key Formulas and Concepts | 关键公式与概念汇总

The following formulas appear repeatedly in examinations. Memorise them precisely and understand how each component relates to the underlying hardware.

以下公式在考试中反复出现。请精确记忆并理解每个组成部分与底层硬件的关系。

Physical address = Segment × 16 + Offset (covers all memory access in 8086)
物理地址 = 段基址 × 16 + 偏移地址（涵盖8086全部内存访问）
Vector address = Interrupt type × 4 (points to the entry in the interrupt vector table)
中断向量地址 = 中断类型号 × 4（指向中断向量表中的表项）
For n-bit two’s complement: range is −2ⁿ⁻¹ to +2ⁿ⁻¹ − 1
对于n位补码：范围为−2ⁿ⁻¹ 至 +2ⁿ⁻¹ − 1
Stack word push: SP ← SP − 2; word pop: SP ← SP + 2
压栈一个字：SP ← SP − 2；弹出一个字：SP ← SP + 2

Beyond memorisation, review worked examples from past paper questions. The most successful candidates draw an explicit diagram of the bus and register structure when answering architecture questions, then support each step of their reasoning with the relevant formula. This demonstrates both theoretical depth and practical problem-solving ability.

除记忆外，还要研习历年真题中的例题。最成功的考生在回答结构类题目时会画出总线和寄存器结构图，再用公式支撑每一步推理。这既展示了理论深度，也体现了实际解题能力。

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Microcomputer Principles: Key Difficulties Explained | 微机原理重难点解析