📚 CPU Exam Essentials for IB and Edexcel Computer Science | CPU 考点精讲 (IB & Edexcel 计算机)
The Central Processing Unit (CPU) is the brain of a computer, executing instructions and managing data. In both IB Computer Science and Edexcel Computer Science, understanding CPU architecture, operation, and performance factors is essential. This revision guide consolidates key concepts from both syllabi, highlights common examination focus areas, and provides bilingual explanations to strengthen your grasp of the topic.
中央处理器（CPU）是计算机的大脑，负责执行指令和处理数据。在 IB 计算机科学和 Edexcel 计算机科学课程中，理解 CPU 的架构、工作原理及性能影响因素至关重要。这份考点精讲整合了两套课程的核心概念，突出常考重点，并通过中英双语解释帮助你扎实掌握本专题。
1. Introduction to the CPU | CPU 简介
The CPU is a microprocessor chip that interprets and carries out the basic instructions required to operate a computer. It consists of millions—or billions—of transistors etched onto a silicon die. At its heart are the Arithmetic Logic Unit, Control Unit, and a set of registers. The CPU communicates with memory and input/output devices via system buses.
CPU 是一个微处理器芯片，负责解释并执行计算机运行所需的基本指令。它由蚀刻在硅片上的数百万乃至数十亿个晶体管构成。其核心部件包括算术逻辑单元、控制单元和一组寄存器。CPU 通过系统总线与内存及输入/输出设备通信。
In IB Computer Science, the CPU is studied under Topic 2 (Computer Architecture), while Edexcel specifications place it within ‘Hardware’ and ‘The Processor’. Both require you to describe the function and interaction of its components, and to evaluate how architecture choices impact performance.
在 IB 计算机科学中，CPU 归属于主题 2（计算机组成），而 Edexcel 课程将其安排在“硬件”与“处理器”部分。两者都要求你能描述各部件的功能及相互作用，并能评估架构选择对性能的影响。
2. Von Neumann vs. Harvard Architecture | 冯·诺依曼与哈佛架构
The Von Neumann architecture uses a single shared memory space for both instructions and data, with one set of buses. This simplicity makes it cost-effective, but it suffers from the “Von Neumann bottleneck” because the CPU must fetch instructions and data sequentially over the same bus, limiting throughput.
冯·诺依曼架构使用单一共享存储空间来存放指令和数据，并只有一组总线。其简单性降低了成本，但也带来了“冯·诺依曼瓶颈”——CPU 必须通过同一条总线依次获取指令和数据，限制了吞吐量。
Harvard architecture, in contrast, has physically separate memory and buses for instructions and data. This allows simultaneous access to both, improving speed. It is commonly found in microcontrollers and digital signal processors. IB and Edexcel exams may ask you to compare these two and identify which is used in typical desktop CPUs (Von Neumann).
相比之下，哈佛架构拥有物理上独立的指令存储器和数据存储器，以及各自的总线。这使得同时访问指令和数据成为可能，从而提升了速度。它常用于微控制器和数字信号处理器。IB 和 Edexcel 考试可能会要求对比这两种架构，并识别典型台式机 CPU 采用的是哪一种（冯·诺依曼）。
3. CPU Components: ALU, Control Unit, Registers | CPU 组成：ALU、控制单元、寄存器
The Arithmetic Logic Unit (ALU) performs arithmetic operations (addition, subtraction) and logical operations (AND, OR, NOT). It receives operands from registers, processes them, and stores the result back. The ALU is purely combinational logic with no memory.
算术逻辑单元（ALU）执行算术运算（加、减）和逻辑运算（与、或、非）。它从寄存器获取操作数，处理后把结果存回。ALU 是无记忆功能的纯组合逻辑电路。
The Control Unit (CU) directs the operation of the processor. It decodes instructions, generates timing and control signals, and coordinates data movement between memory, ALU, and I/O devices. In a typical cycle, the CU orchestrates the fetch, decode, and execute steps.
控制单元（CU）指挥处理器的运作。它译码指令，产生时序和控制信号，并协调内存、ALU 及 I/O 设备之间的数据传送。在一个典型周期中，控制单元掌控取指、译码和执行各步骤。
Registers are small, high-speed storage locations inside the CPU. Key registers include the Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), Current Instruction Register (CIR), and Accumulator (ACC). Their roles are examined in detail in both syllabi.
寄存器是 CPU 内部的小型高速存储单元。关键寄存器包括程序计数器（PC）、内存地址寄存器（MAR）、内存数据寄存器（MDR）、当前指令寄存器（CIR）和累加器（ACC）。两套大纲都会细致考查它们的作用。
4. The Fetch-Decode-Execute Cycle | 取指-解码-执行周期
The fetch-decode-execute cycle is the fundamental sequence by which the CPU processes each instruction. In IB and Edexcel exams, you are frequently required to describe this cycle step by step, including the specific registers involved at each stage.
取指-解码-执行周期是 CPU 处理每条指令的基本流程。IB 和 Edexcel 考试经常要求你逐步描述该周期，包括每一阶段涉及的具体寄存器。
Fetch: The address in the PC is copied to the MAR, the CU sends a read signal on the control bus, and the instruction at that memory address is loaded into the MDR, then transferred to the CIR. The PC is incremented to point to the next instruction.
取指：PC 中的地址复制到 MAR，控制单元在控制总线上发出读信号，该内存地址处的指令被加载到 MDR，然后传送到 CIR。PC 自动递增以指向下一条指令。
Decode: The Control Unit interprets the bit pattern in the CIR, splitting it into opcode and operand(s). It decides what control signals are needed for the execution phase.
译码：控制单元解释 CIR 中的位模式，将其分为操作码和操作数，并决定执行阶段需要哪些控制信号。
Execute: The ALU performs the required operation—arithmetic, logic, or data movement. If data needs to be fetched from memory, the MAR/MDR cycle is repeated for the operand address. The result is stored in a register or sent to memory via the MDR.
执行：ALU 完成所需的运算——算术、逻辑或数据传送。如果需要从内存取操作数，则将操作数地址通过 MAR/MDR 再次执行内存访问。结果存入寄存器或通过 MDR 发送到内存。
5. Key Registers and Their Roles | 主要寄存器及其作用
Program Counter (PC): Holds the address of the next instruction to fetch. It automatically increments (or changes on a jump) to sequence through programs.
程序计数器（PC）：存放下一条要取出的指令的地址。它会自动递增（或发生跳转时更改），使程序顺序执行。
Memory Address Register (MAR): Contains the address of the memory location to be read from or written to. It connects directly to the address bus.
内存地址寄存器（MAR）：含待读取或写入的内存单元地址。它直接连接到地址总线。
Memory Data Register (MDR): Temporarily stores data being transferred to or from main memory. It acts as a buffer between the CPU and memory.
内存数据寄存器（MDR）：暂存向主存传送或从主存取出的数据。它充当 CPU 和内存之间的缓冲。
Current Instruction Register (CIR): Holds the instruction currently being decoded and executed. The CU reads from this register during the decode phase.
当前指令寄存器（CIR）：存放当前正在译码和执行的指令。译码阶段控制单元从该寄存器读取。
Accumulator (ACC): A general-purpose register that temporarily holds ALU results. Many instructions implicitly use the accumulator as both source and destination.
累加器（ACC）：用于暂存 ALU 运算结果的通用寄存器。许多指令都隐式地将累加器同时作为源和目的操作数。
Index Register (IX): Used for indexed addressing; common in IB HL. The CPU adds the contents of IX to an operand to form an effective address, aiding array access.
变址寄存器（IX）：用于变址寻址，常见于 IB HL。CPU 将 IX 的内容与操作数相加得到有效地址，便于访问数组。
6. Factors Affecting CPU Performance | 影响 CPU 性能的因素
Clock speed, measured in GHz, determines how many cycles per second the CPU can execute. A higher clock speed means more instructions can be processed per unit time, but it increases power consumption and heat generation. IB and Edexcel questions often ask for the relationship: Execution time = Number of instructions × CPI / Clock rate.
时钟速度以 GHz 为单位，决定 CPU 每秒可执行的周期数。时钟速度越高，单位时间内可处理指令越多，但也导致功耗和发热增加。IB 和 Edexcel 试题常要求阐述关系：执行时间 = 指令数 × 每指令周期数 / 时钟频率。
Number of cores: Modern CPUs have multiple independent processing units (cores) on one chip, allowing parallel execution of threads. A dual-core processor can simultaneously run two threads, but not all tasks can be parallelised. Amdahl’s Law limits the speedup from additional cores.
核心数：现代 CPU 在一个芯片上包含多个独立的处理单元（核心），允许并行执行线程。双核处理器可同时运行两个线程，但并非所有任务都能并行化。阿姆达尔定律限制了增加核心带来的加速比。
Cache memory: A small amount of very fast memory located on or near the CPU. Levels L1, L2, and L3 differ in size and speed. A larger cache reduces the average memory access time, improving performance. IB HL covers cache mapping techniques (direct, associative).
高速缓存：位于 CPU 内部或附近的小容量极速内存。L1、L2 和 L3 缓存大小和速度各异。更大的缓存可降低平均内存访问时间，从而提升性能。IB HL 还涉及缓存映射方式（直接、组相联）。
Word size: The number of bits the CPU can handle in one go. A 64-bit CPU can process larger numbers and address more memory directly compared to a 32-bit processor, enhancing throughput for certain applications.
字长：CPU 一次能处理的位数。与 32 位处理器相比，64 位 CPU 能处理更大的数值并直接寻址更多内存，对某些应用可提高吞吐量。
7. The System Bus: Data, Address, and Control | 系统总线：数据、地址和控制总线
The system bus consists of three sets of parallel wires connecting the CPU to memory and I/O controllers. The address bus carries the memory address from the CPU; its width determines the maximum addressable memory (e.g., 32 lines give 2³² addresses). The data bus transfers the actual data; its width dictates how many bits can be moved simultaneously. The control bus carries command signals like read/write, clock, and interrupt requests.
系统总线由三组并行导线构成，连接 CPU 与内存及 I/O 控制器。地址总线传输来自 CPU 的内存地址；其宽度决定最大可寻址空间（如 32 条线给出 2³² 个地址）。数据总线传输实际数据；其宽度决定一次能移动多少位。控制总线承载读写、时钟、中断请求等命令信号。
Edexcel exams frequently ask you to explain how bus widths affect system performance. A wider data bus increases bandwidth; a wider address bus allows more RAM to be installed without bank switching.
Edexcel 考试常要求解释总线宽度如何影响系统性能。更宽的数据总线可增加带宽；更宽的地址总线允许安装更大内存而无需 bank switching。
8. Pipelining and Parallel Processing (IB HL) | 流水线与并行处理（IB HL）
Pipelining is a technique that overlaps the execution of multiple instructions. The CPU divides the instruction cycle into stages (fetch, decode, execute, write-back) so that while one instruction is being decoded, the next can be fetched. This improves instruction throughput without increasing clock speed.
流水线是一种重叠执行多条指令的技术。CPU 将指令周期划分为多个阶段（取指、译码、执行、写回），这样在一条指令译码的同时，下一条指令已在取指。这能提高指令吞吐量而无需提高时钟频率。
However, pipeline hazards—structural, data, and control—can cause stalls. IB HL expects you to identify these hazards and discuss solutions such as forwarding, branch prediction, and pipeline interlocking. Edexcel A-Level also touches on pipelining at a basic level.
然而，流水线可能出现结构冒险、数据冒险和控制冒险，导致流水线停顿。IB HL 要求你识别这些冒险并讨论解决方法，如前推、分支预测和流水线互锁。Edexcel A-Level 也浅涉流水线基础。
Superscalar architectures go further by having multiple execution pipes, allowing more than one instruction to complete per clock cycle. These are typical in high-end CPUs and require complex instruction scheduling.
超标量架构更进一步，拥有多条执行流水线，使得每个时钟周期可以完成多条指令。这常见于高端 CPU，需要复杂的指令调度。
9. RISC vs. CISC Architectures | RISC 与 CISC 架构
RISC (Reduced Instruction Set Computer) emphasises a small, highly optimised set of simple instructions, each executing in one clock cycle. RISC processors use load/store architecture and rely on compilers for efficient code. Examples include ARM (used in mobile devices) and older MIPS.
RISC（精简指令集计算机）强调一套小型、高度优化的简单指令，每条指令通常在一个时钟周期内完成。RISC 处理器采用加载/存储架构，并依赖编译器生成高效代码。典型例子有 ARM（用于移动设备）和老式 MIPS。
CISC (Complex Instruction Set Computer) offers a rich set of instructions, some of which perform complex tasks in one instruction, often taking multiple cycles. x86 processors from Intel and AMD are CISC-based. The complexity reduces code size but makes pipelining harder.
CISC（复杂指令集计算机）提供丰富的指令集，有些指令可以在一条指令中完成复杂任务，常需多个周期。Intel 和 AMD 的 x86 处理器基于 CISC。其复杂性减少了代码量，但增加了流水线实现的难度。
Both IB and Edexcel syllabi require comparison of RISC and CISC in terms of instruction complexity, compiler complexity, power consumption, and processor design. Modern CPUs often use hybrid approaches (RISC core with CISC decoder).
IB 和 Edexcel 大纲都要求对比 RISC 与 CISC 在指令复杂度、编译器复杂度、功耗和处理器设计方面的差异。现代 CPU 常采用混合策略（CISC 译码器配合 RISC 核心）。
10. Interrupts and Their Handling | 中断及其处理
An interrupt is a signal that causes the CPU to suspend its current program and execute an Interrupt Service Routine (ISR). Hardware interrupts come from I/O devices; software interrupts are triggered by instructions or error conditions. Interrupts enable efficient I/O and multitasking.
中断是一种让 CPU 暂停当前程序并执行中断服务程序（ISR）的信号。硬件中断来自 I/O 设备，软件中断由指令或错误条件触发。中断机制支持高效的 I/O 和多任务处理。
When an interrupt occurs, the CPU completes the current instruction, saves the PC and other registers onto the stack, and loads the address of the ISR from the interrupt vector table. After servicing, it restores the context and resumes the original program.
当中断发生时，CPU 完成当前指令，将 PC 和其他寄存器的值压栈，然后从中断向量表加载 ISR 的地址。中断处理完毕后，恢复现场并继续执行原程序。
Edexcel focuses on the basic interrupt cycle; IB also examines priority levels, nesting, and the role of the operating system in managing interrupts. In both, you should be able to explain how interrupts improve CPU utilisation.
Edexcel 侧重于基本中断周期；IB 还会考查中断优先级、嵌套及操作系统在中断管理中的作用。不论哪种课程，你都需要能解释中断如何提高 CPU 利用率。
11. CPU Performance Metrics: MIPS, FLOPS, etc. | CPU 性能指标：MIPS、FLOPS 等
MIPS (Millions of Instructions Per Second) measures how many machine instructions a CPU can execute in one second. However, it depends heavily on the instruction set; a simple RISC instruction and a complex CISC instruction are not equivalent. Therefore, MIPS is often considered a crude metric.
MIPS（每秒百万条指令）用于衡量 CPU 一秒钟可执行的机器指令数。但这个指标高度依赖指令集——一条简单的 RISC 指令和一条复杂的 CISC 指令并不等价，因此 MIPS 常被视为粗略指标。
FLOPS (Floating-Point Operations Per Second) is used for scientific and graphics applications. Today, we talk in GFLOPS or TFLOPS. Benchmark suites (SPEC, Geekbench) provide standardised workloads to compare real-world performance. IB and Edexcel may ask you to evaluate the suitability of these metrics.
FLOPS（每秒浮点运算次数）用于科学计算和图形应用；现今常用 GFLOPS 或 TFLOPS。基准测试套件（如 SPEC、Geekbench）提供标准化工作负载以比较实际性能。IB 和 Edexcel 可能要求你评估这些指标的适用性。
Understanding that CPU performance is a combination of clock frequency, IPC (Instructions Per Cycle), and core count helps justify why raw GHz comparisons can be misleading. Always relate metrics to the type of workload.
明确 CPU 性能是时钟频率、IPC（每周期指令数）和核心数的综合体现，有助于解释为何单纯的 GHz 对比并不准确。始终应将指标与工作负载类型联系起来。
12. Exam Tips and Common Pitfalls | 考试技巧与常见错误
When describing the fetch-decode-execute cycle, avoid vague terms. Use the exact register names (PC, MAR, MDR, CIR) and sequence the steps precisely. Diagrams can support your answer, but labels and explanation are essential.
描述取指-解码-执行周期时，避免模糊用语。使用准确保存器名称（PC、MAR、MDR、CIR）并精确排序。图示可以辅助，但标注和解释必不可少。
Do not confuse bus types: the address bus is unidirectional (CPU → memory); data bus is bidirectional; control bus carries individual signals. A common mistake is misstating the direction of buses.
不要混淆总线类型：地址总线是单向的（CPU→内存）；数据总线是双向的；控制总线承载各个信号。常见错误是弄错总线方向。
For performance questions, always consider multiple factors and their trade-offs. Saying ‘higher clock speed = faster’ is insufficient; discuss heat, power, and diminishing returns. For parallelisation, mention Amdahl’s Law or the sequential portions of code.
回答性能问题时，务必考虑多个因素及其权衡。只说“时钟速度越高越快”是不够的；要讨论发热、功耗和边际收益。涉及并行化时，应提及阿姆达尔定律或代码中的顺序部分。
In evaluation questions, relate technical terms to real-world scenarios—e.g., a quad-core CPU benefits video editing but not single-threaded spreadsheets. The IB expects this contextual understanding.
在评价题中，将专业术语与实际场景联系起来——例如，四核 CPU 有利于视频编辑，但无助于单线程电子表格。IB 期望你具备这种情境理解能力。
Finally, practice past papers from both IB and Edexcel. The wording may differ, but the core concepts are identical. Familiarity with command terms (describe, explain, evaluate) will maximise your marks.
最后，多加练习 IB 和 Edexcel 历年试题。措辞或有不同，但核心概念一致。熟悉指令动词（描述、解释、评价）可以帮你拿到更高分数。
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