GCSE WJEC Computer Science: Logic Gates Revision Notes | GCSE WJEC 计算机:逻辑门 考点精讲

📚 GCSE WJEC Computer Science: Logic Gates Revision Notes | GCSE WJEC 计算机:逻辑门 考点精讲

Logic gates are the fundamental building blocks of digital circuits. In GCSE WJEC Computer Science, you need to understand the function, truth table, and Boolean expression for each type of gate, as well as how to combine them to create more complex circuits. This article provides comprehensive revision notes to help you master logic gates for the exam.

逻辑门是数字电路的基本构建模块。在 GCSE WJEC 计算机科学中,你需要理解每种逻辑门的功能、真值表和布尔表达式,以及如何将它们组合起来创建更复杂的电路。本文提供全面的考点精讲,帮助你掌握逻辑门知识,从容应对考试。

1. Introduction to Logic Gates | 逻辑门简介

A logic gate is an electronic component that takes one or more binary inputs and produces a single binary output based on a logical rule.

逻辑门是一种电子元件,它接收一个或多个二进制输入,并根据逻辑规则产生一个二进制输出。

The inputs and outputs are represented by voltage levels, where a high voltage typically represents a logic ‘1’ (TRUE) and a low voltage represents a logic ‘0’ (FALSE).

输入和输出由电压水平表示,通常高电压表示逻辑“1”(真),低电压表示逻辑“0”(假)。

In GCSE WJEC, logic gates are studied using Boolean algebra and truth tables to describe their behaviour.

在 GCSE WJEC 课程中,我们使用布尔代数和真值表来描述逻辑门的行为。

There are several basic logic gates: AND, OR, NOT, NAND, NOR, and XOR. Each has its own symbol, truth table, and Boolean expression.

基本逻辑门包括:与门、或门、非门、与非门、或非门和异或门。每一种都有各自的符号、真值表和布尔表达式。


2. The AND Gate | 与门

The AND gate has two or more inputs. It outputs 1 only when all inputs are 1; otherwise, the output is 0.

与门有两个或更多输入。仅当所有输入均为 1 时,输出才为 1;否则输出为 0。

The Boolean expression for a 2-input AND gate is Q = A·B. The dot (·) represents the AND operation.

二输入与门的布尔表达式为 Q = A·B。点号 (·) 表示与运算。

Q = A·B

The AND gate symbol is a D-shaped outline with two input wires on the left and a single output on the right. In some textbooks, it is drawn as a semi-ellipse with a flat left side.

与门的符号是一个 D 形轮廓,左侧有两根输入线,右侧有一个输出。在某些教材中,它被画成一个左平右圆的半椭圆形。

Truth table for a 2-input AND gate:

二输入与门真值表:

A B Output (Q)
0 0 0
0 1 0
1 0 0
1 1 1

When connecting multiple AND gates, the idea of ‘all high gives high’ remains valid. For three inputs A, B, and C, the output is 1 only if A=1, B=1, and C=1.

当连接多个与门时,“全高出高”的原则仍然成立。对于三个输入 A、B 和 C,仅当 A=1、B=1 且 C=1 时,输出才为 1。


3. The OR Gate | 或门

The OR gate outputs 1 if at least one of its inputs is 1. It only outputs 0 when all inputs are 0.

或门只要至少有一个输入为 1,就输出 1。仅当所有输入均为 0 时,才输出 0。

For a 2-input OR gate, the Boolean expression is Q = A+B. The plus sign represents logical OR.

对于二输入或门,布尔表达式为 Q = A+B。加号表示逻辑或运算。

Q = A+B

The OR gate symbol is shaped like a shield or a curved wedge, with inputs on the left and the output on the pointed right side.

或门的符号形状像一个盾牌或弯曲的楔形,输入在左侧,输出在尖形的右侧。

Truth table:

真值表:

A B Output (Q)
0 0 0
0 1 1
1 0 1
1 1 1

An OR gate with three inputs works in the same way: if any input is 1, the output is 1.

三输入或门的工作方式相同:只要任一输入为 1,输出即为 1。


4. The NOT Gate | 非门

The NOT gate, also called an inverter, has only one input. It outputs the inverse of the input: if the input is 1, the output is 0, and vice versa.

非门,也称为反相器,只有一个输入。它输出输入的反相:如果输入为 1,输出为 0,反之亦然。

Its Boolean expression is Q = ¬A (sometimes written as A’ or /A). The symbol ¬ represents NOT.

其布尔表达式为 Q = ¬A(有时写作 A’ 或 /A)。符号 ¬ 表示非运算。

Q = ¬A

The NOT gate symbol is a triangle followed by a small circle (bubble) at the output. The bubble indicates inversion.

非门符号是一个三角形,输出端带有一个小圆圈(气泡)。这个气泡表示反相。

Truth table:

真值表:

A Output (Q)
0 1
1 0

NOT gates are essential for creating complemented terms in Boolean expressions, such as ¬A in a product term.

非门对于在布尔表达式中创建取反项至关重要,例如在乘积项中的 ¬A。


5. The NAND Gate | 与非门

The NAND gate is equivalent to an AND gate followed by a NOT gate. It outputs 0 only when all inputs are 1; otherwise, it outputs 1.

与非门等价于一个与门和一个非门串联。仅当所有输入均为 1 时输出 0,其他情况输出 1。

The Boolean expression is Q = ¬(A·B). You can also think of it as the complement of the AND function.

布尔表达式为 Q = ¬(A·B)。你也可以将其视为与函数的补。

The NAND gate symbol is the same D-shape as AND but with a small bubble at the output, indicating negation.

与非门符号的形状与与门相同,但输出端带有一个小圆圈,表示取反。

Truth table:

真值表:

A B Output (Q)
0 0 1
0 1 1
1 0 1
1 1 0

A NAND gate is called a universal gate because you can build any other logic function using only NAND gates.

与非门被称为通用门,因为你可以仅用与非门构建任何其他逻辑功能。


6. The NOR Gate | 或非门

The NOR gate is an OR gate followed by a NOT gate. It outputs 1 only when all inputs are 0; if any input is 1, the output is 0.

或非门是一个或门后接一个非门。仅当所有输入均为 0 时输出 1;如果任一输入为 1,输出则为 0。

Its Boolean expression is Q = ¬(A+B). The circle at the output of the symbol shows the inversion.

其布尔表达式为 Q = ¬(A+B)。符号输出端的小圆圈表示取反。

The NOR gate symbol is the OR shield shape with a bubble at the output.

或非门的符号是或门的盾形,并在输出端加有一个小圆圈。

Truth table:

真值表:

A B Output (Q)
0 0 1
0 1 0
1 0 0
1 1 0

NOR gates are also universal, meaning any Boolean function can be implemented using only NOR gates.

或非门同样是通用门,这意味着任何布尔函数都可以仅用或非门来实现。


7. The XOR Gate | 异或门

The exclusive-OR (XOR) gate outputs 1 when the number of 1s on its inputs is odd. For a 2-input XOR, it outputs 1 when the inputs are different, and 0 when they are the same.

异或门(XOR)在输入中 1 的个数为奇数时输出 1。对于二输入异或门,当两个输入不同时输出 1,相同时输出 0。

Boolean expression: Q = A ⊕ B. This can also be written as Q = (¬A·B) + (A·¬B).

布尔表达式:Q = A ⊕ B。也可以写作 Q = (¬A·B) + (A·¬B)。

Q = A ⊕ B

The XOR gate symbol is like an OR gate but with an extra curved line on the input side. There is no bubble at the output unless it is an XNOR gate.

异或门符号形似或门,但在输入侧多了一条弧线。输出端没有小圆圈,除非是异或非门(XNOR)。

Truth table:

真值表:

A B Output (Q)
0 0 0
0 1 1
1 0 1
1 1 0

XOR gates are used in arithmetic circuits, such as half adders and full adders, because they model binary addition without the carry.

异或门用于算术电路,如半加器和全加器,因为它们模拟了不考虑进位的二进制加法。


8. Truth Tables and Boolean Expressions | 真值表与布尔表达式

A truth table lists all possible input combinations and the corresponding output for a logic circuit. The number of rows is 2ⁿ, where n is the number of inputs.

真值表列出了逻辑电路所有可能的输入组合及对应的输出。行数为 2ⁿ,其中 n 是输入个数。

You can derive a Boolean expression from a truth table by writing the sum of products (SOP). For each row where output is 1, create a product term where an input is taken as its true form if it is 1, or complemented if it is 0. Then all these products are OR-ed together.

你可以通过写出积之和(SOP)从真值表推导布尔表达式。对于输出为 1 的每一行,生成一个乘积项:

Published by TutorHao | GCSE Computer Science Revision Series | aleveler.com

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