📚 IGCSE CIE Computer Science: Logic Gates Exam Focus | IGCSE CIE 计算机：逻辑门 考点精讲
Logic gates form the foundation of digital electronics and computer systems. In IGCSE CIE Computer Science (0478), you must recognise standard symbols, write truth tables, analyse simple circuits, and understand how gates combine to perform useful operations. This article unpacks every essential concept, from the basic NOT gate to half and full adders, so you can tackle exam questions with confidence.
逻辑门是数字电子学和计算机系统的基础。在 IGCSE CIE 计算机科学（0478）中，你需要识别标准符号、写出真值表、分析简单电路，并理解门如何组合以执行有用的操作。本文梳理了从基础的非门到半加器和全加器的每个重要概念，帮助你自信应对考试题目。
1. Introduction to Logic Gates | 逻辑门简介
A logic gate is an electronic component that produces a single binary output based on one or more binary inputs. The inputs and output are always either logic 0 (low voltage, false) or logic 1 (high voltage, true). By combining different gates, we can build circuits that perform arithmetic, make decisions, and store data.
逻辑门是一种电子元件，它根据一个或多个二进制输入产生一个二进制输出。输入和输出总是逻辑 0（低电压、假）或逻辑 1（高电压、真）。通过组合不同的门，我们可以构建执行算术运算、作出决策和存储数据的电路。
In CIE examinations, you need to draw and interpret logic circuits using the standard symbols, write Boolean expressions, and predict outputs for given inputs. Symbols follow the rectangle shape with a characteristic curve for OR-type gates and a straight back for AND-type gates, with a small circle indicating inversion (NOT).
在 CIE 考试中，你需要使用标准符号绘制和解释逻辑电路，写出布尔表达式，并根据给定输入预测输出。符号采用矩形形状，或门类型的门有特征曲线，与门类型的门为直背，小圆圈表示取反（非）。
2. The NOT Gate | 非门
The NOT gate, also called an inverter, has a single input and one output. It reverses the logic level: if input A is 0, output Q becomes 1; if A is 1, Q becomes 0.
非门也称为反相器，只有一个输入和一个输出。它反转逻辑电平：如果输入 A 为 0，输出 Q 为 1；如果 A 为 1，Q 为 0。
Q = A’
The Boolean expression uses a prime or an overbar; here we use A’. The truth table is:
布尔表达式使用撇号或上划线；这里我们使用 A’。真值表如下：
| A | Q = A’ |
|---|---|
| 0 | 1 |
| 1 | 0 |
In a circuit diagram, the NOT gate is a triangle followed by a small bubble. Exam tip: never forget the bubble, because omitting it turns a NOT into a buffer (which would just pass the input unchanged).
在电路图中，非门是一个三角形后跟一个小圆圈。考试提示：永远不要忘记圆圈，因为省略它会把非门变成缓冲器（直接传递输入不改变）。
3. The AND Gate | 与门
The AND gate gives output 1 only when all inputs are 1. For a two-input AND gate, Q = A AND B. The Boolean expression can be written as:
与门仅在所有输入都为 1 时输出 1。对于双输入与门，Q = A 与 B。布尔表达式可写作：
Q = A · B
Truth table for two inputs:
双输入真值表：
| A | B | Q = A · B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
The AND operation is analogous to multiplication in binary: 0·0=0, 0·1=0, 1·1=1. In a digital lock, an AND gate can be used to require two conditions to be true before unlocking.
与运算类似于二进制乘法：0·0=0，0·1=0，1·1=1。在数字锁中，与门可用于要求两个条件同时为真才能开锁。
4. The OR Gate | 或门
The OR gate outputs 1 if at least one input is 1. For inputs A and B, the Boolean expression is:
或门只要至少一个输入为 1 就输出 1。对于输入 A 和 B，布尔表达式为：
Q = A + B
Truth table:
真值表：
| A | B | Q = A + B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
OR can be thought of as logical addition (0+0=0, 0+1=1, 1+0=1, 1+1=1). However, note that in Boolean algebra 1+1 still equals 1, not 10. An alarm system might use an OR gate to trigger when any one of several sensors is activated.
或运算可视为逻辑加法（0+0=0，0+1=1，1+0=1，1+1=1）。但请注意，在布尔代数中 1+1 仍然等于 1，而不是 10。报警系统可以使用或门，在多个传感器中的任何一个被触发时发出警报。
5. The NAND Gate | 与非门
A NAND gate is an AND gate followed by a NOT gate. Its output is the opposite of the AND output: it gives 1 unless all inputs are 1. The Boolean expression is:
与非门是与门后接非门。其输出是与门输出的相反：除非所有输入都为 1，否则输出 1。布尔表达式为：
Q = (A · B)’
Truth table:
真值表：
| A | B | Q = (A · B)’ |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The NAND gate is special because it is a universal gate – any logic function can be built using only NAND gates. On a circuit symbol, an AND gate shape has a small bubble at its output.
与非门很特殊，因为它是一个通用门——任何逻辑函数都可以只用与非门构建。在电路符号上，与门形状的输出端有一个小圆圈。
6. The NOR Gate | 或非门
The NOR gate is an OR gate followed by a NOT. It outputs 1 only when all inputs are 0. The Boolean expression is:
或非门是或门后接非门。仅当所有输入为 0 时输出 1。布尔表达式为：
Q = (A + B)’
Truth table:
真值表：
| A | B | Q = (A + B)’ |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
Like NAND, NOR is also a universal gate. Its symbol resembles an OR gate with a bubble at the output. In a security system, a NOR gate might activate an alarm only when no sensors are tripped – useful for testing a ‘quiet’ state.
与与非门一样，或非门也是通用门。其符号类似或门，输出端有一个小圆圈。在安全系统中，或非门可以仅在没有任何传感器被触发时激活警报——这对于检测“安静”状态很有用。
7. The XOR Gate | 异或门
The exclusive-OR (XOR) gate outputs 1 when an odd number of inputs are 1. For two inputs, it gives 1 if the inputs are different. Boolean expression:
异或门（XOR）在输入中有奇数个 1 时输出 1。对于两个输入，当输入不同时输出 1。布尔表达式：
Q = A ⊕ B
Q = A · B’ + A’ · B
Truth table:
真值表：
| A | B | Q = A ⊕ B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
XOR is used extensively in arithmetic circuits, especially adders, because it mimics binary addition ignoring the carry. The XOR symbol is like an OR gate with an extra curved line at the inputs.
异或门广泛用于算术电路，尤其是加法器，因为它模拟二进制加法而忽略进位。异或符号类似或门，但在输入端多了一条曲线。
8. The XNOR Gate | 同或门
The exclusive-NOR (XNOR) gate is the complement of XOR – it outputs 1 when the inputs are identical. Boolean expression:
同或门（XNOR）是异或门的补——当输入相同时输出 1。布尔表达式：
Q = (A ⊕ B)’
Q = A · B + A’ · B’
Truth table:
真值表：
| A | B | Q = (A ⊕ B)’ |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
XNOR is sometimes called the equality gate because it checks whether two bits are equal. In CIE exams, you may see it in comparator circuits or as part of a parity checker.
同或门有时称为相等门，因为它检查两个位是否相等。在 CIE 考试中，你可能会在比较器电路或奇偶校验器中看到它。
9. Combining Logic Gates and Circuit Analysis | 组合逻辑门与电路分析
Real digital systems connect multiple gates to create more complex behaviours. When analysing a logic circuit, always label each intermediate connection with its Boolean expression, working from inputs toward the final output.
真正的数字系统连接多个门以创造更复杂的行为。分析逻辑电路时，始终用布尔表达式标记每个中间连接，从输入向最终输出逐步推导。
For example, consider a circuit: A and B feed into an AND gate producing A·B; this and input C go into an OR gate, giving final Q = (A·B) + C. To complete the truth table, list all input combinations and calculate each intermediate column before the output column.
例如，考虑一个电路：A 和 B 进入一个与门产生 A·B；该结果与输入 C 进入一个或门，最终 Q = (A·B) + C。要完成真值表，列出所有输入组合，并在得到输出列之前计算每个中间列。
Exam questions often provide a partially completed truth table or a circuit diagram and ask you to fill the missing values. Always double-check that you have considered all 2ⁿ rows for n inputs.
考试题目通常提供部分完成真值表或电路图，要求你填写缺失值。务必仔细检查你是否考虑了 n 个输入的所有 2ⁿ 行。
10. Universal Gates: NAND and NOR | 通用门：与非门和或非门
Both NAND and NOR are universal gates, meaning any logic function can be implemented using only one type of gate. This is economically important in manufacturing.
与非门和或非门都是通用门，意味着任何逻辑函数都可以仅用一种类型的门来实现。这在制造中具有重要的经济意义。
To build a NOT gate from a NAND gate, simply tie both inputs together: Q = (A · A)’ = A’. An AND gate can be made from two NANDs: first NAND gives (A·B)’, second NAND acts as NOT on that result. Similarly, an OR gate can be constructed using three NAND gates by applying De Morgan’s law.
用与非门构建非门，只需将两个输入连接在一起：Q = (A · A)’ = A’。与门可用两个与非门制作：第一个与非门给出 (A·B)’，第二个与非门对该结果取非。类似地，或门可通过使用三个与非门并应用德摩根定律来构建。
From NOR gates, a NOT gate is obtained by linking inputs: (A + A)’ = A’. An OR gate needs two NORs: first NOR gives (A+B)’, second NOR inverts it. NAND and NOR implementations are a favourite exam topic – you should be able to draw the equivalent circuit using only the specified universal gate.
从或非门，将输入相连可得到非门：(A + A)’ = A’。或门需要两个或非门：第一个或非门给出 (A+B)’，第二个或非门将其反转。与非门和或非门的实现是考试中的常见题目——你应该能够仅使用指定的通用门画出等效电路。
11. Logic Simplification with Boolean Algebra | 布尔代数逻辑简化
Simplifying Boolean expressions reduces the number of gates, making circuits cheaper and faster. Key rules include:
简化布尔表达式可减少门的数量，使电路更便宜、更快。关键规则包括：
- Identity: A + 0 = A, A · 1 = A
- Null: A + 1 = 1, A · 0 = 0
- Idempotent: A + A = A, A · A = A
- Complement: A + A’ = 1, A · A’ = 0
- Distributive: A·(B+C) = A·B + A·C, A+(B·C) = (A+B)·(A+C)
- De Morgan’s: (A·B)’ = A’ + B’, (A+B)’ = A’ · B’
身份律：A + 0 = A，A · 1 = A
零律：A + 1 = 1，A · 0 = 0
幂等律：A + A = A，A · A = A
互补律：A + A’ = 1，A · A’ = 0
分配律：A·(B+C) = A·B + A·C，A+(B·C) = (A+B)·(A+C)
德摩根定律：(A·B)’ = A’ + B’，(A+B)’ = A’ · B’
De Morgan’s laws are essential for converting between AND/OR forms and NAND/NOR implementations. For example, a NAND gate (A·B)’ is equivalent to A’ + B’ expressed with OR and NOT gates.
德摩根定律对于在 AND/OR 形式与 NAND/NOR 实现之间转换至关重要。例如，与非门 (A·B)’ 相当于用或门和非门表达的 A’ + B’。
In IGCSE, you may be asked to simplify an expression like Q = A·B + A·B’. Using the distributive law: A·(B + B’) = A·1 = A. So the circuit reduces to just a wire (buffer) – no gate needed.
在 IGCSE 中，你可能会被要求简化像 Q = A·B + A·B’ 这样的表达式。使用分配律：A·(B + B’) = A·1 = A。因此电路简化为仅一根连线（缓冲器）——不需要门。
12. Application: Half Adder and Full Adder | 应用：半加器与全加器
A half adder adds two single binary digits (A and B) and produces a Sum (S) and a Carry (C). The Sum is A ⊕ B, and the Carry is A · B. This circuit uses one XOR and one AND gate.
半加器将两个二进制数字（A 和 B）相加，产生和 (S) 与进位 (C)。和是 A ⊕ B，进位是 A · B。该电路使用一个异或门和一个与门。
Full adder adds three single bits – A, B, and a Carry-in (Cin) – to produce Sum and Carry-out (Cout). The Sum is A ⊕ B ⊕ Cin, and Cout = (A·B) + (Cin·(A⊕B)). This can be built with two half adders and an OR gate.
全加器将三个位——A、B 和进位输入 (Cin)——相加，产生和与进位输出 (Cout)。和是 A ⊕ B ⊕
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