IGCSE Computer Science: CPU Key Points | IGCSE 计算机：CPU 考点精讲

📚 IGCSE Computer Science: CPU Key Points | IGCSE 计算机：CPU 考点精讲

The Central Processing Unit (CPU) is often called the ‘brain’ of the computer. It processes all instructions and data, making it the most critical component in any computer system. This revision guide covers everything an IGCSE Computer Science student needs to know about the CPU, from its architecture to performance factors, with clear dual-language explanations.

中央处理器 (CPU) 常被称为计算机的”大脑”。它处理所有指令和数据，是任何计算机系统中最关键的部件。本复习指南涵盖了 IGCSE 计算机科学学生需要掌握的 CPU 全部要点，从体系结构到性能因素，均配以清晰的双语解释。

1. Introduction to CPU | CPU 简介

The CPU is responsible for executing programs by carrying out instructions stored in main memory (RAM). It consists of several components working together in a continuous cycle: fetching an instruction, decoding it, and then executing it. This cycle is fundamental to all modern computers.

CPU 负责通过执行存储在主存 (RAM) 中的指令来运行程序。它由几个协同工作的部件组成，并持续运行一个周期：取出一条指令、解码、然后执行。这个周期是所有现代计算机的基础。

2. Von Neumann Architecture | 冯·诺依曼架构

The vast majority of CPUs today are based on the Von Neumann architecture. In this design, both program instructions and data are stored in the same memory unit. The CPU reads from and writes to this memory via a set of buses (address bus, data bus, control bus). The key feature is the stored-program concept, where instructions are treated as data and can be modified by the program itself.

当今绝大多数 CPU 都基于冯·诺依曼架构。在这种设计中，程序指令和数据存储在同一个存储器中。CPU 通过一组总线（地址总线、数据总线、控制总线）对该存储器进行读写。其关键特征是存储程序概念，即指令被视为数据，并且程序可以修改这些指令。

The address bus carries the memory location the CPU wants to access. The data bus transports the actual data or instruction between the CPU and memory. The control bus sends control signals (like read/write commands) to coordinate the transfer.

地址总线传送 CPU 要访问的内存地址。数据总线在 CPU 和内存之间传输实际的数据或指令。控制总线发送控制信号（如读/写命令）以协调传输。

3. Components of CPU: Control Unit, ALU, Registers | CPU 的组成：控制单元、算术逻辑单元、寄存器

The CPU is composed of three main parts: the Control Unit (CU), the Arithmetic Logic Unit (ALU), and a set of registers. The CU manages the execution of instructions by controlling the flow of data inside the CPU and to external devices. It generates the necessary control signals for the fetch-decode-execute cycle.

CPU 由三个主要部分组成：控制单元 (CU)、算术逻辑单元 (ALU) 和一组寄存器。CU 通过控制 CPU 内部和流向外部设备的数据流来管理指令的执行。它为取指-解码-执行周期生成必要的控制信号。

The ALU performs all arithmetic calculations (addition, subtraction, etc.) and logical operations (AND, OR, NOT, comparisons). Data is held temporarily in registers, which are very fast, small-capacity storage locations within the CPU. These registers provide the CU and ALU with immediate access to the data they need.

ALU 执行所有的算术运算（加、减等）和逻辑运算（与、或、非、比较）。数据暂时保存在寄存器中，寄存器是 CPU 内部极高速、小容量的存储位置。这些寄存器为 CU 和 ALU 提供了对所需数据的即时访问。

4. Key Registers: PC, MAR, MDR, CIR, ACC | 关键寄存器：PC, MAR, MDR, CIR, ACC

For IGCSE, you must be able to name and describe the function of these essential registers:

对于 IGCSE，你必须能够说出并描述以下关键寄存器的功能：

Program Counter (PC) – holds the memory address of the next instruction to be fetched.
程序计数器 (PC) – 存放下一条待取指令的内存地址。
Memory Address Register (MAR) – holds the address of the memory location currently being accessed for reading or writing.
内存地址寄存器 (MAR) – 存放当前正在读写访问的内存地址。
Memory Data Register (MDR) – holds the actual data or instruction that has been read from memory or is to be written to memory.
内存数据寄存器 (MDR) – 存放从内存读出或即将写入内存的实际数据或指令。
Current Instruction Register (CIR) – holds the current instruction while it is being decoded and executed.
当前指令寄存器 (CIR) – 在解码和执行期间存放当前指令。
Accumulator (ACC) – stores the intermediate results of calculations performed by the ALU.
累加器 (ACC) – 存储由 ALU 完成的运算的中间结果。

5. The Fetch-Decode-Execute Cycle | 取指-解码-执行周期

The processor continuously repeats this cycle. In the fetch phase, the address in the PC is copied to the MAR, the CU sends a read signal on the control bus, and the instruction at that memory location is placed on the data bus and stored in the MDR. Then it is copied to the CIR. The PC is incremented to point to the next instruction.

处理器不断重复这个周期。在取指阶段，PC 中的地址被复制到 MAR，CU 在控制总线上发送读信号，该内存地址处的指令被放到数据总线上并存入 MDR。然后它被复制到 CIR。PC 递增以指向下一条指令。

In the decode phase, the CU examines the instruction in the CIR to determine what action is required. This often involves splitting the instruction into an operation code (opcode) and an operand (the data or memory address involved).

在解码阶段，CU 检查 CIR 中的指令以确定需要执行什么操作。这通常涉及将指令拆分为操作码 (opcode) 和操作数（所涉及的数据或内存地址）。

In the execute phase, the CU directs the ALU or other components to carry out the instruction. For example, if the instruction is to add a number to the accumulator, the ALU performs the addition and stores the result in the ACC. The cycle then starts again with the new value in the PC.

在执行阶段，CU 指挥 ALU 或其他部件执行指令。例如，如果指令是将一个数加到累加器中，ALU 执行加法并将结果存入 ACC。然后利用 PC 中的新值再次开始该周期。

6. Factors Affecting CPU Performance: Clock Speed | 影响 CPU 性能的因素：时钟速度

The clock speed, measured in gigahertz (GHz) or megahertz (MHz), indicates how many fetch-decode-execute cycles the CPU can perform per second. A higher clock speed generally means faster processing, as more instructions are executed in a given time. However, this also generates more heat and requires effective cooling.

时钟速度，以吉赫兹 (GHz) 或兆赫兹 (MHz) 为单位，表示 CPU 每秒可以完成多少个取指-解码-执行周期。更高的时钟速度通常意味着更快的处理速度，因为在给定时间内可以执行更多指令。但是，这也会产生更多热量，需要有效的散热。

It is important to note that clock speed alone does not determine overall performance. Modern CPUs may run at similar clock speeds but still outperform older ones due to architectural improvements like pipelining and better cache design.

需要注意的是，仅时钟速度不能决定整体性能。由于流水线技术和更优的缓存设计等架构改进，现代 CPU 可能在相近的时钟速度下远优于旧款。

7. Factors Affecting CPU Performance: Number of Cores | 影响 CPU 性能的因素：核心数量

A core is a complete processing unit capable of performing its own fetch-decode-execute cycle. A multi-core CPU contains two or more cores on one chip, each able to execute instructions independently. This allows true parallel processing, where multiple tasks or parts of a task can be handled simultaneously.

一个核心是一个完整的处理单元，能够执行自己的取指-解码-执行周期。多核 CPU 在一个芯片上包含两个或更多核心，每个核心可以独立执行指令。这允许真正的并行处理，即多个任务或任务的多个部分可以同时处理。

However, the performance gain is not always linear. The software must be written to take advantage of multiple cores. If a program is only designed to run on a single core, the extra cores will not speed up its execution.

但是，性能提升并不总是线性的。软件必须编写成能够利用多个核心。如果一个程序仅设计为在单核上运行，额外的核心不会加快其执行速度。

8. Factors Affecting CPU Performance: Cache Size | 影响 CPU 性能的因素：缓存大小

Cache memory is a small amount of extremely fast RAM located on or very close to the CPU. It stores frequently used instructions and data so the processor can access them quickly, without having to fetch them from the slower main memory (RAM) every time. A larger cache usually improves performance because more data can be kept ready for instant use.

高速缓存 (Cache) 是位于 CPU 上或极靠近 CPU 的少量超高速 RAM。它存储频繁使用的指令和数据，使处理器能够快速访问，而无需每次都从较慢的主存 (RAM) 中取。更大的缓存通常能提高性能，因为有更多数据可以保持在可供即时使用的状态。

Cache is typically organised in levels: L1 cache is the fastest and smallest, built directly into the core; L2 is slightly slower but larger; L3 cache is shared among cores and is even larger. The IGCSE syllabus expects understanding of the general concept rather than detailed level structure.

缓存通常分为多个级别：L1 缓存最快且最小，直接内置于核心中；L2 稍慢但更大；L3 缓存在各核心间共享，容量更大。IGCSE 大纲要求理解一般概念，而非详细的层级结构。

9. Instruction Set and Opcode/Operand | 指令集与操作码/操作数

Every CPU has an instruction set—a collection of basic operations it can perform. During the decode stage, an instruction is broken down into two parts: the opcode, which specifies the operation (e.g., ADD, SUB, LOAD, STORE), and the operand, which provides the data or the address of the data to be used.

每个 CPU 都有一个指令集——它能够执行的基本操作集合。在解码阶段，指令被分解为两部分：操作码 (opcode)，指定操作（如 ADD、SUB、LOAD、STORE）；操作数 (operand)，提供要使用的数据或数据地址。

For example, a simple instruction might be ADD 5, meaning ‘add the value 5 to the current contents of the accumulator’. Another might be LOAD 100, which means ‘load the data found at memory address 100 into the accumulator’. Understanding this differentiation is a common exam requirement.

例如，一条简单指令可能是 ADD 5，意思是”将数值 5 加到累加器的当前内容中”。另一条可能是 LOAD 100，意思是”将内存地址 100 处的数据加载到累加器中”。理解这种区分是常见的考试要求。

10. Embedded Systems and Their Processors | 嵌入式系统及其处理器

An embedded system is a computer system built into a larger device to perform a dedicated function. Examples include washing machines, digital watches, traffic light controllers, and engine management systems. Unlike general-purpose computers, embedded systems typically run a single program stored in ROM.

嵌入式系统是内置在较大设备中以执行特定功能的计算机系统。例子包括洗衣机、电子手表、交通灯控制器和发动机管理系统。与通用计算机不同，嵌入式系统通常运行存储在 ROM 中的单一程序。

The processors used in embedded systems are often microcontrollers. These integrate a CPU, memory (RAM and ROM), and input/output interfaces on a single chip. They are usually low-power, compact, and reliable. The CPU inside such a system is still based on the same fetch-decode-execute cycle but may have a simpler instruction set and lower clock speed to reduce cost and power consumption.

嵌入式系统中使用的处理器通常是微控制器。它们将 CPU、存储器 (RAM 和 ROM) 以及输入/输出接口集成在单个芯片上。它们通常功耗低、体积小且可靠。此类系统内部的 CPU 依然基于相同的取指-解码-执行周期，但可能具有更简单的指令集和更低的时钟速度，以降低成本和功耗。

11. Buses, Addressability and Word Length | 总线、寻址能力与字长

The width of the address bus determines the maximum amount of addressable memory. If there are n address lines, the CPU can address 2ⁿ memory locations. The data bus width (or word length) indicates how many bits can be transferred at once. Wider buses generally allow faster data transfer.

地址总线的宽度决定了可寻址内存的最大容量。如果有 n 条地址线，CPU 可以寻址 2ⁿ 个内存位置。数据总线宽度（或字长）表示一次可以传输多少位。更宽的总线通常允许更快的数据传输。

In the IGCSE context, exam questions may ask you to explain how increasing the address bus width affects memory capacity. For example, a change from 16-bit to 32-bit address bus would increase the addressable locations from 2¹⁶ (about 65,536) to 2³² (over 4 billion).

在 IGCSE 语境下，考题可能会要求你解释增加地址总线宽度如何影响内存容量。例如，从 16 位地址总线变为 32 位，可寻址位置将从 2¹⁶（约 65,536）增加到 2³²（超过 40 亿）。

12. Summary: Key Points for Exam | 总结：考试要点

To excel in CPU-related questions, remember these critical points:

要在 CPU 相关题目中取得优异成绩，请牢记以下关键点：

The Von Neumann architecture stores both data and instructions in the same memory.
冯·诺依曼架构将数据和指令存储在同一内存中。
The four essential registers are PC, MAR, MDR, and CIR (Accumulator is also important).
四个基本寄存器是 PC、MAR、MDR 和 CIR（累加器也很重要）。
The fetch-decode-execute cycle is the continuous loop that drives all processing.
取指-解码-执行周期是驱动所有处理的连续循环。
CPU performance is primarily influenced by clock speed, number of cores, and cache size.
CPU 性能主要受时钟速度、核心数量和缓存大小的影响。
An embedded system’s processor is often a microcontroller, optimised for a single dedicated task.
嵌入式系统的处理器通常是微控制器，针对单一的专用任务优化。
Always be able to explain how data moves between registers during the cycle, as this is a favourite exam scenario.
务必能够解释在该周期中数据如何在寄存器之间移动，因为这是考试中常见的场景。

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IGCSE Computer Science: CPU Key Points | IGCSE 计算机：CPU 考点精讲