📚 Logic Gates for IB and OCR Computer Science | IB OCR 计算机逻辑门考点精讲
Logic gates form the foundation of digital circuits and are a core topic in both IB Computer Science and OCR A-Level Computer Science. Whether you are building a half adder or simplifying a Boolean expression using De Morgan’s laws, a thorough understanding of how each gate behaves, its truth table, and its symbolic representation is essential. This article provides a structured breakdown of all key concepts, common exam pitfalls, and practical design techniques that you need to master logic gates for your assessments.
逻辑门是数字电路的基础，也是 IB 计算机科学和 OCR A-Level 计算机科学的核心考点。不论是搭建半加器，还是运用德摩根定律化简布尔表达式，透彻理解每种门的特性、真值表和符号表示都至关重要。本文将系统梳理所有重要概念、常见考试易错点以及实际设计技巧，帮助你全面掌握逻辑门的相关评估要求。
1. Introduction to Logic Gates | 逻辑门概述
A logic gate is an electronic component that takes one or more binary inputs and produces a single binary output based on a fixed rule. Binary inputs and outputs are represented by two voltage levels, typically labelled as 0 (low, false) and 1 (high, true). Logic gates are the fundamental building blocks of combinational and sequential circuits, and they are used to implement Boolean algebra in hardware form.
逻辑门是一种电子元件，它接受一个或多个二进制输入，并按照确定的规则产生单一的二进制输出。输入和输出由两种电压电平表示，通常标记为 0（低电平、假）和 1（高电平、真）。逻辑门是组合电路和时序电路的基本构件，用于以硬件形式实现布尔代数运算。
In the IB and OCR syllabi, you are expected to recognise standard symbols (both ANSI/IEEE and IEC rectangular shapes), draw and interpret circuit diagrams, derive truth tables, and write corresponding Boolean expressions. Questions often combine several gates into a logic network and ask you to predict the output for given input combinations or to simplify the network to a minimum form.
在 IB 和 OCR 课程大纲中，要求学生能识别标准符号（包括 ANSI/IEEE 和 IEC 矩形符号），绘制并解读电路图，推导真值表，以及写出对应的布尔表达式。考试题目经常将多个门组合成一个逻辑网络，要求你针对给定输入预测输出，或将网络化简为最简形式。
2. Basic Gates: AND, OR, NOT | 基本门：与门、或门、非门
The three simplest logic gates are the AND gate, OR gate, and NOT gate. An AND gate outputs 1 only when all its inputs are 1. Its Boolean expression is Z = A · B (often written as Z = A AND B). A two-input AND gate has the following truth table:
最简单的三种逻辑门是与门、或门和非门。与门仅在所有输入均为 1 时输出 1，其布尔表达式为 Z = A · B（常写作 Z = A AND B）。二输入与门的真值表如下：
| A | B | Z |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
An OR gate outputs 1 if at least one input is 1. Its Boolean expression is Z = A + B (Z = A OR B). The truth table for a two-input OR gate is:
或门在至少一个输入为 1 时输出 1，其布尔表达式为 Z = A + B（Z = A OR B）。二输入或门的真值表是：
| A | B | Z |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
The NOT gate (inverter) takes a single input and outputs its complement. Its Boolean expression is Z = ¬A (or A’). The truth table is trivial: input 0 gives 1, and input 1 gives 0.
非门（反相器）接受单一输入并输出其补值，其布尔表达式为 Z = ¬A（或 A’）。真值表很简单：输入 0 产生 1，输入 1 产生 0。
3. Universal Gates: NAND and NOR | 通用门：与非门和或非门
A NAND gate is equivalent to an AND gate followed by a NOT gate. Its Boolean expression is Z = ¬(A · B). The output is 0 only when all inputs are 1. A two-input NAND truth table shows the inversion of the AND output.
与非门相当于一个与门后接一个非门，其布尔表达式为 Z = ¬(A · B)。只有所有输入均为 1 时输出才为 0。二输入与非门的真值表反映了与门输出的反转。
Similarly, a NOR gate is an OR gate followed by a NOT gate: Z = ¬(A + B). It outputs 1 only when all inputs are 0. Both NAND and NOR gates are called universal gates because any other logic function (AND, OR, NOT, XOR, etc.) can be implemented using only NAND gates or only NOR gates. This property is frequently tested in OCR exams where you may be asked to construct a given circuit solely using NAND gates.
类似地，或非门是一个或门后接非门：Z = ¬(A + B)。仅在所有输入均为 0 时才输出 1。与非门和或非门都被称为通用门，因为仅使用与非门或仅使用或非门就可以实现任何其他逻辑功能（AND、OR、NOT、XOR 等）。这一特性经常在 OCR 考试中考查，可能要求你仅用与非门构建给定电路。
4. XOR and XNOR Gates | 异或门与同或门
The Exclusive-OR (XOR) gate outputs 1 when an odd number of its inputs are 1. For two inputs, it gives a true output when the inputs differ. The Boolean expression is Z = A ⊕ B, which can be written as Z = A · ¬B + ¬A · B. The truth table for a two-input XOR gate is:
异或门（XOR）在输入中 1 的个数为奇数时输出 1。对二输入而言，当两个输入不同时输出真，其布尔表达式为 Z = A ⊕ B，可写为 Z = A · ¬B + ¬A · B。二输入异或门的真值表为：
| A | B | Z |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The Exclusive-NOR (XNOR) gate is the complement of XOR: it outputs 1 when both inputs are the same. Its Boolean expression is Z = ¬(A ⊕ B) or Z = A · B + ¬A · ¬B. The XNOR gate is often used in equality comparators.
同或门（XNOR）是异或门的补：当两个输入相同时输出 1。其布尔表达式为 Z = ¬(A ⊕ B) 或 Z = A · B + ¬A · ¬B。同或门常用于相等比较器。
5. Truth Tables | 真值表
A truth table lists all possible input combinations for a logic circuit and the corresponding output(s). It is the most direct way to describe the behaviour of any combinational logic network. For n inputs, there are 2ⁿ rows. When constructing a truth table, always follow a systematic order (e.g. binary counting from 000 to 111) to ensure no combination is missed.
真值表列出了逻辑电路所有可能的输入组合以及对应的输出。这是描述任何组合逻辑网络功能最直接的方式。对于 n 个输入，共有 2ⁿ 行。在构建真值表时，务必按照系统顺序（例如从 000 到 111 的二进制计数）来确保没有遗漏任何组合。
In exam problems, you are often given a circuit diagram and asked to produce its truth table. Work column by column: label intermediate nodes, compute them stepwise, and finally determine the primary output. For the expression Z = (¬A + B) · (A + ¬C), you would create columns for A, B, C, ¬A, ¬C, ¬A + B, A + ¬C, and finally Z. This methodical approach prevents careless mistakes.
在考试题目中，经常给出电路图并要求你写出其真值表。应逐列处理：标注中间节点，逐步计算，最后确定主输出。以表达式 Z = (¬A + B) · (A + ¬C) 为例，你将创建 A、B、C、¬A、¬C、¬A + B、A + ¬C 和最终 Z 等列。这种有序的方法可以避免粗心错误。
6. Boolean Expressions | 布尔表达式
Boolean expressions use variables (A, B, C, …), logical operators (·, +, ¬, ⊕), and parentheses to represent logic operations. They are the algebraic link between truth tables and logic circuit diagrams. Simplifying Boolean expressions is a key skill, achieved through algebraic manipulation using the laws of Boolean algebra (identity, null, idempotent, complement, commutative, associative, distributive, absorption, and De Morgan’s laws).
布尔表达式使用变量（A、B、C……）、逻辑运算符（·、+、¬、⊕）和括号来表示逻辑运算。它们是连接真值表和逻辑电路图的代数纽带。化简布尔表达式是一项关键技能，可通过运用布尔代数定律（单位律、零律、幂等律、互补律、交换律、结合律、分配律、吸收律和德摩根定律）进行代数操作来实现。
In IB and OCR questions, you may need to derive an expression from a truth table using sum-of-products (SOP) or product-of-sums (POS) methods. In SOP, you consider the rows where output is 1: for each such row, write the AND of the input variables (with the variable negated if it is 0 in that row) and OR all these product terms. For a truth table with output 1 at A=0,B=1 and A=1,B=1, the SOP expression is ¬A·B + A·B, which simplifies to B.
在 IB 和 OCR 的题目中，可能需要你使用与或式（SOP）或或与式（POS）从真值表推导表达式。在 SOP 方法中，考察输出为 1 的行：对于每一行，写出输入变量的与项（如果该行中变量为 0 则取反），然后将所有这些乘积项相或。若真值表在 A=0,B=1 和 A=1,B=1 时输出为 1，SOP 表达式为 ¬A·B + A·B，可化简为 B。
7. Logic Circuit Diagrams | 逻辑电路图
A logic circuit diagram uses standard symbols to represent the interconnections of gates. The IB syllabus recognises both the distinctive shape symbols (curved for AND, pointed for OR, triangle with bubble for NOT) and the rectangular IEC symbols (with & for AND, ≥1 for OR, and 1 for NOT with a bubble). OCR typically uses the ANSI/IEEE distinctive shapes. You should be comfortable drawing and interpreting both styles, though the underlying function is identical.
逻辑电路图使用标准符号表示门的互连关系。IB 课程认可两种符号风格：特征形状符号（AND 用弧形边、OR 用尖边、NOT 用带小圆的三角形）和矩形 IEC 符号（AND 中标 &，OR 中标 ≥1，NOT 用带小圆的 1）。OCR 通常使用 ANSI/IEEE 特征形状。你应该能够熟练绘制并解读两种风格，尽管其功能完全相同。
When drawing circuits, NEATLY label inputs and outputs, use straight lines for connections, and avoid crossing lines where possible. If a signal line branches, place a connection dot at the junction. For complex circuits, break the diagram into functional blocks. Exam marks are often awarded for correct structure and correct gate choices; a missing bubble on a NOT gate can invalidate the entire function.
在绘制电路时，要整洁地标注输入和输出，用直线连接，尽量避免交叉线。如果信号线分支，应在交汇处画上连接点。对于复杂电路，可将图分解为功能块。考试中通常会根据正确的结构和正确的门选择给分；非门上遗漏一个小圆圈就可能导致整个功能失效。
8. De Morgan’s Laws | 德摩根定律
De Morgan’s laws provide a formal method for converting between AND and OR operations when negation is involved. The two laws are:
德摩根定律提供了一种在涉及取反时进行 AND 与 OR 运算转换的规范方法。两条定律是：
¬(A · B) = ¬A + ¬B
¬(A + B) = ¬A · ¬B
These laws allow you to push inversion bubbles through gates and change the gate type: a NAND gate is equivalent to an OR gate with inverted inputs; a NOR gate is equivalent to an AND gate with inverted inputs. In practical circuit design, De Morgan’s laws enable you to replace expensive or unavailable gate types with others, and they are the foundation for deriving the NAND-only or NOR-only implementations.
这些定律允许你将取反小圆圈穿过门并改变门的类型：与非门等效于输入取反的或门；或非门等效于输入取反的与门。在实际电路设计中，德摩根定律使你能够用其他门替代昂贵或不可用的门类型，也是推导纯与非门或纯或非门实现的基础。
On IB and OCR exams, you may be asked to simplify an expression such as ¬(¬A + B) · C. Apply De Morgan: ¬(¬A + B) becomes A · ¬B, so the whole expression simplifies to A · ¬B · C, which a single AND gate can implement. Always show your steps clearly to earn full method marks.
在 IB 和 OCR 考试中，你可能需要化简诸如 ¬(¬A + B) · C 的表达式。应用德摩根律：¬(¬A + B) 变为 A · ¬B，于是整个表达式简化为 A · ¬B · C，可用单个与门实现。务必清晰写出步骤以获取完整的过程分。
9. Combinational Logic Circuit Design | 组合逻辑电路设计
Designing a combinational logic circuit typically follows a systematic approach: (1) from a word problem, define the input and output variables; (2) construct the truth table describing the desired behaviour; (3) derive a Boolean expression (commonly in sum-of-products form); (4) simplify the expression using Boolean algebra or Karnaugh maps; (5) draw the logic circuit diagram using the simplified expression.
组合逻辑电路的设计通常遵循一套系统方法：（1）根据文字问题定义输入和输出变量；（2）构建描述所需功能的真值表；（3）推导布尔表达式（通常为与或式）；（4）运用布尔代数或卡诺图化简表达式；（5）使用化简后的表达式绘制逻辑电路图。
Consider a simple example: design a circuit that outputs 1 when a 2-bit binary number (AB) is a prime number (2 and 3). The truth table has rows 10 and 11 as 1. The SOP expression is A·¬B + A·B = A. So a wire from A to the output is sufficient. More complex problems in exams might involve multiple outputs or don’t-care conditions, but the structured design method remains the same.
举一个简单例子：设计一个电路，当二位二进制数（AB）为质数（2 和 3）时输出 1。真值表中 10 和 11 行为 1。SOP 表达式为 A·¬B + A·B = A。因此，只需将 A 连接到输出即可。考试中更复杂的问题可能涉及多个输出或无关项，但结构化的设计方法保持不变。
10. Adders: Half Adder and Full Adder | 加法器：半加器与全加器
Adders are classic examples of combinational logic circuits. A half adder adds two single-bit binary numbers, A and B, producing a sum bit (S) and a carry bit (C). The Boolean equations are:
加法器是组合逻辑电路的经典例子。半加器将两个单比特二进制数 A 和 B 相加，产生和位（S）与进位位（C）。布尔方程为：
S = A ⊕ B
C = A · B
A half adder can be built using one XOR gate and one AND gate. However, it cannot handle a carry-in from a previous addition, limiting its use to the least significant bit only.
半加器可由一个异或门和一个与门构成。但它不能处理来自前一位的进位输入，因此仅限于最低位加法。
A full adder overcomes this by including a carry-in (Cin). It sums three bits (A, B, Cin) and outputs a sum (S) and a carry-out (Cout). The equations are:
全加器通过引入进位输入（Cin）克服了这一局限。它对三个比特（A、B、Cin）求和，输出和位（S）与进位输出（Cout）。方程为：
S = A ⊕ B ⊕ Cin
Cout = A·B + (A ⊕ B)·Cin
Full adders can be cascaded to build ripple carry adders for multi-bit numbers. Knowing how to derive these equations from truth tables and how to draw the corresponding circuits is a common examination requirement.
多个全加器可级联构成多位数的行波进位加法器。掌握如何从真值表推导这些方程以及如何绘制对应电路是常见的考试要求。
11. Implementation Using NAND/NOR Only | 纯与非门/纯或非门实现
Because NAND and NOR gates are universal, any combinational circuit can be implemented using only NAND gates or only NOR gates. The general approach: start with the simplified Boolean expression in AND-OR form. For NAND-only implementation, double-negate the entire expression and apply De Morgan’s law to convert the outer OR into a NAND. Each AND gate then becomes a NAND and an inverter (which itself can be made from a NAND by tying inputs together).
由于与非门和或非门都是通用门，任何组合电路都可以仅用与非门或仅用或非门实现。一般方法：从与或形式的简化布尔表达式开始。对于纯与非门实现，对整个表达式取两次反，并应用德摩根定律将外层的或转换为与非。每一个与门就变成一个与非门加一个反相器（而反相器本身可通过将与非门的输入端连接在一起实现）。
For example, to implement Z = A·B + C·D using NAND gates only: double-negate to get Z = ¬(¬(A·B) · ¬(C·D)). Now ¬(A·B) is a NAND of A and B, ¬(C·D) is a NAND of C and D, and the final outer NAND combines these two NAND outputs. Thus the circuit uses three NAND gates. Practice drawing these transformations until they become second nature.
例如，要仅用与非门实现 Z = A·B + C·D：双重取反得到 Z = ¬(¬(A·B) · ¬(C·D))。此时 ¬(A·B) 是 A 和 B 的与非，¬(C·D) 是 C 和 D 的与非，最后的外层与非门将这两个与非输出组合起来。因此该电路使用了三个与非门。多加练习绘制这类变换，直到它们成为本能。
12. Summary and Common Mistakes | 总结与常见错误
Mastering logic gates requires fluency in switching between truth tables, Boolean expressions, and circuit diagrams. The most common exam errors include: forgetting to apply De Morgan’s laws correctly (negating incorrectly when breaking a bar); misreading a circuit diagram because a bubble is overlooked; incorrectly ordering rows in a truth table; and using non-universal gates when explicitly asked for NAND-only or NOR-only solutions. Always double-check your work by testing a few input combinations against the original specification.
掌握逻辑门需要在真值表、布尔表达式和电路图之间自如切换。最常见的考试错误包括：德摩根定律应用不当（拆分上划线时取反错误）；因遗漏小圆圈而误读电路图；真值表中行的排列顺序错误；以及在明确要求纯与非门或纯或非门实现时使用了非通用门。务必通过将少数输入组合对照原始规格进行测试来复核你的解答。
Finally, keep your notation clean and consistent. Use the ¬ symbol or an overbar for NOT, · for AND, and + for OR. In logic diagrams, ensure all connection points are clearly marked and gates are labelled if necessary. With regular practice of past paper questions and a clear understanding of the fundamental principles, logic gates can become one of the highest-scoring topics on your IB or OCR Computer Science exam.
最后，保持符号的整洁和一致。使用 ¬ 符号或上划线表示非，用 · 表示与，用 + 表示或。在逻辑图中，确保所有连接点清晰标注，必要时给门加上标记。通过定期练习历年真题并透彻理解基本原理，逻辑门有望成为你 IB 或 OCR 计算机科学考试中得分率最高的专题之一。
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