Logic Gates: Core Revision for IB & AQA Computer Science | 逻辑门考点精讲

📚 Logic Gates: Core Revision for IB & AQA Computer Science | 逻辑门考点精讲

Logic gates are the fundamental building blocks of digital circuits, enabling computers to process binary data through Boolean operations. Understanding their behaviour, truth tables, and combinations is essential for both IB Computer Science and AQA A‑level Computer Science. This article breaks down every key concept, from basic gates to adders and simplification techniques, with paired English‑Chinese explanations to strengthen your bilingual mastery.

逻辑门是数字电路的基本构建模块，通过布尔运算使计算机能够处理二进制数据。理解它们的行为、真值表以及组合方式，对于 IB 计算机科学和 AQA A‑level 计算机科学都至关重要。本文逐一解析每个关键概念，从基本门电路到加法器与化简技巧，并配以中英文对照讲解，帮助你牢固掌握双语知识。

1. Introduction to Logic Gates | 逻辑门简介

Logic gates are electronic circuits that implement Boolean functions. They receive one or more binary inputs (0 or 1, representing LOW and HIGH voltages) and produce a single binary output. The most basic gates are NOT, AND, OR, NAND, NOR, XOR, and XNOR. Each gate has a unique symbol, a truth table, and a Boolean expression that defines its operation.

逻辑门是实现布尔函数的电子电路。它们接收一个或多个二进制输入（0 或 1，代表低电平和高电平），并产生一个二进制输出。最基本的门电路有非门、与门、或门、与非门、或非门、异或门和同或门。每种门都有独特的符号、真值表以及定义其运算的布尔表达式。

In modern digital systems, logic gates are fabricated as integrated circuits (ICs) using CMOS technology. Even complex operations in a CPU, such as arithmetic and control logic, are ultimately constructed from these simple gates. Mastering them is the first step toward understanding computer architecture.

在现代数字系统中，逻辑门采用 CMOS 技术制造为集成电路 (IC)。即便是 CPU 中的复杂操作，如算术运算和控制逻辑，最终也是由这些简单门电路搭建而成。掌握它们是理解计算机体系结构的第一步。

2. Basic Gates: NOT, AND, OR | 基本门电路：非门、与门、或门

The NOT gate (inverter) has one input and one output. It reverses the logic level: input 1 becomes 0, and 0 becomes 1. Boolean expression: F = A or F = A’.

非门（反相器）有一个输入和一个输出。它反转逻辑电平：输入 1 变为 0，0 变为 1。布尔表达式：F = A 或 F = A’。

The AND gate outputs 1 only if all its inputs are 1. For a two‑input AND gate, the Boolean expression is F = A · B. In electronic terms, it is equivalent to a series connection of switches: current flows only when both switches are closed.

与门仅在所有输入均为 1 时才输出 1。对于两输入与门，布尔表达式为 F = A · B。从电子角度看，它等效于开关串联：只有当两个开关都闭合时才有电流。

The OR gate outputs 1 when at least one input is 1. Its Boolean expression is F = A + B. Think of parallel switches: the light turns on if either switch is pressed.

或门在至少一个输入为 1 时输出 1。布尔表达式为 F = A + B。可以类比并联开关：只要按下任意一个开关，灯就会亮。

NOT truth table: Input 0 → Output 1; Input 1 → Output 0

非门真值表：输入 0 → 输出 1；输入 1 → 输出 0
AND truth table: 0·0=0; 0·1=0; 1·0=0; 1·1=1

与门真值表：0·0=0; 0·1=0; 1·0=0; 1·1=1
OR truth table: 0+0=0; 0+1=1; 1+0=1; 1+1=1

或门真值表：0+0=0; 0+1=1; 1+0=1; 1+1=1

3. NAND and NOR Gates | 与非门和或非门

The NAND gate is an AND gate followed by a NOT. It outputs 1 unless all inputs are 1. Boolean expression: F = A·B. NAND is called a ‘universal gate’ because any Boolean function can be implemented using only NAND gates.

与非门是与门后接非门的结果。除所有输入均为 1 的情况外，它输出 1。布尔表达式：F = A·B。与非门被称为“通用门”，因为仅用与非门就能实现任何布尔函数。

The NOR gate is an OR gate followed by an inverter. It outputs 1 only when all inputs are 0. Expression: F = A+B. NOR is also a universal gate and is often used in flash memory design.

或非门是或门后接反相器。仅在所有输入都为 0 时才输出 1。表达式：F = A+B。或非门同样是一种通用门，常用于闪存设计。

In AQA exams, you are expected to recognise their symbols and draw circuits entirely from NAND or NOR gates. In IB, you need to justify how universality works by showing NOT, AND, OR constructed from NAND gates.

在 AQA 考试中，你需要能识别它们的符号并画出完全由与非门或或非门构成的电路。在 IB 中，你需要通过展示用与非门构建非门、与门和或门，来说明其通用性。

4. XOR and XNOR Gates | 异或门和同或门

The XOR (Exclusive OR) gate gives 1 when the inputs differ. For two inputs: F = A ⊕ B. Truth table: 0⊕0=0; 0⊕1=1; 1⊕0=1; 1⊕1=0. It is fundamental to addition, parity checking, and cryptography.

异或门（互斥或门）在输入不同时输出 1。两输入情况：F = A ⊕ B。真值表：0⊕0=0; 0⊕1=1; 1⊕0=1; 1⊕1=0。它在加法、奇偶校验和密码学中不可或缺。

The XNOR (Exclusive NOR) gate is the complement of XOR; outputs 1 when inputs are equal. Expression: F = A ⊕ B or F = A ⊙ B. It is used in equality comparators.

同或门（互斥或非门）是异或门的补；输入相同时输出 1。表达式：F = A ⊕ B 或 F = A ⊙ B。它用于相等比较器。

Note for IB: you may derive XOR from simpler gates. A typical implementation: A⊕B = A·B + A·B. Recognizing this pattern helps in K‑map simplification.

IB 注意：你可能需要用更简单的门实现异或。典型实现：A⊕B = A·B + A·B。识别这种模式有助于卡诺图化简。

5. Truth Tables | 真值表

A truth table lists all possible input combinations and the corresponding output for a logic circuit. For n inputs, there are 2ⁿ rows. Truth tables provide a systematic way to define and verify logic functions and are the starting point for deriving Boolean expressions.

真值表列出所有可能的输入组合以及对应输出。对于 n 个输入，共有 2ⁿ 行。真值表为定义和验证逻辑函数提供了系统化方法，也是推导布尔表达式的起点。

Constructing a truth table for a composite circuit: label intermediate nodes, calculate them stepwise. Example: F = (A·B) + C.

为组合电路构建真值表：标记中间节点，逐步计算。例如：F = (A·B) + C。

A	B	C	A·B	C	F
0	0	0	0	1	1
0	0	1	0	0	0
0	1	0	0	1	1
0	1	1	0	0	0
1	0	0	0	1	1
1	0	1	0	0	0
1	1	0	1	1	1
1	1	1	1	0	1

Exam tip: always double‑check rows where inputs differ by only one bit – these reveal simple errors. For IB internal assessments, truth tables are often used to test the logic of a designed circuit before building it with chips.

考试技巧：务必检查那些仅有一位输入不同的行——这些行最容易暴露简单错误。在 IB 内部评估中，真值表常用于在使用芯片搭建电路之前测试所设计逻辑的正确性。

6. Boolean Expressions and Algebra | 布尔表达式与布尔代数

Boolean algebra manipulates logic expressions using identities and theorems. Key laws: Commutative (A+B = B+A), Associative (A+(B+C) = (A+B)+C), Distributive (A·(B+C) = A·B + A·C), Absorption (A + A·B = A), and De Morgan’s laws: A·B = A + B and A+B = A · B.

布尔代数利用恒等式和定理操纵逻辑表达式。重要定律：交换律 (A+B = B+A)，结合律 (A+(B+C) = (A+B)+C)，分配律 (A·(B+C) = A·B + A·C)，吸收律 (A + A·B = A)，以及德摩根定律：A·B = A + B 和 A+B = A · B。

Simplifying expressions reduces the number of gates needed. For instance, F = A·B + A·B can be reduced to A (by distribution A·(B+B) = A·1 = A). This skill is tested in both IB Paper 2 and AQA structured questions.

化简表达式能减少所需门电路的数量。例如，F = A·B + A·B 可以化简为 A（利用分配律 A·(B+B) = A·1 = A）。这项能力在 IB 论文二和 AQA 结构化问题中都会考查。

Canonical forms: Sum of Products (SOP) and Product of Sums (POS). SOP is derived by OR‑ing the minterms where output is 1; POS by AND‑ing maxterms where output is 0. Converting between them is often easier via truth table or K‑map.

规范形式：积之和 (SOP) 与和之积 (POS)。SOP 通过对输出为 1 的最小项进行或运算得到；POS 通过对输出为 0 的最大项进行与运算得到。两者之间的转换通常通过真值表或卡诺图更容易实现。

7. Logic Gate Symbols | 逻辑门符号

Two common standards exist: ANSI/IEEE (mil‑spec, used in the US) and IEC 60617 (box‑shaped, used internationally). UK AQA exams predominantly use IEC symbols, while IB may accept either but often uses the distinctive ‘curved’ AND/OR or MIL symbols. It is vital to learn both sets.

存在两种常见标准：ANSI/IEEE（军用规格，美国常用）和 IEC 60617（矩形框，国际通用）。英国 AQA 考试主要使用 IEC 符号，而 IB 接受任一标准，但常使用有特色的“曲线”与/或门或 MIL 符号。必须认识两种符号集。

Key recognition: AND = flat‑ended bullet shape (MIL) or box with ‘&’ (IEC); OR = curved pointed shape (MIL) or box with ‘≥1’; NOT = triangle with bubble; NAND = AND with bubble; NOR = OR with bubble; XOR = OR with extra arc or box with ‘=1’.

关键辨识：与门 = 平头子弹形 (MIL) 或带 ‘&’ 的矩形框 (IEC)；或门 = 弧形尖头形 (MIL) 或带 ‘≥1’ 的矩形框；非门 = 三角形加小圆圈；与非门 = 与门加小圆圈；或非门 = 或门加小圆圈；异或门 = 或门附加弧线或带 ‘=1’ 的矩形框。

In schematic diagrams, always check the bubble (inversion) on inputs or outputs. A bubble on an input of an AND gate effectively turns the gate into a NAND function with inverted inputs.

在原理图中，务必检查输入或输出端的小圆圈（反相）。与门输入端带有小圆圈，实际上使其成为具有反相输入的与非功能。

8. Building Circuits: Half Adder and Full Adder | 组合电路：半加器和全加器

A half adder adds two single bits, producing a sum (S) and a carry (C). Logic: S = A ⊕ B, C = A·B. It uses one XOR gate and one AND gate. Half adders cannot handle a carry input, limiting their use to the least significant bit of multi‑bit addition.

半加器将两个单比特相加，产生和 (S) 与进位 (C)。逻辑：S = A ⊕ B，C = A·B。它使用一个异或门和一个与门。半加器无法处理进位输入，因此仅限于多比特加法中的最低位使用。

A full adder adds three bits: two operands and a carry‑in (Cᵢ). It produces sum (S) and carry‑out (Cₒ). Basic structure: S = A ⊕ B ⊕ Cᵢ, Cₒ = (A·B) + (Cᵢ·(A ⊕ B)). Full adders can be cascaded to create a ripple‑carry adder for n‑bit numbers.

全加器对三个比特进行加法：两个操作数和一个进位输入 (Cᵢ)。它产生和 (S) 与进位输出 (Cₒ)。基本结构：S = A ⊕ B ⊕ Cᵢ, Cₒ = (A·B) + (Cᵢ·(A ⊕ B))。全加器可级联起来构成 n 位数的行波进位加法器。

IB often asks for the block diagram and truth table of a 4‑bit binary adder. AQA focuses on constructing a full adder from logic gates and understanding propagation delay. Try building one using only NAND gates to deepen your understanding.

IB 经常要求绘制 4 位二进制加法器的方块图与真值表。AQA 侧重考查用逻辑门构建全加器并理解传播延时。尝试仅用与非门构建一个全加器，以加深理解。

9. Simplifying Logic with Karnaugh Maps (K‑Maps) | 用卡诺图化简逻辑

A Karnaugh map is a visual tool for simplifying Boolean expressions of up to four variables (occasionally six). It arranges minterms so that adjacent cells differ by only one bit, enabling easy grouping of 1s to eliminate variables. Groups must be rectangles of sizes 1, 2, 4, or 8.

卡诺图是一种用于化简最多四个变量（偶尔六个）的布尔表达式的可视化工具。它排列最小项，使得相邻单元只差一个变量，从而便于将 1 分组以消去变量。分组必须是尺寸为 1、2、4 或 8 的矩形。

The simplified SOP expression is obtained by reading off the common variables from each group. For example, an 8‑cell group covering A=1 eliminates B and C, giving F = A. Always wrap around edges: top and bottom, left and right are adjacent.

化简后的 SOP 表达式通过从各组读取公共变量获得。例如，一个覆盖 A=1 的 8 格分组消去了 B 和 C，得到 F = A。务必利用卷绕：上下、左右被视为相邻。

Both IB and AQA require you to construct K‑maps from truth tables, identify prime implicants, and write simplified expressions. Common mistake: leaving out essential prime implicants or creating non‑rectangular groups.

IB 和 AQA 都要求你根据真值表构建卡诺图，识别质蕴含项，并写出化简后的表达式。常见错误：漏掉必要质蕴含项或构成非矩形分组。

10. Practical Applications | 实际应用

Logic gates appear in countless real‑world devices: arithmetic logic units (ALUs), memory decoders, multiplexers, flip‑flops, and control systems. In a washing machine, gates decide when to start the spin cycle based on door‑closed and water‑level sensors.

逻辑门出现在无数现实设备中：算术逻辑单元 (ALU)、存储器译码器、多路选择器、触发器和控制系统。在洗衣机中，逻辑门基于门关闭和水位传感器决定何时开始脱水。

Another example is the traffic light controller where gates process sensor inputs to set safe signal sequences. In IB coursework, you might implement a simple vending machine logic using gates; AQA practical exams may involve building and testing gate circuits on breadboards.

另一个例子是交通灯控制器，其中门电路处理传感器输入以设定安全的信号序列。在 IB 课程作业中，你可能会运用门电路实现一个简单的自动售货机逻辑；AQA 实践考试可能涉及在面包板上搭建并测试门电路。

11. Exam Tips and Common Pitfalls | 考试技巧与常见误区

Read symbols carefully: A bubble on an input changes the function. Mistaking a NOR for an OR with inverted inputs can cost marks.

仔细阅读符号：输入上的小圆圈会改变功能。误将或非门当作带反相输入的或门，会导致丢分。
Double‑check truth table completeness: 2ⁿ rows must be included and in binary order to avoid omissions.

反复检查真值表是否完整：必须包含 2ⁿ 行并按二进制顺序排列，以防遗漏。
K‑map grouping: always start with the largest possible groups (8, then 4, then 2) and ensure every 1 is covered at least once. Redundant groups may not cause an error but indicate incomplete optimisation.

卡诺图分组：始终从尽可能大的组开始（8，然后 4，再 2），并确保每个 1 至少被覆盖一次。冗余分组不一定会导致错误，但表明优化不彻底。
Simplify using Boolean algebra before drawing a circuit to reduce complexity and gain time in exams.

在绘制电路之前先用布尔代数化简，以降低复杂度并节省考试时间。
When converting between NAND‑only or NOR‑only implementations, apply De Morgan’s theorem systematically. Draw the original AND‑OR circuit first, then replace with equivalent gates.

当转换为纯与非或纯或非实现时，有条理地应用德摩根定理。先画出原始与‑或电路，再替换为等效门。

12. Summary | 总结

Mastering logic gates requires fluency in truth tables, Boolean algebra, gate symbols, simplification techniques, and practical circuit building. Whether you are preparing for IB Paper 2 or AQA Component 2, consistent practice with past‑paper questions and hands‑on circuit design is the key to success.

掌握逻辑门需要熟练运用真值表、布尔代数、门电路符号、化简技巧以及实际电路搭建。无论你是在准备 IB 论文二还是 AQA 组件二，持续练习历年真题并亲手设计电路，都是成功的关键。

Return to this guide whenever you need a quick bilingual refresher, and remember: logic gates are not just exam topics – they are the language of all digital computation.

当你需要快速的双语复习时，可以随时查阅本文。请记住：逻辑门不仅是考试内容——它们还是所有数字计算的语言。

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Logic Gates: Core Revision for IB & AQA Computer Science | 逻辑门考点精讲