📚 Core Knowledge of Computer Architecture | 计算机体系结构核心知识
Computer architecture is the conceptual design and fundamental operational structure of a computer system. It defines how the hardware components are organised and how they interact to execute instructions, which forms the foundation for all of computer science.
计算机体系结构是计算机系统的概念性设计和基本运行结构。它定义了硬件组件如何组织以及它们如何相互作用来执行指令，这构成了整个计算机科学的基础。
1. Computer Architecture vs Computer Organisation | 计算机体系结构与计算机组织的区别
Computer architecture refers to the attributes of a system that are visible to a programmer, such as instruction sets, addressing modes, and data types. These attributes directly affect the logical execution of a program.
计算机体系结构是指程序员可见的系统属性，如指令集、寻址方式和数据类型。这些属性直接影响程序的逻辑执行。
Computer organisation, in contrast, describes how the hardware is implemented to realise the architectural specification. It deals with physical components such as control signals, memory technology, and circuit design.
相比之下，计算机组织描述的是如何实现硬件以满足体系结构的规范。它涉及物理组件，如控制信号、存储技术和电路设计。
In short, architecture answers ‘what’ the computer does, while organisation answers ‘how’ it does it.
简而言之，体系结构回答计算机’做什么’，而组织回答它’怎么做’。
2. The Von Neumann Architecture | 冯·诺依曼体系结构
The Von Neumann architecture, proposed by John von Neumann in 1945, is the foundation of most modern computers. Its defining feature is the stored-program concept, where both instructions and data are stored in the same memory unit.
冯·诺依曼体系结构由约翰·冯·诺依曼于1945年提出，是现代大多数计算机的基础。其定义性特征是存储程序概念，即指令和数据存储在同一存储单元中。
Key components of this architecture include a single memory unit, a control unit, an arithmetic logic unit (ALU), and input/output devices. The system communicates through a single bus system, which means instructions and data cannot be fetched simultaneously.
该体系结构的关键组件包括单一存储单元、控制单元、算术逻辑单元（ALU）和输入/输出设备。系统通过单一总线系统通信，这意味着指令和数据无法同时获取。
CPU = ALU + CU + Registers
This sequential processing model is simple and flexible, but it suffers from the ‘Von Neumann bottleneck’ — the limited data transfer rate between the CPU and memory.
这种顺序处理模型简单而灵活，但存在’冯·诺依曼瓶颈’——CPU与存储器之间的数据传输速率受限。
3. The Harvard Architecture | 哈佛体系结构
The Harvard architecture uses physically separate storage and signal pathways for instructions and data. Each memory unit has its own dedicated bus system.
哈佛体系结构为指令和数据使用物理上分离的存储和信号通路。每个存储单元都有自己专用的总线系统。
The main advantage is that the CPU can read an instruction and fetch data simultaneously, improving throughput and performance. This is why Harvard architecture is widely used in embedded systems and digital signal processors (DSPs).
其主要优点是CPU可以同时读取指令和获取数据，从而提高吞吐量和性能。这就是哈佛体系结构被广泛用于嵌入式系统和数字信号处理器（DSP）的原因。
However, the cost and complexity are higher due to duplicated circuitry and buses. A modified Harvard architecture, used in most modern CPUs, separates instruction and data caches while still sharing main memory.
然而，由于电路和总线的重复，成本和复杂性更高。大多数现代CPU使用改进型哈佛体系结构，在共享主存储器的同时分离指令和数据缓存。
4. Central Processing Unit: Core Components | 中央处理器：核心组件
The ALU is responsible for arithmetic operations such as addition, subtraction, multiplication, and division, as well as logical operations such as AND, OR, NOT, and XOR. It contains registers like the accumulator (ACC) to hold intermediate results.
ALU负责算术运算，如加、减、乘、除，以及逻辑运算，如与、或、非和异或。它包含累加器（ACC）等寄存器来保存中间结果。
The control unit (CU) orchestrates the operation of the entire computer. It fetches instructions from memory, decodes them, and generates control signals to direct other components. The CU uses a clock signal to synchronise all operations.
控制单元（CU）协调整个计算机的运行。它从存储器中取指令、对指令进行译码，并生成控制信号来指挥其他组件。CU使用时钟信号来同步所有操作。
Registers are small, high-speed storage locations within the CPU that temporarily store data, addresses, and control information during processing. They are significantly faster than main memory.
寄存器是CPU内小型、高速的存储位置，用于在处理过程中临时存储数据、地址和控制信息。它们比主存储器快得多。
The system clock generates periodic electronic pulses that synchronise activities. Clock speed, measured in hertz (Hz), determines the number of fetch-execute cycles performed per second.
系统时钟产生周期性电子脉冲来同步各项活动。时钟速度以赫兹（Hz）为单位，决定了每秒执行的取指-执行周期次数。
5. CPU Registers in Detail | CPU寄存器详解
Program Counter (PC): Holds the memory address of the next instruction to be fetched. After each instruction is fetched, the PC is updated to point to the subsequent instruction.
程序计数器（PC）：保存下一条待取指令的存储器地址。每取出一条指令后，PC被更新以指向后续指令。
Memory Address Register (MAR): Stores the address of the memory location currently being read from or written to. It connects directly to the address bus.
存储器地址寄存器（MAR）：存储当前正在读取或写入的存储单元地址。它直接连接到地址总线。
Memory Data Register (MDR): Also known as the Memory Buffer Register (MBR), it holds the data being transferred between the CPU and memory. It connects to the data bus.
存储器数据寄存器（MDR）：也称为存储器缓冲寄存器（MBR），保存CPU与存储器之间正在传输的数据。它连接到数据总线。
Accumulator (ACC): A general-purpose register that stores the result of operations performed by the ALU. In simple processors, it is the primary working register.
累加器（ACC）：一个通用寄存器，用于存储ALU执行运算的结果。在简单处理器中，它是主要的工作寄存器。
Current Instruction Register (CIR): Holds the instruction that has just been fetched from memory while it is being decoded and executed by the control unit.
当前指令寄存器（CIR）：保存刚从存储器取出、正在由控制单元译码和执行的指令。
Status Register (SR): Also called the flag register, it contains individual bits that indicate the status of the processor, such as zero flag, carry flag, and overflow flag.
状态寄存器（SR）：也称为标志寄存器，包含指示处理器状态的各个位，如零标志、进位标志和溢出标志。
6. The Fetch-Decode-Execute Cycle | 取指-译码-执行周期
The fetch-decode-execute cycle is the fundamental process by which a CPU executes instructions. It consists of three main phases and repeats continuously.
取指-译码-执行周期是CPU执行指令的基本过程。它由三个主要阶段组成并不断重复。
Fetch phase: The address in the PC is copied to the MAR. The instruction at that address is loaded into the MDR via the data bus. The instruction is then transferred to the CIR. Finally, the PC is incremented to point to the next instruction.
取指阶段：PC中的地址被复制到MAR。该地址处的指令通过数据总线载入MDR。指令随后被传送到CIR。最后，PC递增以指向下一条指令。
Decode phase: The control unit interprets the opcode and operands of the instruction in the CIR. It determines what operations are required and which components are involved.
译码阶段：控制单元解释CIR中指令的操作码和操作数。它确定需要哪些操作以及涉及哪些组件。
Execute phase: The CU issues control signals to perform the operation. This may involve the ALU performing calculations, reading from or writing to memory, or transferring data between registers.
执行阶段：CU发出控制信号来执行操作。这可能涉及ALU执行计算、从存储器读写，或在寄存器之间传输数据。
The cycle repeats for each instruction. The time taken to complete one full cycle is called an instruction cycle, which is measured in clock cycles.
该周期对每条指令重复进行。完成一个完整周期所需的时间称为指令周期，以时钟周期来衡量。
7. System Buses | 系统总线
A bus is a set of parallel wires or pathways that transmit data, addresses, and control signals between hardware components. There are three main types of buses in a typical computer system.
总线是一组在硬件组件之间传输数据、地址和控制信号的并行线路或通路。典型计算机系统中有三种主要类型的总线。
Address Bus: Carries memory addresses from the CPU to memory or I/O devices. It is unidirectional. The width of the address bus determines the maximum addressable memory capacity — an n-bit address bus can address 2ⁿ memory locations.
地址总线：将存储地址从CPU传送到存储器或I/O设备。它是单向的。地址总线的宽度决定最大可寻址存储容量——n位地址总线可寻址2ⁿ个存储单元。
Data Bus: Carries actual data between the CPU, memory, and I/O devices. It is bidirectional. The width of the data bus determines the word length of the processor — a 64-bit data bus can transfer 64 bits of data per bus cycle.
数据总线：在CPU、存储器和I/O设备之间传输实际数据。它是双向的。数据总线的宽度决定处理器的字长——64位数据总线每个总线周期可传输64位数据。
Control Bus: Carries control signals generated by the CU, such as read/write commands, interrupts, and clock signals. It ensures that all operations occur in the correct sequence and that simultaneous access to the bus is controlled.
控制总线：传输由CU生成的控制信号，如读/写命令、中断和时钟信号。它确保所有操作按正确顺序发生，并控制对总线的同时访问。
8. Main Memory and Cache | 主存储器与缓存
Main memory, also known as random access memory (RAM), stores both data and instructions that the CPU is currently using. RAM is volatile — its contents are lost when the power is switched off. Read-only memory (ROM) is non-volatile and stores the bootstrap loader and BIOS.
主存储器，也称为随机存取存储器（RAM），存储CPU当前正在使用的数据和指令。RAM是易失性的——断电后其内容会丢失。只读存储器（ROM）是非易失性的，存储引导加载程序和BIOS。
Cache memory is a small, high-speed memory located between the CPU and main memory. It stores frequently accessed data and instructions to reduce the average memory access time.
缓存存储器是位于CPU和主存储器之间的小型高速存储器。它存储频繁访问的数据和指令，以减少平均存储器访问时间。
The principle of locality states that programs tend to access the same memory locations repeatedly (temporal locality) and access nearby locations (spatial locality). Cache exploits this principle to predict which data will be needed next.
局部性原理指出，程序往往重复访问相同存储位置（时间局部性）并访问附近位置（空间局部性）。缓存利用该原理来预测接下来需要哪些数据。
Cache levels are organised hierarchically: Level 1 (L1) cache is the fastest and smallest, typically 16-64 KB; Level 2 (L2) cache is larger but slower; Level 3 (L3) cache is shared among cores and is even larger.
缓存级别按层次组织：一级（L1）缓存最快且最小，通常为16-64 KB；二级（L2）缓存更大但较慢；三级（L3）缓存由多个核心共享，且更大。
9. Input/Output and Storage | 输入/输出与存储
Input devices such as keyboards, mice, and sensors convert external data into digital signals that the computer can process. Output devices such as monitors, printers, and speakers convert digital signals back into human-readable forms.
键盘、鼠标和传感器等输入设备将外部数据转换为计算机可处理的数字信号。显示器、打印机和扬声器等输出设备将数字信号转换回人类可读的形式。
I/O controllers act as interfaces between the CPU and peripheral devices. They buffer data, handle device-specific protocols, and send interrupts to the CPU when they are ready for data transfer.
I/O控制器充当CPU与外围设备之间的接口。它们缓冲数据、处理设备特定的协议，并在准备数据传输时向CPU发送中断。
Memory-mapped I/O treats I/O devices as memory locations, allowing the CPU to use the same instructions for data transfer. Direct memory access (DMA) allows devices to transfer data directly to and from memory without CPU intervention, freeing the CPU for other tasks.
存储器映射I/O将I/O设备视为存储单元，允许CPU使用相同的指令进行数据传输。直接存储器访问（DMA）允许设备直接与存储器之间传输数据，无需CPU干预，从而使CPU可以处理其他任务。
10. Pipelining and Performance | 流水线与性能
Pipelining is a technique where multiple instructions are in different stages of the fetch-decode-execute cycle simultaneously. This is analogous to an assembly line: while one instruction is being executed, the next is being decoded, and the one after that is being fetched.
流水线是一种技术，使多条指令同时处于取指-译码-执行周期的不同阶段。这类似于流水线作业：当一条指令在执行时，下一条正在被译码，再下一条正在被读取。
A three-stage pipeline can theoretically complete three instructions in the same time it would normally take to complete one. The throughput of the processor increases, although the latency of individual instructions remains unchanged.
三级流水线理论上可以在通常执行完一条指令的时间内完成三条指令。处理器的吞吐量增加，尽管单条指令的延迟保持不变。
Pipelining faces several hazards: structural hazards occur when hardware resources are insufficient; data hazards occur when instructions depend on incomplete results; control hazards occur when branch instructions change the sequential flow.
流水线面临若干风险：结构风险在硬件资源不足时发生；数据风险在指令依赖尚未完成的结果时发生；控制风险在分支指令改变顺序流程时发生。
Other factors affecting CPU performance include the number of cores, clock speed, cache size, and instruction set efficiency. Increasing the clock speed raises power consumption and heat, which may require additional cooling.
影响CPU性能的其他因素包括核心数量、时钟速度、缓存大小和指令集效率。提高时钟速度会增加功耗和热量，可能需要额外的散热措施。
11. RISC vs CISC | 精简指令集计算与复杂指令集计算
Reduced Instruction Set Computing (RISC) uses a small, highly optimised set of instructions. Each instruction executes in a single clock cycle, and the processor uses a large number of registers to reduce memory access.
精简指令集计算（RISC）使用小型、高度优化的指令集。每条指令在一个时钟周期内执行，处理器使用大量寄存器以减少存储器访问。
Complex Instruction Set Computing (CISC) uses a large, complex instruction set where individual instructions may perform multiple operations and take multiple clock cycles to complete. This makes the assembly code shorter but the hardware more complex.
复杂指令集计算（CISC）使用大型、复杂的指令集，其中单条指令可能执行多项操作并需要多个时钟周期才能完成。这使得汇编代码更短，但硬件更复杂。
Modern processors often use a hybrid approach: CISC-style instruction sets are decoded internally into RISC-like micro-operations, combining the benefits of both designs.
现代处理器通常使用混合方法：将CISC风格的指令集在内部译码为类似RISC的微操作，从而结合两种设计的优点。
| Feature | 特征 | RISC | CISC |
|---|---|---|
| Instruction length | 指令长度 | Fixed | 固定 | Variable | 可变 |
| Clock cycles per instruction | 每条指令时钟周期 | 1 | Multiple | 多个 |
| Hardware control | 硬件控制 | Simpler | 较简单 | Complex | 复杂 |
| Registers | 寄存器 | Many | 多 | Few | 少 |
12. Addressing Modes and Interrupts | 寻址方式与中断
Addressing modes define how the CPU calculates the effective address of an operand. Immediate addressing uses a constant value directly in the instruction. Direct addressing specifies the exact memory address of the operand.
寻址方式定义CPU如何计算操作数的有效地址。立即寻址在指令中直接使用常量值。直接寻址指定操作数的确切存储地址。
Indirect addressing stores the address of the operand in a register or memory location, requiring an extra memory access. Indexed addressing adds a constant value to an index register to compute the effective address, which is useful for array processing.
间接寻址将操作数的地址存储在寄存器或存储单元中，需要额外访问一次存储器。变址寻址将常量值与变址寄存器相加来计算有效地址，可有效支持数组处理。
An interrupt is a signal that temporarily suspends the normal execution of the CPU to handle an urgent event, such as a read from an I/O device or a timer signal. When an interrupt occurs, the CPU saves the current state, executes the interrupt service routine (ISR), and then restores the state to resume the interrupted program.
中断是一种信号，用于暂时挂起CPU的正常执行以处理紧急事件，如来自I/O设备的读取或定时器信号。当中断发生时，CPU保存当前状态、执行中断服务程序（ISR），然后恢复状态以继续被中断的程序。
Understanding interrupts is essential for grasping how operating systems manage multitasking, handling multiple processes efficiently by prioritising time-sensitive operations.
理解中断对于掌握操作系统如何管理多任务至关重要，系统通过优先处理时间敏感的操作来高效地管理多个进程。
In summary, computer architecture provides the blueprint that connects hardware components into a functional computing system. Mastering its core concepts — from the CPU components and instruction cycle to memory hierarchy and processor design philosophies — is essential for every A-level computer science student.
总之，计算机体系结构为我们提供了将硬件组件连接成功能完善的计算系统的蓝图。掌握其核心概念——从CPU组件和指令周期到存储层次结构和处理器设计理念——对每一位A-level计算机科学学生都至关重要。
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