Stored Program & Instruction Execution | 存储程序与指令执行

📚 Stored Program & Instruction Execution | 存储程序与指令执行

The stored program concept is one of the most fundamental ideas in computer science. It states that both instructions and data are stored in the same memory unit, and the CPU fetches, decodes, and executes instructions one at a time in a cyclic manner. This article breaks down the complete instruction execution cycle, the registers involved, and the key examination points you must master.

存储程序概念是计算机科学中最基础的思想之一。它指出指令和数据存储在同一个存储器中，CPU 按照取指、译码、执行的循环方式逐条处理指令。本文将从考点出发，拆解完整的指令执行周期、涉及的寄存器以及你必须掌握的考试要点。

1. The Stored Program Concept | 存储程序概念

The stored program concept, first proposed by John von Neumann in the 1940s, means that a computer’s program instructions and the data they operate on are both held in the same read-write memory. The CPU treats them identically in terms of storage, but distinguishes them by context during execution. This design allows a computer to be reprogrammed without changing any hardware.

存储程序概念由约翰·冯·诺依曼于 20 世纪 40 年代首次提出，意思是计算机的程序指令及其操作的数据都存放在同一个可读写存储器中。CPU 在存储层面平等对待它们，但在执行时根据上下文加以区分。这种设计使得计算机无需更换任何硬件即可重新编程。

Instructions + Data → Same Memory → CPU Fetches → Decodes → Executes

指令 + 数据 → 同一存储器 → CPU 取指 → 译码 → 执行

This concept contrasts with earlier systems where programs were hardwired. The key exam point is that a stored program can be loaded into memory and executed, which gives computers their flexibility and general-purpose nature.

这一概念与早期程序硬连线的系统形成对比。考点的关键是：存储程序可以装入内存并执行，从而使计算机具备灵活性和通用性。

2. The Von Neumann Architecture | 冯·诺依曼体系结构

The von Neumann architecture is built around a single shared memory for both instructions and data, a single bus system for transferring data and instructions, and a control unit that orchestrates the fetch-decode-execute cycle. Its main limitation is the von Neumann bottleneck: the single bus can only carry either an instruction or a piece of data at any one moment, which limits throughput.

冯·诺依曼体系结构围绕一个指令和数据共享的存储器、一套用于传输数据和指令的总线系统，以及一个协调取指-译码-执行周期的控制单元来构建。其主要局限是“冯·诺依曼瓶颈”：单一总线在同一时刻只能传输一条指令或一份数据，从而限制了吞吐量。

Single memory space for both instructions and data. | 指令与数据共享同一存储空间。
One bus system shared between data and instructions. | 数据与指令共用一套总线系统。
Sequential execution of instructions. | 指令按顺序依次执行。
Bottleneck caused by the shared bus. | 共享总线导致瓶颈效应。

3. CPU Registers Involved in Instruction Execution | 参与指令执行的 CPU 寄存器

During the instruction cycle, several special-purpose registers work together. You must know each register’s full name, its abbreviation, and its exact role.

在指令周期中，多个专用寄存器协同工作。你必须熟记每个寄存器的全称、缩写及其精确作用。

Register \| 寄存器	Full Name \| 全称	Role \| 作用
PC	Program Counter 程序计数器	Holds the address of the next instruction to be fetched. 保存下一条待取指令的地址。
MAR	Memory Address Register 内存地址寄存器	Holds the address of the memory location being accessed. 保存正在访问的内存地址。
MDR	Memory Data Register 内存数据寄存器	Holds data or instructions read from or written to memory. 保存从内存读出或写入内存的数据或指令。
CIR	Current Instruction Register 当前指令寄存器	Holds the instruction currently being decoded and executed. 保存正在译码和执行中的指令。
ACC	Accumulator 累加器	Stores intermediate results of arithmetic and logic operations. 存储算术与逻辑运算的中间结果。

4. The Fetch Stage | 取指阶段

In the fetch stage, the CPU obtains the instruction from memory. The address of the instruction is held in the PC and is copied into the MAR. The control unit then issues a read signal, and the instruction at that address is placed on the data bus and loaded into the MDR. Finally, the instruction is transferred from the MDR to the CIR for decoding.

在取指阶段，CPU 从内存获取指令。指令地址保存在 PC 中，并被复制到 MAR。控制单元随即发出读信号，该地址处的指令被放到数据总线上并载入 MDR。最后，指令从 MDR 传送到 CIR 以便译码。

PC → MAR → Read Memory → MDR → CIR

PC → MAR → 读内存 → MDR → CIR

During the fetch stage, the PC is also incremented to point to the next instruction, unless a branch or jump occurs later. This increment can happen before or after the instruction is executed, depending on the architecture. Most exam boards expect that the PC increments during the fetch stage so that a sequential program flows naturally.

取指阶段中，PC 也会递增以指向下一条指令，除非后续发生分支或跳转。递增可以发生在指令执行之前或之后，具体取决于体系结构。大多数考试局要求掌握：PC 在取指阶段递增，从而让顺序程序得以自然流动。

5. The Decode Stage | 译码阶段

Once the instruction is in the CIR, the control unit examines the opcode to determine what operation is required. The instruction format typically consists of an opcode and an operand. The opcode specifies the operation, such as LOAD, ADD, STORE, or BRANCH. The operand specifies the address or value on which the operation is performed.

当指令进入 CIR 后，控制单元检查操作码以确定需要执行什么操作。指令格式通常由操作码和操作数组成。操作码指明操作类型，如 LOAD（装载）、ADD（加法）、STORE（存储）或 BRANCH（分支）。操作数指明操作所作用的地止或数值。

Instruction = Opcode + Operand | 指令 = 操作码 + 操作数

Opcode: defines the operation (e.g., ADD). 操作码：定义操作类型（如 ADD）。
Operand: defines the data or address used. 操作数：定义使用的数据或地址。
Decoding is performed by the control unit in the CPU. 译码由 CPU 中的控制单元完成。

6. The Execute Stage | 执行阶段

During the execute stage, the control unit sends signals to the appropriate components to carry out the operation. For example, if the instruction is ADD, the ALU fetches the value from the specified address, adds it to the accumulator, and stores the result back in the accumulator. If the instruction is a branch, the PC is updated to a new address.

在执行阶段，控制单元向相应部件发送信号以完成操作。例如，如果指令是 ADD，ALU 从指定地址取值，将其与累加器中的值相加，并将结果存回累加器。如果指令是分支指令，PC 将被更新为一个新地址。

Execute: ALU performs Arithmetic/Logic Operation | 执行：ALU 进行算术/逻辑运算

For LOAD instructions, data moves from memory into the accumulator. For STORE instructions, data moves from the accumulator to memory. For BRANCH instructions, the PC is overwritten with a new address, either unconditionally or conditionally based on a flag such as zero or negative.

对于 LOAD 指令，数据从内存移入累加器；对于 STORE 指令，数据从累加器写入内存；对于 BRANCH 指令，PC 被覆盖为新地址，可以是无条件分支，也可以根据零标志或负标志等条件进行条件分支。

7. The Complete Instruction Cycle | 完整指令周期

The complete cycle can be summarised as follows. Note carefully the order of operations and the role of each register.

完整周期可总结如下。请务必注意操作顺序和每个寄存器的角色。

Step \| 步骤	Action \| 动作	Registers Involved \| 涉及寄存器
1	The address in PC is copied to MAR. PC 中的地址复制到 MAR。	PC, MAR
2	The instruction at that address is read from memory into MDR. 该地址的指令从内存读入 MDR。	MAR, MDR, Memory
3	The instruction is moved from MDR to CIR. 指令从 MDR 移入 CIR。	MDR, CIR
4	PC is incremented to point to the next instruction. PC 递增以指向下一条指令。	PC
5	The control unit decodes the opcode in CIR. 控制单元对 CIR 中的操作码进行译码。	Control Unit, CIR
6	The instruction is executed (e.g., ALU operation or branch). 执行指令（如 ALU 运算或分支）。	ALU, ACC, PC, Memory

8. Worked Example: Loading a Value | 示例：装载一个数值

Consider the machine code instruction LDA #4, which means “load the value 4 into the accumulator.” The hash symbol indicates immediate addressing — the operand itself is the value, not an address. Let us trace the cycle. Suppose the instruction is stored at memory address 200.

考虑机器指令 LDA #4，意思是“将数值 4 装入累加器”。井号表示立即寻址——操作数本身就是值，而不是地址。我们来追踪这个周期。假设指令存储在地止 200。

Memory[200] = LDA #4 → PC = 200 initially

内存[200] = LDA #4 → PC 初始为 200

PC holds 200, which is copied to MAR. PC 保存 200，复制到 MAR。
The control unit reads memory address 200, and the instruction LDA #4 enters the MDR. 控制单元读取内存地止 200，指令 LDA #4 进入 MDR。
The instruction moves from MDR into CIR for decoding. 指令从 MDR 移入 CIR 进行译码。
PC increments to 201, ready for the next instruction. PC 递增至 201，为下一条指令做好准备。
The control unit decodes LDA and recognizes immediate addressing. 控制单元译码 LDA 并识别立即寻址。
The value 4 is loaded into the accumulator. 数值 4 被装入累加器。

This type of trace question is extremely common in exams. You should be able to state what each register contains at each stage of the cycle.

这类追踪题在考试中极其常见。你应当能够说出每个阶段每个寄存器的内容。

9. Immediate vs Direct Addressing | 立即寻址与直接寻址

Many instruction execution questions test your understanding of addressing modes. Immediate addressing means the operand is a constant value directly inside the instruction. Direct addressing means the operand is the address of a memory location where the actual data is stored.

许多指令执行题考查你对寻址方式的理解。立即寻址表示操作数是直接写在指令中的常量；直接寻址表示操作数是实际数据所在的内存地址。

Feature \| 特征	Immediate \| 立即寻址	Direct \| 直接寻址
Operand means \| 操作数含义	The value itself 数值本身	The address of the value 数值的地址
Example \| 示例	LDA #4	LDA 200
Memory access \| 访存次数	0 additional memory reads 无额外内存读取	1 additional memory read 有 1 次额外内存读取
Speed \| 速度	Faster 更快	Slower 更慢

Examiners often ask you to compare these modes and explain trade-offs. Immediate addressing is fast but inflexible; direct addressing is slower but allows data to be stored and updated in memory.

考官经常要求你比较这些方式并解释取舍。立即寻址快但不够灵活；直接寻址较慢但允许数据在内存中存储和更新。

10. The Role of the ALU and Control Unit | ALU 与控制单元的角色

The Arithmetic and Logic Unit (ALU) performs arithmetic calculations such as ADD, SUBTRACT, MULTIPLY, DIVIDE, and logical operations such as AND, OR, NOT, and comparisons. All data flowing through the ALU passes through the accumulator, which acts as both a source and a destination register.

算术逻辑单元（ALU）执行算术运算，如加、减、乘、除，以及逻辑运算，如 AND、OR、NOT 和比较。所有流经 ALU 的数据都经过累加器，累加器同时充当源寄存器和目的寄存器。

The Control Unit (CU) coordinates all operations. It generates timing signals, controls the fetch-decode-execute cycle, decodes instructions, and manages the flow of data between the CPU, memory, and I/O devices.

控制单元（CU）协调所有操作。它生成时序信号，控制取指-译码-执行周期，译码指令，并管理 CPU、内存和 I/O 设备之间的数据流。

11. Interrupts and the Instruction Cycle | 中断与指令周期

An interrupt is a signal that causes the CPU to suspend its current instruction cycle and handle a separate event, such as a keyboard press or a hardware failure. When an interrupt occurs, the CPU finishes the current instruction, saves the state (including the PC value) onto the stack, and jumps to the interrupt service routine. After the routine completes, the saved PC is restored, and execution resumes.

中断是一种信号，导致 CPU 暂停当前指令周期去处理一个独立事件，例如按键或硬件故障。当中断发生时，CPU 完成当前指令，将状态（包括 PC 值）保存到堆栈，并跳转到中断服务程序。服务程序完成后，保存的 PC 被恢复，执行继续。

Check for interrupts is typically done after the execute stage. 中断检查通常在执行阶段之后进行。
PC and status flags are saved. PC 和状态标志被保存。
The CPU loads the address of the interrupt handler. CPU 装入中断处理程序的地址。
Process is known as “saving state” and “context switch”. 这一过程称为“保存状态”与“上下文切换”。

12. Pipelining and Performance | 流水线与性能

Pipelining is a technique where multiple instructions are in different stages of the instruction cycle simultaneously. While one instruction is being executed, the next is being decoded, and the one after that is being fetched. This does not reduce the execution time of a single instruction but increases throughput.

流水线技术让多条指令同时处于指令周期的不同阶段。当一条指令在执行时，下一条正在译码，再下一条正在取指。这并不会减少单条指令的执行时间，但会提高吞吐量。

Fetch Instruction 1 → Fetch Instruction 2 → Fetch Instruction 3

Decode Instruction 1 → Decode Instruction 2 → Decode Instruction 3

Execute Instruction 1 → Execute Instruction 2 → Execute Instruction 3

取指指令1 → 取指指令2 → 取指指令3

译码指令1 → 译码指令2 → 译码指令3

执行指令1 → 执行指令2 → 执行指令3

The main obstacles to pipelining are hazards: data hazards (an instruction depends on the result of a previous one), structural hazards (competing for the same hardware), and control hazards (branch instructions that change the flow).

流水线的主要障碍是冒险：数据冒险（指令依赖前一条指令的结果）、结构冒险（竞争同一硬件）和控制冒险（改变流程的分支指令）。

13. Common Exam Mistakes | 常见考试错误

The following errors are frequently seen in exam scripts. Avoid them to secure full marks.

以下错误在考试答卷中频繁出现。避免这些错误可争取满分。

Confusing MAR and MDR: MAR holds the address; MDR holds the data. 混淆 MAR 与 MDR：MAR 保存地址，MDR 保存数据。
Stating PC increments after execution instead of during fetch. 错误地说 PC 在执行后递增，而非在取指阶段递增。
Forgetting that immediate addressing does not access memory for data. 忘记立即寻址不需要访问内存来获取数据。
Writing “register” instead of naming the exact register. 只写“寄存器”而不写出具体寄存器名称。
Describing ACC as holding memory addresses instead of data values. 错误地把 ACC 描述为保存内存地址而不是数据值。
Omitting the stack when describing interrupt handling. 描述中断处理时遗漏堆栈的作用。

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Stored Program & Instruction Execution | 存储程序与指令执行