Computer Architecture and Organization | 计算机体系结构与组成原理

📚 Computer Architecture and Organization | 计算机体系结构与组成原理

Computer architecture and organization forms the foundational pillar of computer science, encompassing how hardware components are structured and how they interact to execute instructions. This revision guide covers the essential concepts that appear consistently in A-Level and IGCSE examinations.

计算机体系结构与组成原理是计算机科学的基础支柱，涵盖了硬件组件如何构建以及它们如何相互作用以执行指令。本复习指南涵盖A-Level和IGCSE考试中经常出现的基本概念。

1. Von Neumann Architecture | 冯·诺依曼体系结构

The Von Neumann architecture, proposed by John von Neumann in 1945, describes a system where data and instructions share the same memory and are accessed through a single bus. This architecture features a central processing unit (CPU), a memory unit, and input/output devices connected by a system bus.

冯·诺依曼体系结构由约翰·冯·诺依曼于1945年提出，描述了数据和指令共享同一内存并通过单一总线访问的系统。该体系结构包含中央处理器（CPU）、存储单元以及通过系统总线连接的输入/输出设备。

Key characteristics of the Von Neumann model include:

冯·诺依曼模型的关键特征包括：

Single shared memory for both instructions (program) and data — 指令（程序）和数据共用同一存储空间；
Sequential execution of instructions — 指令按顺序依次执行；
The “stored program” concept — instructions are loaded into memory and executed one after another — “存储程序”概念，即指令先加载到内存中再逐条执行；
A single system bus that carries data, addresses, and control signals, creating the “Von Neumann bottleneck” — 单一系统总线承载数据、地址和控制信号，由此产生“冯·诺依曼瓶颈”。

Memory → CPU → I/O Devices (single bus, shared storage)

内存 → CPU → 输入/输出设备（单总线、共享存储）

2. Harvard Architecture | 哈佛体系结构

The Harvard architecture physically separates instruction memory from data memory, allowing the CPU to fetch an instruction and read/write data simultaneously. This eliminates the contention that occurs in Von Neumann systems where the bus must be shared between instruction fetches and data transfers.

哈佛体系结构将指令存储器和数据存储器在物理上分开，使CPU可以同时取指令和读写数据。这消除了冯·诺依曼体系中指令获取与数据传输必须共享总线而产生的争用问题。

Feature \| 特征	Von Neumann \| 冯·诺依曼	Harvard \| 哈佛
Memory 存储器	Single shared memory 单一共享存储	Separate data & instruction 数据与指令分离
Bus 总线	One bus 单一总线	Two busses 双总线
Speed 速度	Slower (bottleneck) 较慢（瓶颈）	Faster (parallel access) 较快（并行访问）
Typical use 典型用途	General-purpose computers 通用计算机	Embedded systems, DSP 嵌入式系统、数字信号处理

3. CPU Components | CPU 核心组件

The central processing unit (CPU) is composed of several key sub-units that collaborate to process data. Understanding the function of each component is essential for answering architecture questions in examinations.

中央处理器（CPU）由多个关键子单元组成，这些子单元协同工作以处理数据。理解每个组件的功能对于回答考试中的体系结构题目至关重要。

Arithmetic Logic Unit (ALU) 算术逻辑单元: Performs arithmetic operations (addition, subtraction) and logical operations (AND, OR, NOT, comparison). 执行算术运算（加法、减法）和逻辑运算（与、或、非、比较）。
Control Unit (CU) 控制单元: Decodes instructions and generates control signals that direct the operation of all other hardware components. 对指令进行译码并生成控制信号，指挥其他所有硬件组件的运行。
Registers 寄存器: Small, ultra-fast storage locations inside the CPU used to hold temporary data, addresses, and instruction information. CPU内部容量极小但速度极快的存储位置，用于保存临时数据、地址和指令信息。
Clock 时钟: Generates a synchronizing signal that regulates the timing of all CPU operations. 产生同步信号，调节CPU所有操作的时序。
Cache memory 高速缓存: Small but very fast memory located on or near the CPU chip, storing frequently accessed data to reduce latency. 位于CPU芯片之上或附近的容量小但速度极快的存储器，用于存储频繁访问的数据以减少延迟。

The most important registers include the Program Counter (PC), which holds the address of the next instruction, and the Memory Address Register (MAR), which holds the address of the memory location currently being accessed.

最重要的寄存器包括程序计数器（PC），它保存下一条指令的地址，以及内存地址寄存器（MAR），它保存当前正在访问的内存位置的地址。

4. The Fetch-Decode-Execute Cycle | 取指-译码-执行周期

The fetch-decode-execute (FDE) cycle is the fundamental operating loop of the CPU. Each machine instruction passes through these three stages, and the Program Counter is updated before or after each cycle to point to the next instruction.

取指-译码-执行（FDE）周期是CPU的基本运行循环。每条机器指令都经历这三个阶段，程序计数器在每轮周期之前或之后被更新以指向下一条指令。

Stage 1 — Fetch (取指阶段): The address held in the PC is copied to the MAR. The referenced instruction is retrieved from memory and placed into the Memory Data Register (MDR), then loaded into the Current Instruction Register (CIR). The PC is then incremented by 1.

阶段1 — 取指：PC中保存的地址被复制到MAR。引用的指令从内存中取出并放入内存数据寄存器（MDR），然后加载到当前指令寄存器（CIR）。之后PC自动加1。

Stage 2 — Decode (译码阶段): The Control Unit decodes the instruction in the CIR to determine which operation must be performed and what operands are required.

阶段2 — 译码：控制单元对CIR中的指令进行译码，以确定需要执行何种操作以及需要哪些操作数。

Stage 3 — Execute (执行阶段): The ALU performs the required arithmetic or logical operation. The result is written back to a register or to memory as specified by the instruction. Any required address calculations are also completed at this stage.

阶段3 — 执行：ALU执行所需的算术或逻辑操作。结果按指令规定写回到寄存器或内存中。所需的地址计算也在该阶段完成。

Fetch → Decode → Execute → (repeat cycle) | 取指 → 译码 → 执行 →（循环重复）

5. Memory Hierarchy | 存储层次结构

Modern computing systems rely on a memory hierarchy to balance speed, capacity, and cost. Memory that is closer to the CPU is faster but more expensive per unit of capacity, whereas memory further away is slower but cheaper.

现代计算系统依赖存储层次结构来平衡速度、容量和成本。距离CPU越近的存储器速度越快，但单位容量成本更高；距离越远的存储器速度越慢，但成本更低。

Level 层级	Type 类型	Speed 速度	Capacity 容量
1 (Fastest 最快)	CPU Registers 寄存器	1 cycle 1个周期	Bytes 字节级
2	Cache (L1/L2/L3) 高速缓存	Few cycles 数个周期	KB – MB
3	Main Memory (RAM) 主存储器（RAM）	Hundreds of cycles 数百个周期	GB 吉字节级
4 (Slowest 最慢)	Secondary Storage 辅助存储	Milliseconds 毫秒级	TB 太字节级

Memory is divided into primary memory (RAM and ROM), which the CPU can access directly, and secondary storage (magnetic, optical, solid-state), which is non-volatile and used for long-term data persistence. Virtual memory extends the usable address space by paging parts of secondary storage as if they were RAM.

存储器分为CPU可直接访问的主存储器（RAM和ROM），以及非易失性、用于长期数据持久化的辅助存储器（磁介质、光介质、固态介质）。虚拟内存通过将辅助存储的部分内容分页到内存地址空间来扩展可用地址空间。

6. Addressing Modes | 寻址方式

Addressing modes define how the CPU locates an operand in memory. Each mode has different speed and flexibility trade-offs, and examination questions frequently require comparison between them.

寻址方式定义了CPU如何在内存中定位操作数。每种方式在速度和灵活性方面各有取舍，考试题目经常要求对其进行对比。

Immediate addressing 立即寻址: The operand is contained directly in the instruction itself. Fast but limited to constants. 操作数直接包含在指令中。速度快但仅限于常量。
Direct addressing 直接寻址: The instruction contains the actual memory address of the operand. 指令中包含操作数的实际内存地址。
Indirect addressing 间接寻址: The instruction contains the address of the memory location that holds the address of the operand. 指令中包含的内存地址存储的是操作数的地址。
Indexed addressing 变址寻址: The effective address is calculated by adding an index register value to a base address contained in the instruction. Useful for array traversal. 有效地址通过将指令中的基地址与变址寄存器中的值相加得到。适用于数组遍历。
Relative addressing 相对寻址: The operand address is computed relative to the Program Counter, supporting efficient branching. 操作数地址是相对于程序计数器计算出来的，支持高效的分支操作。

Effective Address = Instruction Address + Index Register (for indexed mode)

有效地址 = 指令地址 + 变址寄存器值（用于变址寻址）

7. Buses in the System | 系统总线

A bus is a collection of parallel wires or pathways that transmit data between components inside the computer. The three primary buses that connect the CPU, memory, and I/O controllers are the address bus, the data bus, and the control bus.

总线是计算机内部各组件之间传输数据的一组并行线路或通路。连接CPU、内存和I/O控制器的三条主要总线是地址总线、数据总线和控制总线。

Address bus 地址总线: Carries the memory address selected by the CPU. It is unidirectional (CPU to memory/I/O). Its width determines the maximum addressable memory. 传输CPU选定的内存地址。它是单向的（从CPU到内存/I/O）。其宽度决定最大可寻址内存范围。
Data bus 数据总线: Carries the actual data being transferred between components. It is bidirectional, and its width (e.g., 32-bit or 64-bit) affects the processing speed. 传输组件之间交换的实际数据。它是双向的，其宽度（如32位或64位）影响处理速度。
Control bus 控制总线: Carries control signals such as read/write commands, clock pulses, and interrupt requests. These signals coordinate and synchronise the entire system. 传输读/写命令、时钟脉冲和中断请求等控制信号，用于协调和同步整个系统。

For example, a CPU with a 32-bit address bus can access up to 2³² = 4 GB of memory locations, because each unique address combination maps to one memory cell.

例如，拥有32位地址总线的CPU最多可以访问2³² = 4 GB的内存空间，因为每一个唯一的地址组合对应一个存储单元。

Maximum addressable memory = 2ⁿ bytes (where n = address bus width)

最大可寻址内存 = 2ⁿ 字节（n = 地址总线宽度）

8. RISC vs CISC | 精简指令集与复杂指令集

Instruction set design follows two fundamental philosophies: Reduced Instruction Set Computing (RISC) and Complex Instruction Set Computing (CISC). These approaches differ in instruction complexity, cycle time, and how computations are carried out.

指令集设计遵循两种基本理念：精简指令集计算（RISC）和复杂指令集计算（CISC）。这两种方法在指令复杂度、周期时间和执行计算的方式上各不相同。

Feature 特征	RISC 精简指令集	CISC 复杂指令集
Instruction format 指令格式	Small, simple, fixed-length 简单固定长度	Large, complex, variable-length 复杂可变长度
Cycles per instruction 每指令周期数	Typically 1 通常为1	Many (multiple clock cycles) 多个时钟周期
Control unit design 控制单元设计	Hardwired 硬布线控制	Micro-programmed 微程序控制
Registers 寄存器数目	Many 较多	Fewer 较少
Examples 实例	ARM, MIPS	x86 (Intel, AMD)

RISC processors achieve one instruction per clock cycle through pipelining and load/store architecture, where memory is accessed only through dedicated load and store instructions. CISC processors instead use more complex instructions to reduce the number of instructions needed per program.

RISC处理器通过流水线和加载/存储架构实现每时钟周期一条指令，内存仅通过专用的加载和存储指令访问。CISC处理器则通过更复杂的指令来减少每个程序所需的指令数量。

9. Pipelining and Performance Factors | 流水线与性能因素

CPU performance is determined by multiple factors: clock speed (measured in hertz), the number of cycles per instruction, the instruction set complexity, the amount of cache memory, and the width of the data bus. Pipelining is an efficiency technique that allows the CPU to begin fetching the next instruction while the current instruction is still being executed, analogous to an assembly line.

CPU性能由多个因素决定：时钟速度（以赫兹为单位）、每条指令的周期数、指令集复杂度、高速缓存容量和数据总线宽度。流水线是一种提高效率的技术，允许CPU在当前指令仍在执行时就提前取下一条指令，类似于流水线装配线。

In a five-stage pipeline, the stages are: instruction fetch, instruction decode, operand fetch, execution, and write-back. When the pipeline is full, one instruction completes every clock cycle, improving overall throughput significantly.

在五级流水线中，阶段包括：取指、译码、取操作数、执行和写回。当流水线填满时，每个时钟周期即有一条指令完成，从而显著提高整体吞吐量。

CPU Performance ∝ Clock Speed × Instructions per Cycle × Core Count

CPU 性能 ∝ 时钟速度 × 每周期指令数 × 核心数

Hazards — such as data dependencies between instructions, or branch instructions that change the path of execution — can cause pipeline stalls. Modern processors use techniques such as branch prediction and forwarding to mitigate these effects. For examination purposes, understanding the concept that pipelining increases throughput rather than decreasing the latency of a single instruction is crucial.

冒险（Hazards）——例如指令之间的数据依赖，或改变执行路径的分支指令——可能导致流水线停顿。现代处理器采用分支预测和转发等技巧来减轻这些影响。就考试而言，理解流水线提高的是吞吐量而非降低单条指令延迟这一点至关重要。

10. Interrupts and Input/Output | 中断与输入/输出

Interrupts are signals sent to the CPU by hardware devices or software to request attention. When an interrupt occurs, the CPU suspends its current work, saves the state of the Program Counter and other registers onto the stack, transfers control to an Interrupt Service Routine (ISR), and after its completion restores the saved state to resume processing.

中断是硬件设备或软件向CPU发出的请求注意的信号。当中断发生时，CPU暂停当前工作，将程序计数器和其它寄存器的状态保存到堆栈中，将控制权转移到中断服务程序（ISR），完成后恢复保存的状态以继续原来的处理过程。

There are three principal I/O techniques:

I/O主要有三种技术：

Programmed I/O 程序控制I/O: The CPU polls devices continuously, wasting valuable processing cycles. 轮询设备，浪费宝贵的处理周期。
Interrupt-driven I/O 中断驱动I/O: The CPU resumes other tasks until a device issues an interrupt to signal readiness. 设备准备好时发出中断通知CPU，CPU期间可执行其它任务。
Direct Memory Access (DMA) 直接存储器访问: A dedicated controller transfers blocks of data between memory and I/O devices without CPU intervention, freeing the CPU for other work. 专用DMA控制器无需CPU干预即可在内存与I/O设备之间传输数据块，将CPU解放出来处理其它工作。

In exam responses, always connect the I/O technique to its effect on the CPU — for example, DMA improves overall system efficiency precisely because it removes the CPU from ordinary bulk data transfers, such as disk-to-memory copying.

在答题时，务必把I/O方式与其对CPU的影响联系起来——例如，DMA之所以提升系统整体效率，正是因为在大批量数据（如磁盘到内存复制）传输中不再需要CPU介入。

11. Examining Past-Paper Scenarios | 历年真题典型场景

A common examination question asks candidates to compare the time to access a byte from different levels of the memory hierarchy, or to explain why increasing clock speed alone is insufficient for improving CPU performance.

常见考题包括要求考生比较从存储层次不同层级访问一个字节所需的时间，或解释为何仅提升时钟速度不足以提高CPU性能。

Another recurring question type gives a set of machine code instructions in hexadecimal or binary and asks candidates to trace the contents of the PC, CIR, MAR, and MDR through each stage of the fetch-decode-execute cycle. Practising these trace questions systematically is highly recommended.

另一类常考题型是给出一组以十六进制或二进制表示的机器码指令，要求考生跟踪PC、CIR、MAR和MDR在取指-译码-执行周期各阶段的内容。建议系统性地练习这类追踪题。

When comparing Von Neumann and Harvard architectures, always anchor your answer in examinable criteria: memory organisation, number of busses, and whether simultaneous instruction fetch and data access is possible. When answering on registers, be precise about what each register stores — PC stores the address of the next instruction, not the instruction itself.

比较冯·诺依曼与哈佛架构时，始终依据可考量的标准作答：存储组织结构、总线数量，以及能否同时取指令和访问数据。回答寄存器问题时须精确——PC保存的是下一条指令的地址，而不是指令本身。

12. Summary Checklist | 考点总结清单

Before entering the examination, confirm that you can confidently explain the following core points from this chapter:

进入考场前，请确认你已经能够自信地阐述本章以下核心要点：

The Von Neumann stored-program concept and its shared-memory limitation — 冯·诺依曼存储程序概念及其共享内存局限；
The structural and operational differences between Von Neumann and Harvard architectures — 冯·诺依曼与哈佛架构之间的结构与运行差异；
The role of the ALU, Control Unit, and the full set of core registers in the CPU — ALU、控制单元以及CPU全部核心寄存器的功能作用；
Each phase of the fetch-decode-execute cycle with correct register usage — 取指-译码-执行周期各阶段及正确的寄存器使用；
The memory hierarchy, plus how cache and virtual memory improve apparent speed — 存储层次结构，以及缓存和虚拟内存如何改善实际速度；
All five addressing modes with examples — 全部五种寻址方式并举例说明；
Address bus width calculation and system bus functions — 地址总线宽度计算和系统总线功能；
RISC versus CISC comparison points — RISC与CISC的比较要点；
Pipelining, hazards, and their impact on CPU throughput — 流水线、冒险及其对CPU吞吐量的影响；
Programmed I/O, interrupt-driven I/O, and DMA — 程序控制I/O、中断驱动I/O与DMA的区别及应用。

Mastery of these topics will not only secure marks in direct recall questions but also provides the framework for logical, structured answers in extended-response questions on computer architecture.

熟练掌握以上主题不仅能在直接记忆类题目中得分，还能为体系结构扩展回答题提供逻辑清晰、结构完整的答题框架。

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Computer Architecture and Organization | 计算机体系结构与组成原理