A-Level CIE Computer Science: Computer Architecture Key Points | A-Level CIE 计算机：计算机体系结构考点精讲

📚 A-Level CIE Computer Science: Computer Architecture Key Points | A-Level CIE 计算机：计算机体系结构考点精讲

Computer architecture forms the foundation of all digital systems. Understanding how the CPU works, how data flows between components, and how instructions are executed is essential for any A-Level computer scientist. This guide unpacks the CIE syllabus requirements, breaking down each concept into clear, exam-ready explanations.

计算机体系结构是所有数字系统的基础。理解 CPU 如何工作、数据如何在组件之间流动以及指令如何执行，对每一位 A-Level 计算机科学学生都至关重要。本指南根据 CIE 大纲要求，逐一拆解每个概念，提供清晰且适合考试的解释。

1. Introduction to Computer Architecture | 计算机体系结构导论

Computer architecture refers to the design of the internal components of a computer system, in particular the central processing unit (CPU), memory, and the buses that connect them. The most widely adopted model is the Von Neumann architecture, which stores both instructions and data in the same memory unit.

计算机体系结构指的是计算机系统内部组件的设计，尤其是中央处理器（CPU）、存储器以及连接它们的总线。最广泛采用的模型是冯·诺依曼架构，它将指令和数据存储在同一内存单元中。

Key concepts include the stored program concept, the fetch-decode-execute cycle, and how the processor interacts with main memory. At A-Level, you must be able to describe the roles of each register, control unit, and ALU, and explain how the system bus coordinates data transfer.

关键概念包括存储程序概念、取指—解码—执行周期，以及处理器如何与主存交互。在 A-Level 考试中，你必须能描述各个寄存器、控制单元和 ALU 的作用，并解释系统总线如何协调数据传输。

2. The Von Neumann Model | 冯·诺依曼模型

The Von Neumann architecture is built on the stored program concept: both program instructions and data are held in the same read-write memory. This design allows programs to be modified just like data, enabling flexible, general-purpose computing.

冯·诺依曼架构建立在存储程序概念之上：程序指令和数据都存放在同一个可读写存储器中。这种设计使得程序可以像数据一样被修改，从而实现了灵活的通用计算。

In this model, the CPU contains a control unit (CU), an arithmetic logic unit (ALU), and a set of registers. A single system bus carries addresses, data, and control signals between the processor and memory. The bottleneck of this architecture is often the shared bus, which can limit performance — known as the ‘Von Neumann bottleneck’.

在该模型中，CPU 包含控制单元（CU）、算术逻辑单元（ALU）和一组寄存器。单一的系统总线在处理器和内存之间传输地址、数据和控制信号。该架构的瓶颈常常是共享总线，这会限制性能——被称为“冯·诺依曼瓶颈”。

Stored program concept – instructions fetched from memory
存储程序概念 – 指令从内存中取出
Single shared memory – for both data and instructions
单一共享内存 – 同时存放数据和指令

3. CPU Components and Their Functions | CPU 组件及其功能

The CPU is the brain of the computer. It consists of three main functional units: the control unit (CU), the arithmetic logic unit (ALU), and registers. The CU directs the operation of the processor by sending timing and control signals. It decodes instructions and manages data flow between the ALU, registers, and memory.

CPU 是计算机的大脑。它由三个主要功能单元组成：控制单元（CU）、算术逻辑单元（ALU）和寄存器。CU 通过发送时序和控制信号来指导处理器的操作。它解码指令并管理 ALU、寄存器和内存之间的数据流。

The ALU performs arithmetic (addition, subtraction) and logical (AND, OR, NOT) operations. It receives operands from registers, carries out the operation, and stores the result in a register. Registers are small, extremely fast storage locations within the CPU, each serving a specific role during the instruction cycle.

ALU 执行算术运算（加法、减法）和逻辑运算（AND、OR、NOT）。它从寄存器接收操作数，执行运算，并将结果存入寄存器。寄存器是 CPU 内部极小但极快的存储位置，每个寄存器在指令周期中都有特定作用。

Component	Function
CU	Controls and coordinates CPU activities
ALU	Performs calculations and logic
Registers	Hold temporary data during execution

组件 | 功能 (CU 控制协调, ALU 算术逻辑, 寄存器暂存)

4. Registers: The CPU’s Working Memory | 寄存器：CPU 的工作存储器

Registers are temporary storage locations inside the CPU used to hold data, addresses, and instructions currently being processed. They operate at the processor’s clock speed, making them the fastest form of memory in the computer. CIE expects students to know the role of each key register.

寄存器是 CPU 内部的临时存储位置，用于存放当前正在处理的数据、地址和指令。它们以处理器的时钟速度运行，是计算机中最快的存储器。CIE 要求考生了解每个关键寄存器的作用。

Program Counter (PC) – holds the address of the next instruction to be fetched.
程序计数器 (PC) – 保存下一条要取出的指令的地址。
Memory Address Register (MAR) – holds the address of the memory location to be accessed.
内存地址寄存器 (MAR) – 保存将要访问的内存位置的地址。
Memory Data Register (MDR) – holds the data that has been fetched from or will be written to memory.
内存数据寄存器 (MDR) – 保存从内存取出或要写入内存的数据。
Current Instruction Register (CIR) – holds the instruction currently being decoded and executed.
当前指令寄存器 (CIR) – 保存正在被解码和执行的指令。
Accumulator (ACC) – stores intermediate arithmetic and logic results.
累加器 (ACC) – 存储算术和逻辑运算的中间结果。
Index Register (IX) – used for indexed addressing; holds a base value that can be added to an operand.
变址寄存器 (IX) – 用于变址寻址；保存一个可与操作数相加的基值。

5. The System Bus: Address, Data, and Control | 系统总线：地址、数据和控制

The system bus is a set of parallel wires that connects the CPU to memory and I/O devices. It is divided into three distinct buses, each carrying a different type of signal. The width of these buses directly affects system performance.

系统总线是一组并行线路，将 CPU 连接到内存和 I/O 设备。它分为三组不同的总线，每组传输不同类型的信号。这些总线的宽度直接影响系统性能。

The address bus is unidirectional (from CPU to memory), carrying the location of the data or instruction. Its width determines the maximum addressable memory — a 32-line address bus can address 2³² memory locations. The data bus is bidirectional, carrying the actual data between CPU and memory. Its width dictates how many bits can be transferred at once; a 64-bit data bus moves 8 bytes per clock cycle.

地址总线是单向的（从 CPU 到内存），携带数据或指令的位置信息。它的宽度决定了最大可寻址内存——32 位地址总线可寻址 2³² 个内存位置。数据总线是双向的，在 CPU 和内存之间传输实际数据。其宽度决定了一次能传输多少位；64 位数据总线每个时钟周期可移动 8 字节。

The control bus carries commands and timing signals, such as read/write lines, interrupt requests, and clock signals. It coordinates the activities of all connected components.

控制总线传输命令和时序信号，如读/写线、中断请求和时钟信号。它协调所有连接组件的活动。

6. The Fetch-Decode-Execute Cycle | 取指-解码-执行周期

This cycle is the fundamental operational process of the CPU. Every instruction passes through these three stages before the next one begins. The speed at which this cycle runs is governed by the system clock.

这个周期是 CPU 的基本操作过程。每条指令在开始下一条之前都要经历这三个阶段。该周期的运行速度由系统时钟控制。

Fetch: The address in the PC is copied to the MAR. A read signal is sent via the control bus. The instruction from memory is placed on the data bus and stored in the MDR. It is then copied to the CIR. The PC is incremented to point to the next instruction.

取指：PC 中的地址被复制到 MAR。通过控制总线发送读信号。内存中的指令被放到数据总线上并存入 MDR。然后将它复制到 CIR。PC 递增以指向下一条指令。

Decode: The control unit interprets the bit pattern in the CIR. It splits the instruction into opcode and operand(s), and sets up the necessary circuitry within the ALU and registers to carry out the operation.

解码：控制单元解释 CIR 中的位模式。它将指令拆分为操作码和操作数，并设置 ALU 和寄存器中必要的电路来执行该操作。

Execute: The ALU performs the required operation, which may involve arithmetic, logic, data movement, or a jump. If a memory access is needed, the address is placed in the MAR, and data flows through the MDR. The result is stored in a register or memory.

执行：ALU 执行所需的操作，这可能包括算术、逻辑、数据移动或跳转。如果需要进行内存访问，地址被放入 MAR，数据通过 MDR 流动。结果存入寄存器或内存。

7. Pipelining: Improving Efficiency | 流水线：提高效率

Pipelining is a technique used in modern CPUs to improve instruction throughput. Instead of waiting for one instruction to complete all three stages before starting the next, the processor overlaps the stages. While one instruction is being executed, the next can be decoded, and a third can be fetched simultaneously.

流水线是现代 CPU 用来提高指令吞吐量的一种技术。处理器不再等待一条指令完成所有三个阶段才开始下一条，而是让各阶段重叠。当一条指令正在执行时，下一条可以解码，同时再下一条可以被取出。

A typical three-stage pipeline consists of fetch, decode, and execute stages running in parallel. This can triple the number of instructions processed per unit time under ideal conditions. However, hazards can occur: data hazards (when an instruction depends on the result of a previous one), control hazards (branch instructions causing wrong predictions), and structural hazards (resource conflicts).

一个典型的三级流水线由并行运行的取指、解码和执行阶段组成。在理想条件下，这可以使单位时间内处理的指令数增加到三倍。然而，可能会出现冒险（hazards）：数据冒险（一条指令依赖于前一条指令的结果）、控制冒险（分支指令导致预测错误）和结构冒险（资源冲突）。

Exam questions often ask you to describe how pipelining works and to explain one type of hazard with a simple example. Be precise about the stages and the potential for stalls.

考试经常要求你描述流水线的工作原理，并用一个简单的例子解释一种冒险类型。要准确描述各个阶段以及停顿的可能性。

8. RISC vs. CISC Architectures | RISC 与 CISC 架构

Two fundamental design philosophies underpin CPU instruction sets: Reduced Instruction Set Computer (RISC) and Complex Instruction Set Computer (CISC). CIE expects you to compare them in terms of instruction complexity, number of registers, use of pipeline, and compiler requirements.

两种基本的设计理念支撑着 CPU 指令集：精简指令集计算机（RISC）和复杂指令集计算机（CISC）。CIE 要求考生从指令复杂度、寄存器数量、流水线使用和编译器需求等方面进行比较。

RISC processors use a small, highly optimized set of simple instructions. Each instruction typically executes in one clock cycle, making pipelining straightforward. They use many general-purpose registers and require more RAM because program code can be larger. The compiler plays a heavier role in generating efficient code. Examples: ARM, MIPS.

RISC 处理器使用一小组高度优化的简单指令。每条指令通常在一个时钟周期内执行，使流水线易于实现。它们使用许多通用寄存器，并且由于程序代码可能更大，需要更多 RAM。编译器在生成高效代码方面承担更重要的角色。示例：ARM、MIPS。

CISC processors have a large set of complex instructions, some of which can perform multi-step operations in a single instruction. This reduces the number of instructions per program but requires more complex circuitry, making pipelining harder. CISC uses fewer registers and relies on microcode to break complex instructions into simpler steps. Example: x86 (Intel, AMD).

CISC 处理器有一大套复杂指令，其中一些可以在单条指令中执行多步操作。这减少了每个程序的指令数量，但需要更复杂的电路，使流水线更难实现。CISC 使用较少的寄存器，并依赖微码将复杂指令分解为更简单的步骤。示例：x86（Intel、AMD）。

Feature	RISC	CISC
Instruction set size	Small, simple	Large, complex
Instruction execution time	Usually 1 clock cycle	Often multi-cycle
Pipelining	Easy to implement	Harder due to variable timing
Registers	Many general-purpose	Fewer, some dedicated
Compiler complexity	More complex	Less complex

特性 | RISC / CISC 对比 (指令集大小, 执行时间, 流水线, 寄存器, 编译器复杂度)

9. Addressing Modes | 寻址模式

Addressing modes specify how the CPU interprets the operand part of an instruction. They allow more flexible access to data. The CIE syllabus focuses on immediate, direct, indirect, indexed, and relative addressing.

寻址模式指定 CPU 如何解释指令的操作数部分。它们可以更灵活地访问数据。CIE 大纲重点关注立即、直接、间接、变址和相对寻址。

Immediate addressing – the operand is the actual data, e.g., LOAD #5 loads the value 5.
立即寻址 – 操作数就是实际数据，如 LOAD #5 加载数值 5。
Direct addressing – the operand holds the memory address of the data.
直接寻址 – 操作数存放数据的存储地址。
Indirect addressing – the operand gives an address which points to the actual data address. Useful for implementing pointers.
间接寻址 – 操作数给出一个地址，该地址指向实际数据的地址。适用于实现指针。
Indexed addressing – the effective address is formed by adding a constant (from the instruction) to the contents of the index register (IX). Great for arrays.
变址寻址 – 有效地址由指令中的常数加上变址寄存器（IX）的内容形成。非常适合数组。
Relative addressing – used in branch instructions; the offset is added to the program counter to form the target address. Makes code relocatable.
相对寻址 – 用于分支指令；偏移量与程序计数器相加形成目标地址。使代码可重定位。

10. Memory Hierarchy – Cache, RAM, and Storage | 存储体系：缓存、内存和存储

Computer systems use a memory hierarchy to balance speed, capacity, and cost. The closer to the CPU, the faster and more expensive per byte the memory becomes. Registers (fastest) sit at the top, followed by cache, main memory (RAM), and secondary storage (hard disk/SSD) at the bottom.

计算机系统使用存储层次结构来平衡速度、容量和成本。离 CPU 越近，每字节的速度越快，成本也越高。寄存器（最快）位于顶层，其次是高速缓存（cache）、主存储器（RAM），底层是二级存储器（硬盘/固态硬盘）。

Cache memory is a small amount of extremely fast SRAM located on or very near the CPU. It stores frequently accessed instructions and data to reduce the average time to access memory. Modern processors have multiple levels: L1 (smallest, fastest), L2, and L3 (larger, shared). When the CPU finds needed data in cache, it’s called a cache hit; otherwise, a cache miss requires fetching from slower RAM.

高速缓存是位于 CPU 内部或非常靠近 CPU 的小容量、极快速 SRAM。它存储频繁访问的指令和数据，以减少平均内存访问时间。现代处理器有多级缓存：L1（最小、最快）、L2 和 L3（更大、共享）。当 CPU 在缓存中找到所需数据时，称为缓存命中；否则，缓存未命中就需要从较慢的 RAM 中获取。

The principle of locality explains why caches work: temporal locality (recently accessed data is likely to be used again) and spatial locality (data near recently accessed data is likely to be needed soon).

局部性原理解释了为什么缓存有效：时间局部性（最近访问过的数据很可能再次被使用）和空间局部性（最近访问过的数据附近的数据很可能很快被需要）。

11. Interrupts and Input/Output | 中断和输入输出

Interrupts are signals from hardware or software that prompt the CPU to suspend its current task and execute a special routine called an Interrupt Service Routine (ISR). After the ISR completes, the CPU resumes its original task. This mechanism allows efficient handling of I/O devices without constant polling.

中断是来自硬件或软件的信号，它促使 CPU 暂停当前任务，转而执行一个称为中断服务程序（ISR）的特殊例程。ISR 完成后，CPU 恢复原任务。这种机制无需持续轮询，就能高效处理 I/O 设备。

When an interrupt occurs, the CPU completes the current fetch-decode-execute cycle, saves the state (contents of PC and registers) onto the system stack, identifies the interrupt source (via vector or priority), and loads the address of the corresponding ISR into the PC. After servicing, the saved state is restored, and execution continues from where it left off.

当中断发生时，CPU 完成当前的取指-解码-执行周期，将状态（PC 和寄存器的内容）保存到系统栈上，识别中断源（通过向量或优先级），并将相应 ISR 的地址加载到 PC 中。在服务结束后，恢复保存的状态，并从断点处继续执行。

Direct Memory Access (DMA) is a method for transferring data between fast I/O devices and memory without continuous CPU intervention. A DMA controller takes over the system bus to move blocks of data, freeing the CPU for other tasks.

直接存储器访问 (DMA) 是一种在快速 I/O 设备与内存之间传输数据的方法，无需 CPU 的持续干预。DMA 控制器接管系统总线以移动数据块，从而将 CPU 解放出来执行其他任务。

12. Exam Tips & Summary | 考试技巧与总结

In CIE A-Level Computer Science, architecture questions often combine definitions with comparative analysis. Remember to use precise terminology: ‘opcode’, ‘operand’, ‘address bus’, ‘control bus’. Diagrams of the fetch-decode-execute cycle showing register transfers can boost your marks. Be ready to compare RISC vs. CISC with concrete examples and to explain how a cache improves performance using the principle of locality.

在 CIE A-Level 计算机科学中，体系结构题常常将定义与对比分析结合起来。记住要使用精确的术语：“操作码opcode”、“操作数operand”、“地址总线address bus”、“控制总线control bus”。画出显示寄存器传输的取指-解码-执行周期图可以获得加分。准备好用具体例子比较 RISC 与 CISC，并运用局部性原理解释缓存如何提高性能。

Key topics to master:

需要掌握的关键主题：

Functions of PC, MAR, MDR, CIR, ACC, IX
PC、MAR、MDR、CIR、ACC、IX 的功能
The fetch-decode-execute cycle step by step
逐步理解取指-解码-执行周期
System bus width and addressable memory calculation
系统总线宽度与可寻址内存计算
Pipelining stages and hazard types
流水线阶段和冒险类型
Addressing modes with examples
寻址模式及示例
Interrupt handling and DMA
中断处理和 DMA

Master these concepts, and you will be well-prepared for the architecture section of your CIE exams. Good luck!

掌握这些概念，你将为 CIE 考试的体系结构部分做好充分准备。祝你好运！

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A-Level CIE Computer Science: Computer Architecture Key Points | A-Level CIE 计算机：计算机体系结构 考点精讲