Boolean Algebra | 布尔代数考点精讲

📚 Boolean Algebra | 布尔代数考点精讲

Boolean algebra is the backbone of digital logic and computer circuit design. Mastering its laws, simplification techniques, and mapping methods is essential for success in IB and CIE Computer Science. This article covers all core concepts step by step, from basic operators to Karnaugh maps, with clear bilingual explanations.

布尔代数是数字逻辑和计算机电路设计的基石。掌握其定律、化简方法和映射技巧，对于 IB 和 CIE 计算机科学考试至关重要。本文从基本运算符到卡诺图，一步步用清晰的双语解释覆盖所有核心概念。

1. Introduction and Basic Operators | 简介与基本运算符

Boolean algebra operates on binary variables that can only take the values 0 and 1. The three fundamental operations are AND, OR, and NOT. In Boolean expressions, AND is represented by a dot (·) or multiplication (e.g., A·B), OR by a plus sign (e.g., A+B), and NOT by an overbar or prime (e.g., A’ or ¬A).

布尔代数处理只能取值 0 和 1 的二进制变量。三种基本运算是与（AND）、或（OR）、非（NOT）。在布尔表达式中，与用点号或乘号表示（如 A·B），或用加号表示（如 A+B），非用上划线或撇号表示（如 A’ 或 ¬A）。

The AND gate outputs 1 only if all inputs are 1. The OR gate outputs 1 if at least one input is 1. The NOT gate, also called an inverter, outputs the complement of its input.

与门仅在所有输入均为 1 时才输出 1。或门只要至少一个输入为 1 就输出 1。非门又称反相器，输出输入的补码。

A	B	A AND B (A·B)	A OR B (A+B)	NOT A (A’)
0	0	0	0	1
0	1	0	1	1
1	0	0	1	0
1	1	1	1	0

Other derived operators include NAND (NOT AND), NOR (NOT OR), XOR (exclusive OR), and XNOR (exclusive NOR). NAND outputs 1 only when at least one input is 0. XOR outputs 1 when inputs differ.

其他派生运算符包括与非（NAND）、或非（NOR）、异或（XOR）和同或（XNOR）。与非仅在至少一个输入为 0 时输出 1。异或在输入不同时输出 1。

2. Boolean Laws and Theorems | 布尔定律与定理

The foundational Boolean laws allow us to manipulate and simplify logical expressions. These include identity, null, idempotent, complement, commutative, associative, distributive, absorption, and De Morgan’s laws. Understanding each law is crucial for algebraic simplification.

基本的布尔定律使我们能够操作和化简逻辑表达式。包括同一律、零律、幂等律、互补律、交换律、结合律、分配律、吸收律和德摩根定律。理解每条定律对代数化简至关重要。

• Identity Law | 同一律: A + 0 = A, A · 1 = A
• Null Law | 零律: A + 1 = 1, A · 0 = 0
• Idempotent Law | 幂等律: A + A = A, A · A = A
• Complement Law | 互补律: A + A’ = 1, A · A’ = 0
• Double Negation | 双重否定: (A’)’ = A
• Commutative Law | 交换律: A + B = B + A, A · B = B · A
• Associative Law | 结合律: (A + B) + C = A + (B + C), (A · B) · C = A · (B · C)
• Distributive Law | 分配律: A · (B + C) = A·B + A·C, A + (B·C) = (A+B) · (A+C)
• Absorption Law | 吸收律: A + A·B = A, A · (A + B) = A

These laws are applied repeatedly in simplification problems. For example, using absorption: A + A·B = A(1 + B) = A·1 = A. Similarly, A·(A + B) = A·A + A·B = A + A·B = A.

这些定律在化简题中被反复应用。例如，使用吸收律：A + A·B = A(1 + B) = A·1 = A。类似地，A·(A + B) = A·A + A·B = A + A·B = A。

3. Truth Tables | 真值表

A truth table lists all possible combinations of input values and the corresponding output of a Boolean function. For n input variables, there are 2ⁿ rows. Truth tables are essential for verifying equivalence between expressions and for deriving standard forms.

真值表列出了输入值的所有可能组合以及布尔函数对应的输出。对于 n 个输入变量，共有 2ⁿ 行。真值表对于验证表达式是否等价以及推导标准形式至关重要。

To construct a truth table for F = A·B + A’·C, first list all combinations of A, B, C (8 rows). Compute A·B and A’·C separately, then apply OR to get the final output. A systematic approach ensures no row is missed.

要构造 F = A·B + A’·C 的真值表，首先列出 A、B、C 的所有组合（8 行）。分别计算 A·B 和 A’·C，然后进行或运算得到最终输出。系统的方法可确保不遗漏任何行。

A	B	C	A·B	A’·C	F
0	0	0	0	0	0
0	0	1	0	1	1
0	1	0	0	0	0
0	1	1	0	1	1
1	0	0	0	0	0
1	0	1	0	0	0
1	1	0	1	0	1
1	1	1	1	0	1

Truth tables are also the basis for writing Sum-of-Products (SOP) and Product-of-Sums (POS) forms, which we will explore later.

真值表也是书写积之和（SOP）与和之积（POS）形式的基础，后续会详细探讨。

4. Logic Gates | 逻辑门

Boolean algebra is implemented physically using logic gates. Each gate corresponds to a Boolean function. Basic gates include AND, OR, NOT, NAND, NOR, XOR, and XNOR. Their symbols and truth tables must be memorized for both IB and CIE exams.

布尔代数通过逻辑门在物理上实现。每个门对应一个布尔函数。基本门包括与门、或门、非门、与非门、或非门、异或门和同或门。其符号和真值表必须熟记，以备 IB 和 CIE 考试。

NAND and NOR gates are called universal gates because any Boolean function can be implemented using only NAND gates or only NOR gates. This property is often tested in circuit simplification questions.

与非门和或非门被称为通用门，因为任何布尔函数都可以仅用与非门或仅用或非门来实现。这一特性经常在电路化简题中考查。

When drawing circuit diagrams, use standard ANSI/IEEE symbols: AND is D-shaped, OR is shield-shaped with curved back, NOT is a triangle with a bubble, NAND is AND with bubble, NOR is OR with bubble. For international exams, both ANSI and IEC rectangular symbols may be accepted, but consistency matters.

绘制电路图时，使用标准 ANSI/IEEE 符号：与门为 D 形，或门为弧形背面的盾形，非门为带气泡的三角形，与非门为带气泡的与门，或非门为带气泡的或门。在国际考试中，ANSI 和 IEC 矩形符号可能均可接受，但需保持一致。

5. De Morgan’s Theorems | 德摩根定理

De Morgan’s theorems provide a way to convert between AND and OR operations and are extremely useful in simplification. The two rules state:

德摩根定理提供了与运算和或运算之间转换的方法，在化简中极其有用。这两条规则如下：

(A + B)’ = A’ · B’

(A · B)’ = A’ + B’

In words: the complement of a sum equals the product of complements; the complement of a product equals the sum of complements. These can be generalized to any number of variables: (A + B + C)’ = A’·B’·C’, and (A·B·C)’ = A’+B’+C’.

换句话说：和的补等于补的积；积的补等于补的和。这些定理可以推广到任意多个变量：(A+B+C)’ = A’·B’·C’，且 (A·B·C)’ = A’+B’+C’。

De Morgan’s laws are often used to push negations inward when simplifying complex expressions or converting all gates to NAND/NOR. For example, F = (A·B)’ + C can be rewritten as A’ + B’ + C, eliminating the internal AND-NOT gate.

德摩根定律常用于在化简复杂表达式或将所有门转换为与非/或非门时，将否定向内推。例如，F = (A·B)’ + C 可改写为 A’ + B’ + C，从而省去内部的与非门。

A common exam question is to prove equivalence using truth tables or algebraic manipulation. For instance, show that (A’·B’)’ = A + B. Using De Morgan: (A’·B’)’ = (A’)’ + (B’)’ = A + B. Always verify each step.

常见考题要求使用真值表或代数变换证明等价性。例如，证明 (A’·B’)’ = A + B。使用德摩根定律：(A’·B’)’ = (A’)’ + (B’)’ = A + B。务必验证每一步。

6. Simplification Using Boolean Algebra | 使用布尔代数化简

Expressions can be simplified by applying the laws in a logical sequence. The goal is to reduce the number of gates and inputs in a digital circuit. There is no single fixed method, but the following steps are typically helpful:

可以通过按逻辑顺序应用定律来化简表达式。目的是减少数字电路中门和输入的数量。虽然没有固定方法，但以下步骤通常很有帮助：

• Use De Morgan’s laws to remove all overbars over groups.
• Use 德摩根定律去除所有组合上的上划线。
• Multiply out brackets if necessary to obtain a sum-of-products form.
• 若需要，将括号乘开以得到积之和形式。
• Look for common factors and use A + A’ = 1 to eliminate terms.
• 寻找公因子并利用 A + A’ = 1 消去项。
• Apply absorption and idempotent laws to simplify.
• 应用吸收律和幂等律进行化简。

Example: Simplify F = AB + AB’. Factor: F = A(B + B’) = A(1) = A. Another: F = A + A’B = (A + A’)(A + B) = 1·(A + B) = A + B (using the second distributive law). Alternatively, use consensus theorem (AB + A’C + BC = AB + A’C).

例题：化简 F = AB + AB’。提取公因式：F = A(B + B’) = A(1) = A。另一例：F = A + A’B = (A + A’)(A + B) = 1·(A + B) = A + B（使用第二分配律）。或者使用共识定理（AB + A’C + BC = AB + A’C）。

Algebraic simplification becomes tedious for more than 4 or 5 variables; that’s where Karnaugh maps come in.

对于超过 4 或 5 个变量的情况，代数化简会变得繁琐，此时就需要卡诺图。

7. Standard Forms: SOP and POS | 标准形式：积之和与和之积

A Boolean function can be expressed in Sum-of-Products (SOP) form, where several AND terms are ORed together (e.g., AB + A’C). Alternatively, it can be expressed in Product-of-Sums (POS) form, where several OR terms are ANDed together (e.g., (A+B)(A’+C)). These are called ‘standard forms’.

布尔函数可以表示为积之和（SOP）形式，即多个与项进行或运算（如 AB + A’C）。也可以表示为和之积（POS）形式，即多个或项进行与运算（如 (A+B)(A’+C)）。这两种称为“标准形式”。

The canonical SOP (also called minterm expansion) includes every variable in each product term either in true or complemented form for every combination where output is 1. The canonical POS (maxterm expansion) includes every variable in each sum term for combinations where output is 0.

规范积之和（也称为最小项展开）在每个积项中包含所有变量，要么原变量要么反变量，针对输出为 1 的每个组合。规范和之积（最大项展开）在输出为 0 的组合中，每个和项包含所有变量。

To convert a truth table to canonical SOP: for each row where F=1, write a minterm (AND of all variables, with 0 complemented). Then OR all minterms. For example, the truth table earlier gave F = A’B’C + A’BC + AB’C’? Actually we had F=1 for rows (0,0,1), (0,1,1), (1,1,0), (1,1,1). So canonical SOP: F = A’B’C + A’BC + ABC’ + ABC. That can be simplified to A’C + AB.

将真值表转换为规范积之和：对于每个 F=1 的行，写出一个最小项（所有变量的与，0 写成反变量）。然后将所有最小项进行或运算。例如，前面的真值表中 F=1 的行是 (0,0,1), (0,1,1), (1,1,0), (1,1,1)。因此规范积之和为：F = A’B’C + A’BC + ABC’ + ABC，可化简为 A’C + AB。

Canonical POS: for each row where F=0, write a maxterm (OR of all variables, with 1 complemented). Then AND all maxterms. Both forms are tested frequently in exams.

规范和之积：对于每个 F=0 的行，写出一个最大项（所有变量的或，1 写成反变量），然后将所有最大项进行与运算。两种形式在考试中都经常出现。

8. Karnaugh Maps (K-Maps) | 卡诺图

Karnaugh maps provide a visual method for simplifying Boolean expressions of up to four variables (sometimes five or six for advanced courses, but IB/CIE mostly focus on 2–4 variables). A K-map is a grid where each cell corresponds to a minterm, and adjacent cells differ by exactly one variable.

卡诺图提供了一种可视化方法，用于化简最多四个变量（高级课程可到五或六个，但 IB/CIE 主要关注 2–4 个变量）的布尔表达式。卡诺图是一个网格，每个单元格对应一个最小项，相邻单元格恰好只有一个变量不同。

For a 2-variable K-map (variables A,B), cells are arranged 2×2. For 3 variables (A,B,C), we use a 2×4 grid with Gray code ordering on the axes (00, 01, 11, 10). For 4 variables (A,B,C,D), a 4×4 grid is used. Labeling must follow Gray code to maintain adjacency.

对于 2 变量卡诺图（变量 A, B），单元格为 2×2 排列。对于 3 变量（A, B, C），使用 2×4 网格，轴按格雷码顺序标记（00, 01, 11, 10）。对于 4 变量（A, B, C, D），使用 4×4 网格。标记必须遵循格雷码以保持相邻性。

To use a K-map: fill in 1s for all minterms where the function outputs 1. Then group adjacent 1s into the largest possible power-of-two rectangles (1, 2, 4, 8…). Each group yields a product term where variables that change within the group are eliminated. Overlapping groups are allowed, and groups may wrap around the edges.

使用卡诺图的方法：在所有函数输出为 1 的最小项对应单元格中填入 1。然后将相邻的 1 分组成尽可能大的、大小为 2 的幂的矩形（1, 2, 4, 8…）。每个分组生成一个积项，其中在组内发生变化的变量被消去。分组可以重叠，且可以环绕边界。

For example, a 3-variable function given by minterms m1, m3, m6, m7 (i.e., A’B’C, A’BC, ABC’, ABC) will simplify to A’C + AB. The grouping of m1 and m3 eliminates B, giving A’C; grouping m6 and m7 eliminates C, giving AB.

例如，一个由最小项 m1, m3, m6, m7（即 A’B’C, A’BC, ABC’, ABC）给出的 3 变量函数将化简为 A’C + AB。m1 和 m3 分组消去 B，产生 A’C；m6 和 m7 分组消去 C，产生 AB。

When forming groups, ensure all 1s are covered with the fewest number of groups, but each group must be as large as possible. This yields a minimal SOP expression.

在分组时，需确保用最少的组数覆盖所有 1，但每组必须尽可能大。这样可以得到最小的积之和表达式。

9. Don’t Care Conditions | 无关项

In some logic designs, certain input combinations never occur or we don’t care about the output. These are called don’t care conditions, denoted by X in truth tables and K-maps. Don’t cares can be treated as either 0 or 1 to help form larger groups and further simplify the expression.

在某些逻辑设计中，某些输入组合永远不会出现，或者我们不关心其输出。这些称为无关项，在真值表和卡诺图中以 X 表示。无关项可视为 0 或 1，以帮助形成更大的分组，进一步化简表达式。

When using a K-map, include X cells in a group if they enable a larger grouping, but do not create a group consisting solely of X’s. This flexibility often leads to a simpler circuit. In SOP, we use X as 1 when beneficial; in POS, we use X as 0 when needed.

使用卡诺图时，若 X 单元格能让分组变得更大，则将其包含进组，但不能创建完全由 X 组成的分组。这种灵活性通常能得到更简单的电路。在积之和中，有利时将 X 当作 1；在和之积中，需要时将 X 当作 0。

Example: F = Σm(1,3,7) + d(5) for a 3-variable function (A,B,C). Minterms: 001, 011, 111 and don’t care 101. The K-map will have 1s in 001, 011, 111 and X in 101. Grouping 1s at 011, 111 and X at 101 gives a group of four (top row 01,11) representing A’C? Actually careful: standard Gray order for ABC: A down, BC across as 00,01,11,10. Cells: m1=001 (A’B’C), m3=011 (A’BC), m5=101 (AB’C) don’t care, m7=111 (ABC). If we use X as 1, we can group m1,m3,m5,m7 as a square covering BC columns 01 and 11, and both rows A=0,1? Actually m1 (A’B’C) and m5 (AB’C) differ in A, same B’C? Let me think: m1: A’B’C, m3: A’BC, m5: AB’C, m7: ABC. A square of four across both rows and columns 01,11? The columns are B’C, BC? That group would eliminate A and give variable? Wait, the K-map for 3 variables: rows A=0,1; columns BC: 00,01,11,10. m1 is A=0, BC=01 (B’C); m3 is A=0, BC=11 (BC); m5 is A=1, BC=01 (B’C); m7 is A=1, BC=11 (BC). So grouping all four gives a term where both A and B change? That eliminates A and B, leaving C. Thus F = C. Including X simplified drastically.

例如：对于三变量函数 F = Σm(1,3,7) + d(5)（变量 A, B, C）。最小项：001, 011, 111，无关项 101。卡诺图中，001, 011, 111 处为 1，101 处为 X。将 011, 111 处的 1 与 101 处的 X 分组可得包含四个单元格的大组，化简后 F = C。包含无关项大幅简化了表达式。

10. Universal Gates: NAND and NOR Implementation | 通用门：与非门和或非门实现

Any Boolean function can be implemented using only NAND gates or only NOR gates. This is practically important because real digital circuits often use only one type of gate for manufacturing simplicity. Converting to NAND/NOR logic is a standard exam topic.

任何布尔函数都可以仅用与非门或仅用或非门来实现。这一点在实践上很重要，因为实际数字电路通常只使用一种门以简化制造。转换为与非/或非逻辑是标准考点。

For NAND-only implementation: begin with a simplified SOP expression. The conversion uses double negation and De Morgan to transform all AND/OR gates into NANDs. For an AND-OR SOP circuit, replace every AND gate with a NAND followed by an inverter (bubble), and then replace the OR gate with a NAND with bubbles on inputs, effectively cancelling bubbles. The result is a two-level NAND-NAND circuit. Similarly, for NOR-only implementation, start with a simplified POS expression and convert OR-AND into NOR-NOR.

对于仅用与非门的实现：从化简后的积之和表达式开始。利用双重否定和德摩根定律，将所有与/或门转换为与非门。对于与-或积之和电路，将每个与门替换为带反相器（气泡）的与非门，然后将或门替换为输入带气泡的与非门，从而有效抵消气泡。最终得到一个两级与非-与非电路。类似地，仅用或非门实现时，从化简后的和之积表达式开始，将或-与转换为或非-或非电路。

Example: F = AB + CD. Draw AND-OR. For NAND conversion, insert bubbles at all AND outputs and OR inputs. Then merge cascaded NOTs. The two AND gates become NAND gates; the OR gate with bubbles becomes a NAND. The final circuit is three NAND gates: AB -> NAND1, CD -> NAND2, outputs fed to NAND3. For NOR, we would need POS form: F = (A+C)(A+D)(B+C)(B+D), then two-level NOR-NOR.

示例：F = AB + CD。画出与-或电路。转换为与非门时，在所有与门输出和或门输入处插入气泡。然后合并级联的非门。两个与门变成与非门；带气泡的或门变成与非门。最终电路用三个与非门实现：AB 接与非门1，CD 接与非门2，输出接与非门3。若用或非门，则需要和之积形式：F = (A+C)(A+D)(B+C)(B+D)，然后两级或非-或非实现。

11. Application: Circuit Design from Specifications | 应用：根据规格设计电路

A typical exam question describes a real-world logic problem (e.g., a voting machine, alarm system, or traffic light controller) and asks you to derive the Boolean expression and draw the circuit. The design steps are: (1) define input and output variables; (2) construct a truth table from the word description; (3) derive the simplified Boolean expression using K-map or Boolean algebra; (4) draw the logic circuit, possibly using universal gates.

典型考题会描述一个现实逻辑问题（如投票机、报警系统或交通灯控制器），要求推导布尔表达式并画出电路。设计步骤为：(1) 定义输入和输出变量；(2) 根据文字描述构建真值表；(3) 使用卡诺图或布尔代数推导化简后的布尔表达式；(4) 画出逻辑电路，可能要求使用通用门。

For example: ‘Design a circuit that outputs 1 when a majority of three inputs A, B, C are 1.’ Majority function: F = AB + AC + BC. This is a classic case. The K-map of minterms 011, 101, 110, 111 yields F = AB + BC + AC.

例如：“设计一个电路，当三个输入 A、B、C 中多数为 1 时输出 1。”多数函数：F = AB + AC + BC。这是一个经典案例。最小项 011, 101, 110, 111 的卡诺图化简得到 F = AB + BC + AC。

Always verify your final circuit works correctly by testing a few input combinations. Exam reports highlight that students often lose marks for careless errors in truth tables or grouping.

务必通过测试几个输入组合来验证最终电路是否正常工作。考试报告指出，学生常因

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