📚 IB Computer Science: CPU Focused Exam Revision | IB 计算机：CPU 考点精讲
The CPU is the core component executing programs, and a solid understanding of its architecture and operation is essential for the IB Computer Science examination. This article presents a systematic review of key CPU concepts, including the Von Neumann model, registers, the instruction cycle, buses, and factors affecting performance.
CPU 是执行程序的核心部件，对其架构和运作的扎实理解是 IB 计算机科学考试的关键。本文系统梳理了 CPU 的重要考点，涵盖冯·诺依曼模型、寄存器、指令周期、总线以及影响性能的因素。
1. CPU Basics and Core Components | CPU 基础与核心组件
The Central Processing Unit (CPU) interprets and executes program instructions. It consists of three main functional units: the Control Unit (CU), the Arithmetic Logic Unit (ALU), and a set of registers. The CU directs the operation of the processor by generating control signals to coordinate data movement and instruction execution. The ALU performs arithmetic (addition, subtraction) and logical (AND, OR, NOT) operations on data. Registers are high‑speed storage locations inside the CPU used to hold temporary data and control information during the instruction cycle.
中央处理器（CPU）解释并执行程序指令。它由三个主要功能单元组成：控制单元（CU）、算术逻辑单元（ALU）和一组寄存器。CU 通过生成控制信号来协调数据移动和指令执行，从而指挥处理器的运行。ALU 对数据执行算术（加、减）和逻辑（与、或、非）运算。寄存器是 CPU 内部的高速存储位置，用于在指令周期中暂存临时数据和控制信息。
All components are connected via internal buses that carry data, addresses, and control signals. A basic understanding of this tripartite structure helps in grasping how a CPU fetches, decodes, and executes instructions.
所有组件通过内部总线相连，这些总线传输数据、地址和控制信号。理解这一三元结构有助于掌握 CPU 如何取指、译码和执行指令。
2. The Von Neumann Architecture | 冯·诺依曼架构
The IB syllabus focuses on the Von Neumann architecture, which stores both program instructions and data in the same main memory. This stored‑program concept means that a program is just a sequence of binary codes in memory, and the CPU can treat instructions as data if needed. A key implication is the Von Neumann bottleneck: the single bus used to transfer both instructions and data can limit overall performance because the CPU often has to wait while one type of transfer completes before starting another.
IB 大纲聚焦于冯·诺依曼架构，该架构将程序指令和数据存储在同一个主存储器中。这种“存储程序”概念意味着程序不过是内存中的一串二进制编码，CPU 可在需要时将指令当作数据处理。一个关键影响是冯·诺依曼瓶颈：用于传输指令和数据的单一总线会限制整体性能，因为在完成一种传输之前，CPU 常常必须等待，然后才能开始另一种传输。
In contrast, Harvard architecture uses separate memories and buses for instructions and data, allowing simultaneous access. While not the main focus in IB, students should be able to compare the two at a basic level.
相比之下，哈佛架构为指令和数据使用独立的存储器和总线，可以同时访问。虽然在 IB 中不是主要焦点，但学生应能进行基本比较。
The Von Neumann model defines the basic execution cycle: fetch an instruction from memory, decode it, and then execute it. The next several sections dissect this cycle and the hardware that supports it.
冯·诺依曼模型定义了基本的执行周期：从内存取指令，译码，然后执行。接下来的几节将剖析这个周期及其支持硬件。
3. CPU Registers and Their Roles | CPU 寄存器及其作用
Registers are the fastest memory in the computer, built directly into the CPU. Dedicated registers play specific roles during the fetch‑decode‑execute cycle. The most commonly examined are:
寄存器是计算机中最快的内存，直接内置于 CPU 中。专用寄存器在取指‑译码‑执行周期中发挥特定作用。最常考查的包括：
PC (Program Counter): holds the memory address of the next instruction to be fetched. After a fetch, the PC is incremented to point to the next sequential instruction, unless a jump or branch modifies it.
PC（程序计数器）：存放下一条要取指指令的内存地址。取指后，PC 会递增以指向下一条顺序指令，除非跳转或分支指令修改了它。
MAR (Memory Address Register): stores the address of the memory location that the CPU needs to read from or write to. The address is placed on the address bus.
MAR（内存地址寄存器）：存储 CPU 需要读取或写入的内存地址。该地址被放到地址总线上。
MDR (Memory Data Register, also called MBR): holds the data that has just been read from memory or is about to be written to memory. It serves as a buffer between the CPU and main memory.
MDR（内存数据寄存器，也称 MBR）：保存刚由内存读出的数据或即将写入内存的数据。它充当 CPU 与主存之间的缓冲。
CIR (Current Instruction Register): contains the actual instruction that is being decoded and executed. The instruction is split into an opcode (operation code) and operand (address or data).
CIR（当前指令寄存器）：存放正在被译码和执行的指令。指令被分为操作码（opcode）和操作数（地址或数据）。
ACC (Accumulator): a general‑purpose register used by the ALU to store intermediate results of calculations. In many simple processors, arithmetic operations implicitly use the accumulator.
ACC（累加器）：一个通用寄存器，ALU 用于存放运算的中间结果。在许多简单的处理器中，算术运算隐含使用累加器。
Understanding the precise role of each register enables you to trace the instruction cycle step by step, a common exam task.
理解每个寄存器的确切作用，能使你逐步跟踪指令周期，这是考试中的常见任务。
4. The Machine Instruction Cycle: Fetch | 机器指令周期：取指
The fetch stage retrieves the next instruction from main memory. The steps are:
取指阶段从主存中取出下一条指令。步骤如下：
1. The address in the PC is copied to the MAR. The PC holds the address of the instruction we want.
1. PC 中的地址被复制到 MAR。PC 保存我们想要指令的地址。
2. The MAR places this address on the address bus, and the control unit issues a memory read signal via the control bus.
2. MAR 将该地址放到地址总线上，控制单元通过控制总线发出内存读信号。
3. The memory subsystem responds by locating the data at that address and placing it on the data bus, from where it is loaded into the MDR.
3. 内存子系统响应，在指定地址找到数据并将其放到数据总线上，然后该数据被加载到 MDR。
4. The content of the MDR (the instruction) is copied to the CIR to be decoded. Simultaneously, the PC is incremented by the length of the instruction (e.g., by 1 or by 4, depending on the word size) so that it points to the next instruction in sequence.
4. MDR 的内容（即指令）被复制到 CIR 以待译码。同时，PC 按指令长度递增（例如加 1 或加 4，取决于字长），从而指向顺序的下一条指令。
At the end of fetch, the CIR contains the instruction binary pattern, and the PC has been updated. The processor is ready to decode.
取指结束时，CIR 包含指令的二进制模式，PC 已更新。处理器准备好译码。
5. The Machine Instruction Cycle: Decode | 机器指令周期：译码
In the decode stage, the Control Unit examines the opcode field of the instruction in the CIR. The CU’s instruction decoder translates the binary opcode into a sequence of control signals that will orchestrate the execute stage. For example, an opcode for ‘ADD’ will activate the ALU to perform addition, while a ‘LOAD’ opcode will trigger a memory read operation.
在译码阶段，控制单元检查 CIR 中指令的操作码字段。CU 的指令译码器将二进制操作码转换为一系列控制信号，这些信号将指挥执行阶段。例如，“ADD” 操作码将激活 ALU 执行加法，而 “LOAD” 操作码将触发内存读操作。
If the instruction has an operand that refers to a memory address, the decode stage may also involve computing that address (e.g., using a base register plus offset) and loading it into the MAR. On simple processors, this may be part of the execute stage, but conceptually the interpretation and preparation occur now.
如果指令的操作数引用某个内存地址，译码阶段还可能包括计算该地址（例如，使用基址寄存器加偏移量）并将其加载到 MAR。在简单的处理器上，这可能是执行阶段的一部分，但从概念上讲，解释和准备工作现在发生。
The decode stage is critical for setting up data paths and control signals. Without it, the processor would not know which hardware resources are needed.
译码阶段对于设置数据通路和控制信号至关重要。没有它，处理器将不知道需要哪些硬件资源。
6. The Machine Instruction Cycle: Execute | 机器指令周期：执行
During execution, the processor carries out the operation specified by the instruction. A few representative examples illustrate the process.
在执行期间，处理器执行指令指定的操作。几个代表性的例子可以说明这一过程。
For an arithmetic instruction such as ADD R1, the contents of R1 are sent to one input of the ALU, the accumulator provides the other input, and the CU sets the ALU to perform addition. The result is stored back in the accumulator, and status flags (e.g., zero, overflow) in the status register are updated.
对于算术指令，如 ADD R1，R1 的内容被送到 ALU 的一个输入端，累加器提供另一个输入端，CU 设置 ALU 执行加法。结果存回累加器，并更新状态寄存器中的标志位（如零标志、溢出标志）。
For a LOAD instruction, the MAR holds the memory address computed during decode. The CU issues a read signal, the memory provides the data on the data bus, and this value is loaded into the ACC or another specified register.
对于 LOAD 指令，MAR 保存译码时计算出的内存地址。CU 发出读信号，存储器在数据总线上提供数据，该值被加载到 ACC 或另一个指定的寄存器。
For a STORE instruction, the contents of a CPU register are sent to the MDR, the address to write to is placed in the MAR, and the CU issues a memory write signal. Data travels from the MDR over the data bus to the memory.
对于 STORE 指令，CPU 寄存器的内容被送到 MDR，要写入的地址被放入 MAR，CU 发出内存写信号。数据从 MDR 经数据总线传输到内存。
For a branch (JMP) instruction, the execute stage simply overwrites the PC with the target address, thereby breaking the sequential flow. If the branch is conditional (e.g., JZ – jump if zero), the condition flags are examined first; if the condition is true, the PC is updated, otherwise the PC continues sequentially.
对于分支（JMP）指令，执行阶段只是用目标地址覆盖 PC，从而打破顺序执行。如果分支是有条件的（如 JZ – 为零则跳转），则先检查条件标志；若条件为真，则更新 PC，否则 PC 顺序继续。
The cycle then repeats with a new fetch from the updated PC. This continuous loop is the heartbeat of a Von Neumann machine.
然后周期重复，从更新后的 PC 重新取指。这个持续的循环是冯·诺依曼机器的心跳。
7. The Role of Buses in CPU Operation | 总线在 CPU 操作中的作用
Buses are shared communication pathways that connect the CPU, memory, and I/O devices. There are three main buses: the address bus, the data bus, and the control bus. The address bus carries memory addresses from the CPU (usually from the MAR) to memory; its width determines the maximum addressable memory (e.g., a 32‑bit address bus can address 2³² memory locations). The data bus transfers the actual data between the CPU and memory or I/O devices; its width often matches the word size of the processor and influences how much data can be moved per transfer. The control bus is a collection of lines that transmit commands and timing signals (read, write, interrupt, clock) from the CU to other components.
总线是连接 CPU、内存和 I/O 设备的共享通信路径。主要有三种总线：地址总线、数据总线和控制总线。地址总线将内存地址从 CPU（通常来自 MAR）传送到内存；其宽度决定了最大可寻址内存容量（例如，32 位地址总线可寻址 2³² 个内存单元）。数据总线在 CPU 与内存或 I/O 设备之间传输实际数据；其宽度通常与处理器的字长相匹配，影响每次传输可移动的数据量。控制总线是一组从 CU 向其他部件传递命令和时序信号（读、写、中断、时钟）的线路。
The interaction of these buses was evident in the fetch cycle: the address bus carried the instruction address, the data bus delivered the instruction, and the control bus signalled a read. A wider data bus can improve performance by fetching more data per clock cycle, but it increases cost and complexity.
这些总线的互作用在取指周期中可见：地址总线传送指令地址，数据总线提供指令，控制总线发出读信号。更宽的数据总线可以通过每个时钟周期获取更多数据来提高性能，但会增加成本和复杂性。
8. Clock Speed and Performance | 时钟速度与性能
The system clock generates a continuous stream of pulses that synchronise all CPU operations. Each pulse defines a clock cycle, during which a certain amount of work can be performed (e.g., a portion of the fetch or execute stage). Clock speed is measured in hertz (Hz), typically gigahertz (GHz) for modern CPUs. A 3 GHz processor cycles 3 × 10⁹ times per second. In general, a higher clock speed means more instructions can be processed per second, improving performance, but there are limits. Power consumption and heat dissipation rise with frequency, leading to thermal throttling if cooling is insufficient. Moreover, the clock speed alone does not determine performance; the amount of work done per cycle (instructions per clock, IPC) is equally important.
系统时钟产生连续的脉冲流，同步所有 CPU 操作。每个脉冲定义了一个时钟周期，在该周期内可以完成一定量的工作（例如，完成取指或执行阶段的一部分）。时钟速度以赫兹（Hz）衡量，现代 CPU 通常以吉赫兹（GHz）为单位。一个 3 GHz 的处理器每秒周期数为 3 × 10⁹。通常，更高的时钟速度意味着每秒可处理更多指令，从而提升性能，但存在限制。功耗和散热随频率升高而增加，如果冷却不足就会导致热降频。而且，时钟速度本身并不决定性能；每个周期完成的工作量（每时钟周期指令数，IPC）同样重要。
In the IB exam, you may be asked to explain why simply doubling the clock speed does not double the actual performance, as memory and bus bottlenecks may stall the pipeline.
在 IB 考试中，你可能会被要求解释为什么简单地将时钟速度翻倍并不能使实际性能翻倍，因为内存和总线瓶颈可能使流水线停顿。
9. Cache Memory and Its Impact | 高速缓存及其影响
Cache is a small, extremely fast memory placed between the CPU and main memory. It stores copies of frequently accessed instructions and data to reduce the average access time. Modern CPUs have multiple levels of cache: Level 1 (L1) is the fastest and smallest, usually split into instruction and data caches and located on the same die as the core; Level 2 (L2) is larger and slightly slower, still per‑core or shared; Level 3 (L3) is larger, slower, and often shared among all cores. When the CPU needs data, it first checks L1, then L2, then L3, and finally main memory. A hit in a faster cache avoids the long latency of a main memory access, significantly boosting performance for repeated data patterns.
高速缓存是位于 CPU 和主存之间的小型、超快内存。它存储经常访问的指令和数据的副本，以减少平均访问时间。现代 CPU 拥有多级高速缓存：一级缓存（L1）最快也最小，通常分为指令缓存和数据缓存，与核心在同一芯片上；二级缓存（L2）较大且稍慢，仍为每核心或共享；三级缓存（L3）更大、更慢，通常在所有核心间共享。当 CPU 需要数据时，它首先检查 L1，然后 L2，再查 L3，最后访问主存。在更快的缓存中命中可以避免主存访问的长延迟，对重复的数据模式显著提升性能。
Key metrics include hit rate and cache latency. A program with good locality of reference will achieve high hit rates and run faster. The IB assessment may ask you to discuss how increasing cache size improves performance, but after a certain point the hit rate gains diminish, and larger caches can be slower and more expensive.
关键指标包括命中率和缓存延迟。具有良好局部性的程序将获得高命中率并运行更快。IB 评估可能要求你讨论增加缓存大小如何提升性能，但在某一点之后命中率的提升会递减，而且更大的缓存可能更慢、更昂贵。
10. Multicore Processing and Parallelism | 多核处理与并行性
A multicore processor contains two or more independent processing units (cores) on a single chip. Each core can execute its own thread simultaneously, enabling true parallel execution. This improves multitasking performance and speeds up applications designed to split work across multiple threads, such as video rendering or scientific simulations. However, to benefit from multiple cores, software must be written to exploit parallelism; sequential programs see little speedup. Coordination between cores requires shared caches and inter‑core communication, adding design complexity.
多核处理器在单个芯片上包含两个或更多独立处理单元（核心）。每个核心可以同时执行自己的线程，实现真正的并行执行。这改进了多任务处理的性能，并能加速为将工作分配到多线程而设计的应用程序，如视频渲染或科学模拟。然而，要受益于多核心，软件必须编写成能利用并行性；顺序程序几乎没有加速。核心之间的协调需要共享缓存和核心间通信，增加了设计复杂性。
IB questions often ask for an evaluation of multicore versus higher clock speed. Multicore provides better energy efficiency and scalability for parallel workloads, while higher clock speed benefits single‑threaded tasks but hits thermal limits sooner.
IB 试题常常要求评估多核与更高时钟速度的优劣。多核为并行工作负载提供更好的能效和可扩展性，而更高时钟速度有利于单线程任务，但更快触及散热极限。
11. Comparing CISC and RISC Architectures | CISC 与 RISC 架构比较
While processor instruction set architectures are broadly divided into Complex Instruction Set Computer (CISC) and Reduced Instruction Set Computer (RISC), the IB syllabus expects a basic comparison. CISC processors (e.g., x86) have a large, complex instruction set with instructions that can perform multi‑step operations in a single instruction, often using microcode. This aims to reduce the number of instructions per program and ease compiler design, but the complex decoding can slow clock speeds and make pipelining harder. RISC processors (e.g., ARM) use a smaller set of simple instructions that are typically executed in one clock cycle. They rely on a large register set and load/store architecture, where only load and store instructions access memory. RISC designs facilitate pipelining and higher clock frequencies, and they are more power‑efficient, which is why they dominate mobile devices.
虽然处理器指令集架构大体分为复杂指令集计算机（CISC）和精简指令集计算机（RISC），但 IB 大纲要求进行基本比较。CISC 处理器（如 x86）拥有庞大、复杂的指令集，单条指令可以执行多步操作，常使用微码。其目的在于减少每个程序的指令数并简化编译器设计，但复杂的译码会降低时钟速度并使流水线化更难。RISC 处理器（如 ARM）使用较小的简单指令集，通常在单个时钟周期内执行。它们依赖大量寄存器集和加载/存储架构，只有加载和存储指令访问内存。RISC 设计有利于流水线化和更高的时钟频率，而且更加节能，这使它们在移动设备中占主导地位。
Modern implementations often blur these boundaries (CISC processors internally translate complex instructions to RISC‑like micro‑operations), but the conceptual distinction remains relevant for exam answers on processor design trade‑offs.
现代实现常常模糊这些界限（CISC 处理器内部将复杂指令转换为类 RISC 微操作），但在回答有关处理器设计权衡的考题时，这一概念区别仍然重要。
12. CPU Performance Evaluation Metrics | CPU 性能评估指标
To quantify CPU performance, several metrics are used. Instructions Per Second (IPS) or Millions of Instructions Per Second (MIPS) measures raw execution rate but does not account for the complexity of instructions (a RISC processor may need more instructions for the same task). Floating‑point Operations Per Second (FLOPS) is critical for scientific workloads. More relevant is the execution time of a given benchmark suite, as it reflects the combined effect of clock speed, IPC, pipeline efficiency, and memory hierarchy. Common benchmarks include SPEC CPU for integer and floating‑point tasks. IB questions often ask you to explain why different benchmarks may rank CPUs differently, emphasising that no single metric tells the whole story.
为量化 CPU 性能，使用了若干指标。指令每秒（IPS）或百万指令每秒（MIPS）衡量原始执行速率，但不考虑指令的复杂性（RISC 处理器完成同一任务可能需要更多指令）。浮点运算每秒（FLOPS）对科学工作负载至关重要。更具相关性的是给定基准测试套件的执行时间，因为它反映了时钟速度、IPC、流水线效率和内存层次的综合影响。常见基准包括面向整数和浮点任务的 SPEC CPU。IB 试题经常要求你解释为何不同基准测试会对 CPU 给出不同排名，强调没有单一指标可以说明全部情况。
Amdahl’s Law is also relevant: the maximum speedup from improving a portion of a system is limited by the fraction of time that the improved part is used. Thus, optimising the CPU alone may bring diminishing returns if the memory system remains slow.
阿姆达尔定律也与此相关：改善系统某一部分所能带来的最大加速比，受限于该改善部分被使用的时间比例。因此，如果内存系统仍然缓慢，仅优化 CPU 可能得到递减的回报。
Mastering these interlinked concepts will equip you to answer exam questions that require evaluation of a system’s performance from multiple angles.
掌握这些相互关联的概念将使你能够回答需要从多个角度评估系统性能的考试题目。
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