📚 Logic Gates Exam Essentials | 逻辑门 考点精讲
Logic gates are the fundamental building blocks of digital circuits. They take one or more binary inputs and produce a single binary output based on a logical rule. In the CIE IGCSE Computer Science exam, you must be able to recognise standard gate symbols, complete truth tables, write Boolean expressions, and analyse or design simple logic circuits. This revision guide breaks down every essential topic to help you score full marks.
逻辑门是数字电路的基本构建块。它们接收一个或多个二进制输入，并根据逻辑规则产生一个二进制输出。在 CIE IGCSE 计算机科学考试中，你必须能识别标准门符号、填写真值表、写出布尔表达式，以及分析或设计简单逻辑电路。本考点精讲将逐一拆解所有核心知识点，助你拿下满分。
1. Binary Logic and Truth Tables | 二进制逻辑与真值表
Computers operate using binary signals – only two states exist: 0 and 1. A logic gate processes these binary inputs electronically. A truth table lists every possible combination of inputs (usually A, B, etc.) and shows the resulting output. For a gate with n inputs, the truth table has 2ⁿ rows.
计算机使用二进制信号工作——只存在两种状态：0 和 1。逻辑门通过电子方式处理这些二进制输入。真值表列出所有可能的输入组合（通常为 A、B 等），并显示对应的输出。对于具有 n 个输入的门，真值表有 2ⁿ 行。
The columns are labelled with the input names and the output. Under CIE conventions, 0 represents FALSE or LOW voltage, while 1 represents TRUE or HIGH voltage. You must memorise the standard truth tables for all basic gates, as they are tested both directly and within larger circuit questions.
列以输入名称和输出为标签。按照 CIE 惯例，0 代表 FALSE 或低电压，1 代表 TRUE 或高电压。你必须记住所有基本门的标准真值表，因为它们不仅会直接考查，还会出现在更复杂的电路题中。
2. NOT Gate | 非门
The NOT gate has only one input and one output. Its job is to invert the signal: if the input is 0, the output is 1; if the input is 1, the output is 0. The Boolean expression is Q = NOT A, written as Q = Ā or Q = ¬A. The symbol is a triangle followed by a small circle (bubble) at the output.
非门只有一个输入和一个输出。它的功能是反转信号：如果输入为 0，则输出为 1；如果输入为 1，则输出为 0。布尔表达式为 Q = NOT A，写作 Q = Ā 或 Q = ¬A。符号为一个三角形，输出端有一个小圆圈（气泡）。
| A | Q |
|---|---|
| 0 | 1 |
| 1 | 0 |
In exam answers, always use the bubble notation when drawing a NOT gate or adding an inverted input to another gate. The bubble indicates inversion.
在考试作答时，绘制非门或在其他门的输入端添加反相时，务必使用气泡符号。气泡表示反相。
3. AND Gate | 与门
The AND gate takes two or more inputs. The output is 1 only when all inputs are 1. If any input is 0, the output is 0. For two inputs A and B, the Boolean expression is Q = A AND B, written as Q = A · B or Q = AB. The standard symbol is a D‑shaped gate with a flat back.
与门有两个或更多输入。只有当所有输入都为 1 时，输出才为 1。如果任意输入为 0，则输出为 0。对于两个输入 A 和 B，布尔表达式为 Q = A AND B，写作 Q = A · B 或 Q = AB。标准符号为一个背面平坦的 D 形门。
| A | B | Q |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Think of an AND gate as requiring every condition to be true before it ‘lets the signal through’. This concept is often tested in alarm systems or safety‑interlock scenarios in the exam.
可以把与门理解为需要所有条件都为真时才“让信号通过”。考试中常在报警系统或安全互锁场景中考查这一概念。
4. OR Gate | 或门
The OR gate also has two or more inputs. The output is 1 if at least one input is 1. The output is 0 only when all inputs are 0. The Boolean expression is Q = A OR B, written as Q = A + B. The symbol is a curved shape with a pointed output, sometimes called a shield shape.
或门也有两个或更多输入。只要至少有一个输入为 1，输出就为 1。只有当所有输入都为 0 时，输出才为 0。布尔表达式为 Q = A OR B，写作 Q = A + B。符号为尖头输出的弧形，有时称为盾形。
| A | B | Q |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
Note the difference from the AND gate: the OR gate does not require all inputs to be 1. Even a single 1 makes the output 1. This is the inclusive OR; when we later consider XOR, the distinction becomes important.
注意与与门的区别：或门不要求所有输入都为 1。即使只有一个 1，输出也为 1。这是包含性或；后续考虑异或门时，这种区别就很重要。
5. NAND Gate | 与非门
A NAND gate is logically equivalent to an AND gate followed by a NOT gate. Its output is the opposite of the AND output: it gives 0 only when all inputs are 1; otherwise the output is 1. The Boolean expression is Q = A NAND B, written as Q = (A · B)̄. The symbol is an AND gate with a bubble at the output.
与非门在逻辑上等效于一个与门后接一个非门。其输出是与门输出的反相：只有当所有输入都为 1 时，输出才为 0；否则输出为 1。布尔表达式为 Q = A NAND B，写作 Q = (A · B)̄。符号为输出端带有一个气泡的与门。
| A | B | Q |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The NAND gate is incredibly important because it is a universal gate – any other logic function can be built using only NAND gates. You will often be asked to construct a given expression using only NAND gates.
与非门极其重要，因为它是一种通用门——仅使用与非门就能构建出任何其他逻辑函数。考试中经常要求你只用与非门来构建给定的表达式。
6. NOR Gate | 或非门
A NOR gate is an OR gate followed by a NOT gate. Its output is 1 only when all inputs are 0. If any input is 1, the output becomes 0. The Boolean expression is Q = A NOR B, written as Q = (A + B)̄. The symbol is an OR gate with a bubble at the output.
或非门是一个或门后接一个非门。只有当所有输入都为 0 时，输出才为 1。只要任意输入为 1，输出就变为 0。布尔表达式为 Q = A NOR B，写作 Q = (A + B)̄。符号为输出端带有一个气泡的或门。
| A | B | Q |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
Like NAND, the NOR gate is also universal. In some textbooks and past papers, you will meet questions comparing NAND-only and NOR-only implementations of a circuit. Practise converting simple expressions into NOR-only logic.
与与非门一样，或非门也是通用门。在一些教材和历年真题中，你会遇到比较仅用与非门和仅用或非门实现电路的问题。练习将简单表达式转换为仅用或非门的逻辑。
7. XOR Gate | 异或门
The XOR (exclusive OR) gate behaves like an OR gate but with one crucial difference: it gives 1 only when the inputs are different. If both inputs are the same (both 0 or both 1), the output is 0. The Boolean expression is Q = A XOR B, sometimes written as Q = A ⊕ B. The standard CIE symbol uses an extra curved line behind the OR shape.
异或门的行为类似或门，但有一个关键区别：只有在输入不同时它才输出 1。如果两个输入相同（都是 0 或都是 1），则输出为 0。布尔表达式为 Q = A XOR B，有时写作 Q = A ⊕ B。CIE 标准符号在或门形状后加了一条额外的弧线。
| A | B | Q |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
XOR is often used in adders and parity checkers. The expression Q = A ⊕ B can also be expressed using AND, OR and NOT as (A · B̄) + (Ā · B). Memorising this equivalent expression can help you answer extended questions.
异或门常用于加法器和奇偶校验器。表达式 Q = A ⊕ B 也可以用与门、或门和非门表示为 (A · B̄) + (Ā · B)。记住这个等价表达式有助于回答扩展题。
8. Universal Gates: NAND and NOR | 通用门：与非门和或非门
A gate is called ‘universal’ if you can use only that type of gate to create NOT, AND and OR functions. NAND and NOR are both universal. For example, a NAND gate with its inputs tied together becomes a NOT gate. Cascading NANDs can produce an AND (NAND + NOT). Similarly, a NOR gate with tied inputs gives a NOT, and a NOR followed by a NOT forms an OR.
如果一个门能够仅使用该类型门来实现非、与和或功能，则称为“通用门”。与非门和或非门都是通用门。例如，将与非门的输入连接在一起就变成了非门。级联与非门可以产生与功能（与非门加非门）。类似地，将或非门的输入连接在一起得到非门，或非门加非门则形成或门。
In the exam, you might see a diagram with several NAND gates and be asked to derive the overall Boolean expression. Start by labelling intermediate points, then simplify step by step. The ability to recognise these universal‑gate combinations is tested frequently.
考试中，你可能会看到一个由多个与非门组成的图表，并被要求推导出整体布尔表达式。从标注中间点开始，然后逐步化简。识别这些通用门组合的能力经常被考查。
9. Drawing Logic Circuits from Boolean Expressions | 根据布尔表达式绘制逻辑电路
Exam questions often provide a Boolean expression such as Q = (A · B) + (C̄) and ask you to draw the corresponding logic circuit. Follow a systematic approach: identify the order of operations – NOTs first, then ANDs, then ORs – unless brackets force a different sequence. Draw a gate for every operator, label all connections, and add any required NOT bubbles.
考题通常给出一个布尔表达式，如 Q = (A · B) + (C̄)，并要求你画出相应的逻辑电路。遵循系统化的方法：确定运算顺序——先非、再与、后或——除非括号强制改变顺序。为每个运算符画一个门，标注所有连线，并添加所需的非门气泡。
Remember that CIE uses specific symbols: the AND gate has a straight left side, the OR gate has a curved back. If an input is inverted, you can either draw a separate NOT gate or simply add a bubble directly on the receiving gate input. Both are acceptable, but the bubble on the input is neater and more common in mark schemes.
记住 CIE 使用特定的符号：与门左侧是一条直线，或门有一个弧形背部。如果输入是反相的，你可以单独画一个非门，也可以直接在接收门输入端添加气泡。两种方式均可，但输入端气泡更简洁，在评分标准中更常见。
10. Completing Truth Tables for Combined Circuits | 填写组合电路的真值表
For a circuit with multiple gates, you must track every internal signal. Add extra columns to your truth table for intermediate outputs. For example, if the expression is Q = (A · B) + C̄, you might have columns for A, B, C, then D = A · B, E = C̄, and finally Q = D + E. Fill in each row systematically.
对于包含多个门的电路，你必须追踪每个内部信号。在真值表中添加额外的列来表示中间输出。例如，若表达式为 Q = (A · B) + C̄，你可以包含列 A、B、C，然后是 D = A · B，E = C̄，最后是 Q = D + E。逐行系统地填写。
A common mistake is to overlook that a change in one input could affect several gates simultaneously. Double‑check your work by applying the Boolean expression directly and comparing with the circuit result. Practise with past papers – CIE expects you to complete truth tables for circuits with up to three inputs and two levels of logic.
一个常见错误是忽略了一个输入的变化可能同时影响多个门。通过直接应用布尔表达式并与电路结果进行比较来复核你的答案。用历年真题进行练习——CIE 要求你为最多三个输入和两层逻辑的电路填写真值表。
11. Exam Tips and Common Pitfalls | 考试技巧与常见失分点
Always check whether the question requires a symbol, a truth table, a Boolean expression or a drawn circuit. Read the command word carefully: ‘Draw’ means you must use standard gate symbols, ‘Complete’ means fill in the truth table, and ‘Write’ means give the expression. Marks are awarded for correct labelling and neat presentation.
务必检查题目要求的是符号、真值表、布尔表达式还是电路图。仔细阅读指令词：“Draw”表示你必须使用标准门符号，“Complete”表示填写真值表，“Write”表示给出表达式。正确标注和整洁的呈现都会获得分数。
Watch out for inverted inputs in expressions like Q = Ā + B. This is an OR gate with a NOT on A only, not a NOR gate. A bubble only on one input does not make the entire gate a NAND or NOR. Also, ensure you use the correct bubble placement when an output is inverted. Finally, never leave a truth table blank even if the expression looks daunting – work column by column.
注意像 Q = Ā + B 这样的表达式中带反相的输入。这是一个只在 A 上加非门的或门，而不是一个或非门。仅在一个输入上加气泡并不会使整个门变成与非门或或非门。此外，当输出反相时，确保气泡位置正确。最后，即使表达式看起来令人生畏，也绝不要把真值表留空——逐列填写。
12. Quick Revision Summary | 快速复习总结
Recap of key Boolean expressions and truth table outputs you must know from memory:
必须记住的关键布尔表达式和真值表输出回顾：
- NOT: Q = Ā — output opposite to input.
- AND: Q = A · B — output 1 only when both inputs are 1.
- OR: Q = A + B — output 1 if any input is 1.
- NAND: Q = (A · B)̄ — output 0 only when both inputs are 1.
- NOR: Q = (A + B)̄ — output 1 only when both inputs are 0.
- XOR: Q = A ⊕ B — output 1 when inputs differ.
- 非：Q = Ā — 输出与输入相反。
- 与：Q = A · B — 仅当两个输入都为 1 时输出 1。
- 或：Q = A + B — 任意输入为 1 则输出 1。
- 与非：Q = (A · B)̄ — 仅当两个输入都为 1 时输出 0。
- 或非：Q = (A + B)̄ — 仅当两个输入都为 0 时输出 1。
- 异或：Q = A ⊕ B — 输入不同时输出 1。
Understanding how to combine these gates, how to convert between circuits and expressions, and how to identify universal gate implementations will give you a solid foundation for the entire logic gate section of the CIE IGCSE Computer Science examination.
理解如何组合这些门、如何在电路和表达式之间转换，以及如何识别通用门实现，将为你在 CIE IGCSE 计算机科学考试中整个逻辑门部分打下坚实基础。
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