📚 Computer Architecture Key Concepts for GCSE OCR | 计算机体系结构考点精讲
Mastering computer architecture is essential for the GCSE OCR Computer Science exam. This guide breaks down the CPU, von Neumann design, registers, the fetch‑decode‑execute cycle, and factors like clock speed, cache, and cores – all mapped to the J277 specification. We will also explore embedded systems and what makes them different. Each section pairs an English explanation with its Chinese translation, helping you build both knowledge and bilingual confidence.
掌握计算机体系结构对 GCSE OCR 计算机科学考试至关重要。本指南将拆解中央处理器、冯·诺依曼设计、寄存器、取指‑译码‑执行周期，以及时钟频率、缓存与核心数量等性能因素——全部对应 J277 规格。我们还将探讨嵌入式系统及其独特之处。每个章节都配有中英文对照解释，帮助你构建知识的同时提升双语能力。
1. What is a CPU? | 什么是中央处理器？
The Central Processing Unit (CPU) is the brain of the computer. It processes instructions from programs by performing calculations, making logical decisions, and moving data. Every time you open an app, type a key, or stream a video, the CPU executes millions of instructions per second to make it happen. In the OCR GCSE course, the CPU is treated as a general‑purpose processor that follows the von Neumann architecture.
中央处理器（CPU）是计算机的大脑。它通过执行计算、作出逻辑判断和移动数据来处理程序指令。每当你打开一个应用、按下一个键或流式播放视频时，CPU 每秒执行数百万条指令来实现这些操作。在 OCR GCSE 课程中，CPU 被视为遵循冯·诺依曼体系结构的通用处理器。
The CPU is not one single component; it is a complex chip containing several key parts: the Control Unit, the Arithmetic Logic Unit, a set of registers, and cache memory. These parts work together to fetch, decode, and execute instructions in a continuous cycle. Understanding how they interact is central to the exam.
CPU 并非单一元件，而是一个包含多个关键部分的复杂芯片：控制单元、算术逻辑单元、一组寄存器以及缓存。这些部分协同工作，在一个连续的周期中完成取指、译码和执行指令。理解它们如何相互作用是考试的核心。
2. The Von Neumann Architecture | 冯·诺依曼体系结构
The von Neumann architecture is the foundational design used by almost all modern computers. Named after mathematician John von Neumann, it describes a system where both program instructions and data are stored in the same memory unit. This stored‑program concept allows the CPU to fetch instructions from memory, modify them if needed, and execute them sequentially.
冯·诺依曼体系结构是几乎所有现代计算机所使用的基础设计。它以数学家约翰·冯·诺依曼命名，描述了一种将程序指令和数据存储在同一个存储器中的系统。这种存储程序概念使得 CPU 能够从内存中取出指令，必要时修改它们，并顺序执行。
Key features include the Memory Unit (often RAM) that holds both instructions and data, the CPU which contains the Control Unit and ALU, and buses that connect them. Data and instructions travel along the data bus, addresses are sent via the address bus, and control signals use the control bus. This structure makes computers flexible because different programs can simply be loaded into memory and run.
关键特征包括：存储单元（通常是 RAM）同时存放指令和数据；包含控制单元和 ALU 的 CPU；以及连接它们的总线。数据和指令沿数据总线传输，地址通过地址总线发送，控制信号则使用控制总线。这种结构使计算机非常灵活，因为不同的程序只需加载到内存中即可运行。
3. The Control Unit (CU) | 控制单元
The Control Unit (CU) is the component that orchestrates the operation of the CPU. It does not process data itself; instead, it directs the flow of data between the CPU, memory, and input/output devices by sending control signals. Think of it as a conductor in an orchestra, telling each section when to play.
控制单元（CU）是协调 CPU 运行的组件。它本身并不处理数据，而是通过发送控制信号来指挥数据在 CPU、内存和输入/输出设备之间的流动。可以把它想象成交响乐团的指挥，告诉每个声部何时演奏。
The CU decodes the instruction that has been fetched from memory. Based on the opcode (the operation code), it activates the correct circuits in the ALU, routes data between registers, and manages the timing of the fetch‑decode‑execute cycle. Every tick of the clock, the CU issues the signals that keep everything in step.
控制单元对从内存中取出的指令进行译码。它根据操作码（opcode）激活 ALU 中正确的电路，在寄存器之间传送数据，并管理取指‑译码‑执行周期的时序。每一个时钟周期，控制单元都会发出信号，使所有部件保持同步。
4. The Arithmetic Logic Unit (ALU) | 算术逻辑单元
The Arithmetic Logic Unit (ALU) is where the actual calculations and logical operations take place. It can perform arithmetic operations such as addition, subtraction, multiplication, and division, as well as logic operations like AND, OR, NOT, and comparisons. The ALU is the number‑cruncher of the CPU.
算术逻辑单元（ALU）是实际执行计算和逻辑操作的地方。它能够执行加法、减法、乘法和除法等算术运算，以及 AND、OR、NOT 和比较等逻辑运算。ALU 是 CPU 中的数字计算器。
When the Control Unit decodes an instruction that involves a calculation, it sends the required data to the ALU and tells it which operation to perform. The ALU often uses a special register called the accumulator (ACC) to temporarily hold results. The outcomes of operations can influence the program flow – for example, if a comparison shows two values are equal, the CU may trigger a jump in the program.
当控制单元译码出一条涉及计算的指令时，它会把所需数据发送给 ALU，并告诉它执行哪种操作。ALU 通常使用一个称为累加器（ACC）的特殊寄存器来临时保存结果。运算结果会影响程序流程——例如，如果比较显示两个值相等，控制单元可能会触发程序跳转。
5. CPU Registers: MAR, MDR, PC, ACC | 中央处理器寄存器
Registers are small, extremely fast memory locations located directly inside the CPU. They hold data, instructions, or addresses that the CPU needs to access instantly. The four registers you must know for OCR GCSE are the Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), and Accumulator (ACC).
寄存器是直接位于 CPU 内部的极小但极快的内存位置。它们存放着 CPU 需要立刻访问的数据、指令或地址。你必须为 OCR GCSE 掌握的四个寄存器是：程序计数器（PC）、存储器地址寄存器（MAR）、存储器数据寄存器（MDR）和累加器（ACC）。
- Program Counter (PC): Holds the memory address of the next instruction to be fetched. After each fetch, it increments to point to the next instruction, unless a jump occurs.
- 程序计数器（PC）： 存放下一条待取指令的内存地址。每次取指后它都会递增以指向下一条指令，除非发生跳转。
- Memory Address Register (MAR): Holds the address of the memory location that the CPU is about to read from or write to. It is connected to the address bus.
- 存储器地址寄存器（MAR）： 存放 CPU 即将读取或写入的内存地址。它连接着地址总线。
- Memory Data Register (MDR): Holds the actual data or instruction that has been fetched from memory, or that is to be written to memory. It is connected to the data bus.
- 存储器数据寄存器（MDR）： 存放从内存中取出的实际数据或指令，或者即将写入内存的数据。它连接着数据总线。
- Accumulator (ACC): Stores the intermediate results of calculations performed by the ALU. Many ALU operations use the accumulator as both an input and output.
- 累加器（ACC）： 存储 ALU 所执行计算的中间结果。许多 ALU 操作使用累加器作为输入和输出。
6. The Fetch‑Decode‑Execute Cycle | 取指‑译码‑执行周期
The fetch‑decode‑execute cycle is the continuous process that the CPU follows from the moment it is powered on until shutdown. Every single instruction goes through these three stages at speeds determined by the clock. This cycle is sometimes called the instruction cycle.
取指‑译码‑执行周期是 CPU 从开机直到关机所持续遵循的过程。每条指令都会以由时钟决定的速度经历这三个阶段。这个周期有时也被称为指令周期。
Fetch: The address in the PC is copied to the MAR. The CU sends a read signal on the control bus, and the instruction at that address is placed into the MDR via the data bus. The instruction is then copied to the Current Instruction Register (CIR). The PC is incremented to point to the next instruction.
取指： PC 中的地址被复制到 MAR。CU 在控制总线上发送读信号，该地址处的指令通过数据总线被放入 MDR。随后指令被复制到当前指令寄存器（CIR）。PC 递增以指向下一条指令。
Decode: The CU interprets the instruction held in the CIR. It identifies the opcode and the operand(s). The opcode tells the CU which operation to perform, while the operand might be data or an address.
译码： CU 对 CIR 中的指令进行解析。它识别出操作码和操作数。操作码告诉 CU 要执行哪种操作，而操作数可能是数据或地址。
Execute: The CU sends signals to the relevant parts of the CPU to carry out the instruction. This might involve reading data from memory into the MDR, performing a calculation in the ALU and storing the result in the ACC, or sending data to an output device. The cycle then repeats from the fetch stage.
执行： CU 向 CPU 的相关部件发送信号来执行指令。这可能涉及将数据从内存读入 MDR，在 ALU 中执行计算并将结果存入 ACC，或者将数据发送到输出设备。然后该周期从取指阶段开始重复。
7. Clock Speed | 时钟频率
Clock speed measures how many cycles the CPU can execute per second, expressed in Hertz (Hz). Modern processors run at gigahertz speeds, meaning billions of cycles per second. For example, a 3.5 GHz processor can complete 3.5 billion cycles in one second. The clock synchronises all components via a metronome‑like pulse generated by an internal crystal oscillator.
时钟频率衡量 CPU 每秒能执行多少个周期，单位是赫兹（Hz）。现代处理器以吉赫频率运行，意味着每秒数十亿个周期。例如，一颗 3.5 GHz 的处理器每秒可以完成 35 亿个周期。时钟通过内部晶体振荡器产生的节拍器般的脉冲来同步所有部件。
In theory, a higher clock speed means more instructions are processed per second, so the computer feels faster. However, clock speed is not the only factor influencing performance. Other factors such as cache size, the number of cores, and the type of instructions being processed also matter. Overclocking can increase clock speed but generates excess heat, which must be managed to avoid damage.
理论上，更高的时钟频率意味着每秒处理更多的指令，因此计算机感觉更快。然而，时钟频率并非影响性能的唯一因素。缓存大小、核心数量以及所处理指令的类型也同样重要。超频可以提高时钟频率，但会产生额外热量，必须加以管理以避免损坏。
8. Cache Memory | 缓存
Cache is a small amount of very fast memory located inside or very close to the CPU. It stores frequently used instructions and data so that the CPU can access them far more quickly than fetching them from RAM. Accessing data from RAM is hundreds of times slower than from cache, so a larger, well‑designed cache can dramatically raise performance.
缓存是位于 CPU 内部或与之非常接近的一小块极快内存。它存储常用的指令和数据，使得 CPU 比从 RAM 获取时能快得多的速度访问它们。从 RAM 访问数据比从缓存慢数百倍，因此容量更大、设计良好的缓存可以显著提高性能。
CPUs typically have multiple levels of cache: Level 1 (L1) is the smallest and fastest, often built directly into the core; Level 2 (L2) is slightly larger but a bit slower; and Level 3 (L3) is shared among cores and larger still. The more cache a CPU has, the less often it needs to wait for main memory, leading to a noticeable speed improvement in tasks such as gaming, video editing, and running multiple programs.
CPU 通常拥有多级缓存：一级缓存（L1）容量最小且速度最快，通常直接内置于核心中；二级缓存（L2）稍大但稍慢；三级缓存（L3）在核心间共享，容量更大。CPU 拥有的缓存越多，它需要等待主存的次数就越少，从而在游戏、视频编辑和运行多个程序等任务中带来明显的速度提升。
9. Number of Cores | 多核处理器
A core is a complete processing unit that can independently read and execute instructions. A multi‑core CPU contains two or more cores on a single chip, for example a quad‑core processor has four cores. Multi‑core designs allow the computer to process several instructions truly simultaneously, which improves multitasking and the performance of software written to utilise multiple threads.
核心是一个完整的处理单元，能够独立读取并执行指令。多核 CPU 在单个芯片上包含两个或更多核心，例如四核处理器拥有四个核心。多核设计使计算机能够真正同时处理多条指令，从而改善多任务处理能力以及为利用多线程而编写的软件的性能。
Simply adding more cores does not multiply performance by the number of cores. Many programs are not designed to split work across multiple cores, so the speed increase depends on how well the software is parallelised. For general use, dual‑core or quad‑core processors offer a good balance between cost and performance, while high‑end tasks like video rendering benefit from 8‑core or even 16‑core chips.
仅仅增加更多核心并不会使性能按核心数量成倍增长。许多程序并没有设计为将工作分配到多个核心上，因此速度提升取决于软件的并行化程度。对于一般使用，双核或四核处理器提供了成本与性能之间的良好平衡，而视频渲染等高端任务则可以受益于 8 核甚至 16 核芯片。
10. Embedded Systems | 嵌入式系统
An embedded system is a computer built into a larger device to perform a dedicated, pre‑programmed function. Unlike general‑purpose computers like laptops or smartphones, embedded systems are typically designed to do one task repeatedly and efficiently with minimal user interaction. They are everywhere: in microwave ovens, washing machines, traffic lights, car engine control units, and medical devices.
嵌入式系统是一种内置于更大设备中的计算机，用于执行专用的、预先编程的功能。与笔记本电脑或智能手机等通用计算机不同，嵌入式系统通常设计为以最少的用户交互重复并高效地执行一项任务。它们无处不在：微波炉、洗衣机、交通信号灯、汽车发动机控制单元和医疗设备中都有嵌入式系统。
Embedded systems often have limited resources: a lower‑power processor, less memory, and no hard disk. Their software, called firmware, is stored in ROM or flash memory. Because they are optimised for a specific task, they can be made very reliable, energy‑efficient, and cheap. When studying for the OCR exam, you should be able to give examples and explain why a dedicated embedded system is preferred over a full personal computer in these use cases.
嵌入式系统通常资源有限：功耗较低的处理器、较少的内存，且没有硬盘。它们的软件称为固件，存储在 ROM 或闪存中。由于针对特定任务进行了优化，它们可以做得非常可靠、节能且廉价。在为 OCR 考试学习时，你应该能够举例说明，并解释在这些应用场景中为什么专用嵌入式系统比完整的个人电脑更受欢迎。
11. The Role of Buses in Architecture | 总线在体系结构中的作用
Buses are the communication highways that connect the CPU, memory, and input/output devices. The three main buses are the address bus, data bus, and control bus. The address bus carries memory addresses from the CPU to memory (it is unidirectional), the data bus carries data and instructions in both directions (bidirectional), and the control bus carries control signals such as read, write, and clock timing signals.
总线是连接 CPU、内存和输入/输出设备的通信高速公路。三条主要总线是地址总线、数据总线和控制总线。地址总线将内存地址从 CPU 传送到内存（单向），数据总线在两个方向上传输数据和指令（双向），而控制总线则传输读、写和时钟定时信号等控制信号。
The width of the address bus determines how many unique memory locations the CPU can address. For example, a 32‑bit address bus can directly address 232 memory locations, which equals 4 GB of RAM. A wider data bus allows more bits to be transferred per clock cycle, increasing potential speed. Understanding buses helps explain why a 32‑bit CPU cannot use more than 4 GB of RAM without tricks.
地址总线的宽度决定了 CPU 能够寻址多少个唯一内存位置。例如，一条 32 位的地址总线可以直接寻址 232 个内存位置，这等于 4 GB 的 RAM。更宽的数据总线允许每个时钟周期传输更多比特，从而提升潜在速度。理解总线有助于解释为什么 32 位 CPU 在不使用技巧的情况下无法使用超过 4 GB 的内存。
12. Exam Tips and Common Pitfalls | 考试技巧与常见误区
When answering OCR questions on computer architecture, be precise with terminology. Do not confuse the MAR with the MDR; the MAR holds an address (pointing to a location), while the MDR holds the data or instruction itself. Also remember that the Program Counter (PC) holds the address of the next instruction, not the current one.
在回答 OCR 关于计算机体系结构的问题时，术语要准确。不要混淆 MAR 和 MDR；MAR 存放地址（指向一个位置），而 MDR 存放数据或指令本身。还要记住，程序计数器（PC）存放下一条指令的地址，而不是当前指令的地址。
Students often lose marks by giving vague descriptions of the fetch‑decode‑execute cycle. Be ready to describe each step in order, naming the registers involved. Avoid saying ‘the CPU gets the data’ – instead say ‘the address from the PC is loaded into the MAR, the instruction is fetched from memory into the MDR…’. Specificity shows real understanding.
学生常因对取指‑译码‑执行周期的描述模糊而失分。要准备好按顺序描述每一步，并说出所涉及的寄存器。不要说“CPU 获取数据”——而要说“来自 PC 的地址被加载到 MAR 中，指令从内存中被取入 MDR……”。具体化能体现真正的理解。
For performance questions, never claim that ‘adding more cache always speeds up a computer’ or ‘more cores always make it faster’. Discuss the context: software must be written to use multiple cores, and cache only helps if the data is reused frequently. Linking factors together shows a deeper level of analysis expected at GCSE.
对于性能问题，永远不要声称“增加更多缓存总是能加快计算机速度”或“更多核心总是让它更快”。要讨论具体情境：软件必须被编写成能够利用多核，并且缓存仅在数据被频繁重用时才提供帮助。将多个因素联系起来显示了 GCSE 所期望的更深层次的分析。
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