📚 Logic Gates Exam Essentials | 逻辑门 考点精讲
Logic gates are the fundamental building blocks of digital circuits. In OCR A-Level Computer Science, you need to master their symbols, truth tables, Boolean expressions, and how to combine them into functional circuits such as adders. This article breaks down every key concept you will be tested on, from simple NOT gates to the application of De Morgan’s laws and algebraic simplification.
逻辑门是数字电路的基本构建块。在 OCR A-Level 计算机科学中，你需要掌握它们的符号、真值表、布尔表达式，以及如何将它们组合成加法器等功能电路。本文分解了考试中的每一个关键概念，从简单的非门到德摩根定律的应用和代数化简。
1. Introduction to Logic Gates | 逻辑门简介
A logic gate is an electronic component that takes one or more binary inputs and produces a single binary output. The output depends solely on the current input values, making these circuits combinational. In the OCR specification, you must recognise and use six basic gates: NOT, AND, OR, NAND, NOR, XOR, and their extended form XNOR.
逻辑门是一种电子元件，它接收一个或多个二进制输入并产生单个二进制输出。输出完全取决于当前的输入值，因此这些电路是组合逻辑电路。在 OCR 考纲中，你必须识别并使用六种基本门：非门、与门、或门、与非门、或非门、异或门以及它们的扩展形式同或门。
All gates can be represented by standard symbols, Boolean expressions, and truth tables. In exam questions, you are often asked to draw a logic circuit from a Boolean expression, complete a truth table, or simplify an expression using Boolean algebra. A clear grasp of each gate’s behaviour is essential before tackling larger circuits.
所有门都可以用标准符号、布尔表达式和真值表表示。在考试题目中，你经常需要根据布尔表达式画出逻辑电路、填写真值表，或者用布尔代数化简表达式。在挑战更大的电路之前，清晰掌握每一个门的行为至关重要。
2. NOT Gate | 非门
The NOT gate, also called an inverter, has a single input. It outputs the opposite binary value: if the input is 1, the output is 0, and vice versa. Its Boolean expression is written as Q = ¬A or simply Q = A’.
非门，也称反相器，只有一个输入。它输出相反的二进制值：如果输入是 1，输出为 0，反之亦然。它的布尔表达式写作 Q = ¬A 或简写为 Q = A’。
The truth table is the simplest possible:
真值表是最简单的：
| A | Q |
|---|---|
| 0 | 1 |
| 1 | 0 |
In circuit design, the NOT gate is often used to provide the complementary value needed for other operations. It is represented by a triangle with a small bubble at the output.
在电路设计中，非门常用于提供其他操作所需的互补值。它由一个三角形和输出端的一个小圆圈表示。
3. AND Gate | 与门
An AND gate outputs 1 only if all its inputs are 1. For a two‑input AND gate, the output is 0 in every other case. The Boolean expression is Q = A · B.
与门仅在所有输入都为 1 时才输出 1。对于两输入与门，其他情况下输出均为 0。布尔表达式为 Q = A · B。
| A | B | Q |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
AND gates are essential whenever a condition requires multiple inputs to be true simultaneously. In processor design, they are used in control units to generate enable signals only when specific opcode bits are all active.
当需要多个输入同时为真时，与门至关重要。在处理器设计中，它们被用于控制单元，仅当特定操作码位全都有效时才生成使能信号。
4. OR Gate | 或门
An OR gate outputs 1 if at least one input is 1. Its Boolean expression is Q = A + B. The only time the output is 0 is when both inputs are 0.
或门在至少一个输入为 1 时输出 1。其布尔表达式为 Q = A + B。只有当两个输入都为 0 时，输出才为 0。
| A | B | Q |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
OR logic appears in selection circuits and interrupt request lines: any active request can trigger the processor’s attention. Combined with AND and NOT, it forms the basis for most digital systems.
或逻辑出现在选择电路和中断请求线路中：任何活动的请求都可以触发处理器的注意。与与门和非门结合，它构成了大多数数字系统的基础。
5. NAND Gate | 与非门
A NAND gate is the exact opposite of an AND gate: its output is 0 only when all inputs are 1. The Boolean expression is Q = ¬(A · B) or Q = (A · B)’. This gate is of particular interest because it is functionally complete—any logic function can be built using only NAND gates.
与非门是与门的精确反相：仅当所有输入都为 1 时输出才为 0。布尔表达式为 Q = ¬(A · B) 或 Q = (A · B)’。这个门特别重要，因为它功能完备——任何逻辑函数都可以仅用与非门构建。
| A | B | Q |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Because NAND gates are cheap to fabricate and reduce chip count, you will often see exam questions asking you to create an AND, OR, or NOT using only NANDs. This tests your understanding of De Morgan’s laws.
由于与非门制造成本低且能减少芯片数量，你常会看到考题要求仅用与非门实现与门、或门或非门。这测试你对德摩根定律的理解。
6. NOR Gate | 或非门
The NOR gate produces the inverted output of an OR gate: its output is 1 only when all inputs are 0. The Boolean expression is Q = ¬(A + B) or Q = (A + B)’. Like NAND, NOR is functionally complete.
或非门产生或门的反相输出：仅当所有输入都为 0 时输出才为 1。布尔表达式为 Q = ¬(A + B) 或 Q = (A + B)’。与与非门一样，或非门功能完备。
| A | B | Q |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
In memory cells and latches, NOR gates are used to hold state. Understanding both NAND and NOR gives you flexibility in circuit design, as some logic families favour one type over the other.
在存储单元和锁存器中，或非门用于保持状态。理解与非门和或非门，能为电路设计带来灵活性，因为有些逻辑系列更倾向于其中一种类型。
7. XOR and XNOR Gates | 异或门和同或门
The Exclusive‑OR (XOR) gate outputs 1 when an odd number of inputs are 1. For two inputs, that means A and B must be different. Its Boolean expression is Q = A ⊕ B, which can be expanded to Q = (A · B’) + (A’ · B). The truth table is:
异或门（XOR）在输入中 1 的个数为奇数时输出 1。对于两个输入，这意味着 A 和 B 必须不同。其布尔表达式为 Q = A ⊕ B，可展开为 Q = (A · B’) + (A’ · B)。真值表如下：
| A | B | Q |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The XNOR (Exclusive‑NOR) gate is the complement of XOR; it outputs 1 when the two inputs are equal. Its expression is Q = A ⊙ B or Q = (A ⊕ B)’. XNOR is often used as an equality comparator.
同或门（XNOR）是异或门的补码；当两个输入相等时输出 1。它的表达式为 Q = A ⊙ B 或 Q = (A ⊕ B)’。同或门常用作相等比较器。
XOR gates are critical in arithmetic circuits: the sum bit of a half adder is simply A ⊕ B. You will also meet them in parity checkers and error detection codes.
异或门在算术电路中至关重要：半加器的和位就是 A ⊕ B。你还会在奇偶校验器和错误检测码中遇到它们。
8. Truth Tables and Boolean Expressions | 真值表和布尔表达式
A truth table exhaustively lists every possible input combination and the corresponding output of a logic circuit. For n inputs, a truth table has 2ⁿ rows. In OCR exams, you are regularly required to draw a truth table for a given logic circuit or Boolean expression.
真值表详尽列出了每个可能的输入组合以及逻辑电路相应的输出。对于 n 个输入，真值表有 2ⁿ 行。在 OCR 考试中，经常要求你为给定的逻辑电路或布尔表达式画出真值表。
To write a Boolean expression from a truth table, you can use the sum‑of‑products method. Identify the rows where the output is 1, form a product term (AND) for each by including each variable in its true or complemented form, and then OR all those products together. For example, if Q = 1 when A=0, B=1 and when A=1, B=1, the expression is Q = A’·B + A·B, which simplifies to Q = B.
要从真值表写出布尔表达式，可以使用积之和（SUM OF PRODUCTS）方法。找出输出为 1 的行，为每一行形成一个乘积项（与运算），其中包含每个变量的原变量或补变量形式，然后将所有这些乘积项相或。例如，若 Q = 1 出现在 A=0, B=1 以及 A=1, B=1，表达式为 Q = A’·B + A·B，可化简为 Q = B。
9. De Morgan’s Laws | 德摩根定律
De Morgan’s laws allow you to transform expressions so that AND becomes OR (and vice versa) when applying negation. The two laws are:
德摩根定律允许你变换表达式，使得在求反时与运算变为或运算，反之亦然。这两条定律是：
(A + B)’ = A’ · B’
(A · B)’ = A’ + B’
These rules are essential when you need to implement a circuit using only NAND or NOR gates. For instance, the OR function using NANDs: A + B = (A’ · B’)’, which is a NAND of the inverted inputs. You can obtain the inversions by tying the inputs of a NAND together to form a NOT.
当你需要仅用与非门或或非门实现电路时，这些规则必不可少。例如，用与非门实现或功能：A + B = (A’ · B’)’，即对反相输入进行与非运算。通过将与非门的输入连在一起便可得到非门。
Exam questions frequently test your ability to simplify a circuit by applying De Morgan’s laws and then redraw it with a single gate type. Practise rewriting expressions until the transformation becomes second nature.
考题经常测试你运用德摩根定律简化电路，然后用单一门类型重画电路的能力。请多加练习改写表达式，直至变换变得得心应手。
10. Combinational Logic Circuits | 组合逻辑电路
A combinational logic circuit is one where the outputs depend only on the present inputs. There is no memory element involved. In your exam, you may be presented with a diagram containing multiple gates and asked to determine the Boolean expression, complete a truth table, or spot simplification opportunities.
组合逻辑电路是指输出仅取决于当前输入的电路，不涉及存储元件。在考试中，你可能会遇到包含多个门级的电路图，要求你确定布尔表达式、完成真值表，或找出可以简化的地方。
When tackling these diagrams, label the output of each gate with a sub‑expression, then combine them following the circuit flow. This method prevents errors in large circuits. Always check if two identical terms appear that could be simplified, e.g., A + A’·B = A + B.
处理这些电路图时，先用子表达式标出每个门的输出，然后顺着电路流将其合并。这种方法能防止出现大电路中的错误。请始终检查是否出现了可以化简的相同项，比如 A + A’·B = A + B。
Standard combinational blocks like multiplexers and decoders are built from these fundamental gates, but for logic gate questions, the focus is on hand‑crafted channel designs and their optimisation.
像多路复用器和译码器这样的标准组合模块是由这些基础门构建的，但在逻辑门题目中，重点是手工设计的通路及其优化。
11. Simplification with Boolean Algebra | 布尔代数化简
Simplifying Boolean expressions reduces the number of gates and inputs, saving cost and improving speed. The OCR specification expects you to use the basic identities of Boolean algebra:
化简布尔表达式可以减少门和输入的数量，从而节约成本并提高速度。OCR 考纲期望你使用布尔代数的基本恒等式：
- A + 0 = A and A · 1 = A — identity laws
- A + 1 = 1 and A · 0 = 0 — annulment
- A + A = A and A · A = A — idempotent
- A + A’ = 1 and A · A’ = 0 — complement
- (A’)’ = A — double negation
- A + A·B = A — absorption
化简布尔代数需要运用基本恒等式，例如同一律、零一律、幂等律、互补律以及吸收律。上述列表中展示了常用的恒等式。
A typical exam task gives you an unsimplified expression like Q = A·B + A·B’. By factoring, Q = A·(B + B’) = A·1 = A, showing that a two‑gate circuit can be replaced by a single wire. Always aim for the minimal SOP or POS form.
典型的考题会给出一个未化简的表达式，如 Q = A·B + A·B’。通过提取公因子，Q = A·(B + B’) = A·1 = A，这表明一个两门级电路可以用一根导线替代。务必以最简的积之和或和之积形式为目标。
Karnaugh maps are also covered in the OCR specification, but they are a separate topic; algebraic simplification is the direct skill tested most often under the logic gates heading.
卡诺图也在 OCR 考纲范围内，但属于一个独立主题；在逻辑门标题下，代数化简是最常被直接测试的技能。
12. Half Adder and Full Adder | 半加器和全加器
Adders are the classic application of logic gates and appear repeatedly in exams. A half adder adds two single binary digits, producing a sum and a carry out. Its logic is:
加法器是逻辑门的经典应用，在考试中反复出现。半加器将两个单二进制位相加，产生一个和位与一个进位。其逻辑为：
Sum = A ⊕ B
Carry = A · B
The circuit therefore consists of one XOR gate and one AND gate. A full adder extends this to add three inputs: A, B, and a carry in (Cin). Its sum and carry out are given by:
该电路因此由一个异或门和一个与门组成。全加器则扩展为将三个输入相加：A、B 和进位输入 Cin。其和位与进位输出为：
Sum = A ⊕ B ⊕ Cin
Cout = (A · B) + (Cin · (A ⊕ B))
You can build a full adder either from two half adders and an OR gate, or directly from logic gates. Knowing how to construct and analyse these circuits is vital, as they form the core of the Arithmetic Logic Unit (ALU).
你可以用两个半加器和一个或门构成全加器，也可以直接由逻辑门搭建。了解如何构建和分析这些电路至关重要，因为它们构成了算术逻辑单元（ALU）的核心。
In word‑length adders, multiple full adders are cascaded, connecting Cout of one stage to Cin of the next. This ripple‑carry arrangement demonstrates how simple gates scale to perform binary addition on bytes and words.
在字长加法器中，多个全加器被级联，将前一级的 Cout 连接到下一级的 Cin。这种行波进位结构展示了简单门如何扩展，以对字节和字执行二进制加法。
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