Memory in Computer Systems: IB & Edexcel Key Concepts | IB Edexcel 计算机：存储器考点精讲

📚 Memory in Computer Systems: IB & Edexcel Key Concepts | IB Edexcel 计算机：存储器考点精讲

Memory is the component of a computer system that stores data and instructions, either temporarily or permanently. Understanding memory hierarchy, types of RAM and ROM, cache mapping, virtual memory, and addressing modes is essential for IB and Edexcel Computer Science exams. This guide breaks down every key concept with clear explanations and exam-focused details.

存储器是计算机系统中用于临时或永久存储数据和指令的部件。理解存储器层次结构、RAM 和 ROM 的类型、缓存映射、虚拟内存以及寻址模式，对于 IB 和 Edexcel 计算机科学考试至关重要。本指南将逐一剖析每个关键概念，提供清晰讲解并紧扣考点。

1. Memory Hierarchy Overview | 存储器层次结构概述

The memory hierarchy organises storage into levels based on speed, cost, and capacity. At the top, registers inside the CPU are fastest but smallest and most expensive per bit. Below them are cache (L1, L2, L3), main memory (RAM), and secondary storage (SSD, HDD). The principle of locality ensures that frequently accessed data moves up the hierarchy.

存储器层次结构根据速度、成本和容量将存储划分为不同级别。最顶层是 CPU 内部的寄存器，速度最快但容量最小、每比特成本最高。其下依次是缓存（L1、L2、L3）、主存储器（RAM）和辅助存储器（SSD、HDD）。局部性原理确保频繁访问的数据向上层移动。

Registers: fastest, inside CPU, store immediate operands. / 寄存器：最快，位于 CPU 内部，存储立即操作数。
Cache: small, high-speed SRAM between CPU and main memory. / 缓存：位于 CPU 和主存之间的小容量高速 SRAM。
Main memory: DRAM, holds running programs and data. / 主存储器：DRAM，存放正在运行的程序和数据。
Secondary storage: non-volatile, large capacity (HDD, SSD). / 辅助存储器：非易失性，大容量（HDD、SSD）。

Speed ↑, Cost per bit ↑, Capacity ↓ as we move up the hierarchy.

从底层到顶层：速度 ↑、每比特成本 ↑、容量 ↓。

2. Types of Primary Memory | 主存储器的类型

Primary memory is directly accessed by the CPU and consists of RAM and ROM. RAM is volatile, meaning it loses data when power is off. ROM is non-volatile and retains data permanently. Both are semiconductor-based but serve different roles during boot and program execution.

主存储器由 CPU 直接访问，包含 RAM 和 ROM。RAM 是易失性的，断电后数据丢失。ROM 是非易失性的，可永久保存数据。两者均基于半导体，但在启动和程序执行期间扮演不同角色。

Property / 属性	RAM	ROM
Volatility / 易失性	Volatile (data lost on power off) / 易失	Non-volatile (permanent) / 非易失
Read/Write / 读写	Read and write / 可读写	Primarily read-only (some types writable) / 主要只读（某些类型可写）
Typical use / 典型用途	Stores OS, applications, data in use / 存放正在使用的操作系统、应用程序和数据	Firmware, BIOS/UEFI, bootloader / 固件、BIOS/UEFI、引导加载程序

3. SRAM vs DRAM | 静态 RAM 与动态 RAM

RAM is divided into Static RAM (SRAM) and Dynamic RAM (DRAM). SRAM uses flip-flop circuits to store each bit, making it faster and more expensive. DRAM uses capacitors that must be periodically refreshed, offering higher density at lower cost but with slower access times.

RAM 分为静态 RAM（SRAM）和动态 RAM（DRAM）。SRAM 使用触发器电路存储每个比特，速度更快但成本更高。DRAM 使用电容存储数据，必须定期刷新，密度更高、成本更低，但访问速度较慢。

SRAM: 4–6 transistors per cell, no refresh needed, used for cache memory. / 每单元 4-6 个晶体管，无需刷新，用于缓存。
DRAM: 1 transistor + 1 capacitor per cell, needs refreshing every few milliseconds, used for main memory. / 每单元 1 个晶体管 + 1 个电容，需几毫秒刷新一次，用于主存。
Speed comparison: SRAM access time ~ 1-10 ns; DRAM ~ 50-100 ns. / 速度比较：SRAM 访问时间约 1-10 ns；DRAM 约 50-100 ns。
Cost: SRAM is about 4–5 times more expensive per bit than DRAM. / 成本：SRAM 每比特比 DRAM 贵约 4-5 倍。

4. Types of ROM | ROM 的类型

ROM chips store firmware and boot programs. Early ROM was mask-programmed at manufacture. Programmable ROM (PROM) can be written once. Erasable PROM (EPROM) can be erased with UV light. Electrically Erasable PROM (EEPROM) can be erased and rewritten electrically, enabling firmware updates. Flash memory is a modern EEPROM variant.

ROM 芯片存储固件和引导程序。早期的 ROM 在制造时通过掩膜编程。可编程 ROM（PROM）只能写入一次。可擦除 PROM（EPROM）可以用紫外光擦除。电可擦除 PROM（EEPROM）可以电气擦除和重写，支持固件更新。闪存是现代 EEPROM 的变体。

Mask ROM: programmed during fabrication, cannot be changed. / 掩膜 ROM：制造时编程，不能更改。
PROM: user-programmable once using special device. / PROM：用户使用专用设备一次性编程。
EPROM: erasable via UV, then reprogrammed; package has quartz window. / EPROM：紫外线擦除后可重编程；封装有石英窗。
EEPROM: electrically erasable byte by byte; used in BIOS chips. / EEPROM：可按字节电气擦除；用于 BIOS 芯片。
Flash: block-erasable EEPROM, used in SSDs, USB drives, firmware. / 闪存：可按块擦除的 EEPROM，用于 SSD、U盘、固件。

5. Cache Memory | 缓存存储器

Cache is a small, fast memory placed between the CPU and main memory to reduce the average memory access time. It exploits the principles of temporal and spatial locality. Modern CPUs have multiple cache levels: L1 (split into instruction and data caches), L2 (unified, larger), and L3 (shared among cores).

缓存是置于 CPU 与主存之间的小容量快速存储器，用于降低平均内存访问时间。它利用了时间局部性和空间局部性原理。现代 CPU 拥有多级缓存：L1（分为指令和数据缓存）、L2（统一、更大）和 L3（多核共享）。

Hit: data found in cache → fast access. / 命中：在缓存中找到数据 → 快速访问。
Miss: data not in cache → must fetch from slower memory, causing a stall. / 未命中：缓存中无数据 → 必须从较慢的存储器获取，带来停顿。
Hit rate / 命中率: fraction of accesses satisfied by cache. / 缓存满足的访问比例。
Average access time = Hit time + Miss rate × Miss penalty. / 平均访问时间 = 命中时间 + 未命中率 × 未命中代价。

6. Cache Mapping Techniques | 缓存映射技术

A cache mapping function determines where a main memory block can be placed in the cache. The three main techniques are direct mapping, fully associative mapping, and set-associative mapping. Each provides a trade-off between hit rate, complexity, and cost.

缓存映射函数决定了主存块可放置在缓存中的位置。三种主要技术是直接映射、全相联映射和组相联映射。它们在命中率、复杂度和成本之间进行不同的权衡。

Direct mapping: each memory block maps to exactly one cache line (index = block address mod number of lines). Simple, fast, but high conflict misses. / 直接映射：每个内存块映射到唯一缓存行（索引 = 块地址 mod 行数）。简单快速，但冲突未命中率高。
Fully associative: a block can be placed anywhere. Complex, expensive comparison hardware, lowest miss rate. / 全相联：块可放置在任意位置。比较硬件复杂昂贵，未命中率最低。
Set-associative: cache divided into sets; a block maps to a specific set but can occupy any line within that set (n-way set associative). Balance between direct and fully associative. / 组相联：缓存划分为组；块映射到特定组，但可占用组内任意行（n 路组相联）。平衡直接与全相联。

In direct mapping, a physical address is split as:

Tag | Index | Block Offset

直接映射中，物理地址划分如下：

标签 | 索引 | 块内偏移

7. Cache Replacement Policies | 缓存替换策略

When a cache miss occurs and the set is full, a replacement policy decides which existing block to evict. Common policies include Least Recently Used (LRU), First-In First-Out (FIFO), and Random. LRU generally provides the best hit rate but requires extra hardware for tracking usage history.

当缓存未命中且组已满时，替换策略决定驱逐哪个现有块。常见策略包括最近最少使用（LRU）、先进先出（FIFO）和随机替换。LRU 通常提供最佳命中率，但需要额外硬件跟踪使用历史。

LRU: replaces the block unused for the longest time. / 替换最长时间未被使用的块。
FIFO: replaces the block loaded earliest, regardless of usage. / 替换最早加载的块，忽略使用情况。
Random: selects any block uniformly; simple hardware, unpredictable but avoids worst-case patterns. / 随机选择任一块；硬件简单，避免最坏情况模式。
Pseudo-LRU: practical approximation of LRU used in large caches. / 伪 LRU：用于大缓存的 LRU 实用近似。

8. Virtual Memory | 虚拟内存

Virtual memory is a memory management technique that allows the execution of programs larger than physical RAM by using disk space as an extension. Each process has its own virtual address space; the OS and MMU (Memory Management Unit) translate virtual addresses to physical addresses using page tables.

虚拟内存是一种内存管理技术，通过将磁盘空间作为扩展，允许执行比物理 RAM 更大的程序。每个进程拥有自己的虚拟地址空间；操作系统和内存管理单元（MMU）使用页表将虚拟地址翻译为物理地址。

Virtual address space: contiguous to the process, but physically scattered. / 虚拟地址空间：对进程连续，但物理上分散。
Physical memory: divided into fixed-size frames. / 物理内存被划分为固定大小的帧。
Disk backing store: holds pages not currently in memory. / 磁盘后备存储：保存当前不在内存中的页面。
Page fault: when a required page is not in RAM, it must be loaded from disk (high latency). / 缺页：所需页面不在 RAM 中，必须从磁盘加载（高延迟）。

9. Paging and Page Tables | 分页与页表

Paging divides virtual memory into fixed-size pages and physical memory into frames of the same size. A page table maps virtual page numbers to physical frame numbers. Each entry also contains control bits (valid, dirty, referenced). Translation Lookaside Buffer (TLB) is a small cache for page table entries to speed up translation.

分页将虚拟内存划分为固定大小的页面，物理内存划分为相同大小的帧。页表将虚拟页号映射到物理帧号。每个表项还包含控制位（有效位、脏位、引用位）。快表（TLB）是页表项的小型缓存，用于加速地址翻译。

Page size: typically 4 KiB. Small pages reduce internal fragmentation but increase page table size. / 页面大小：通常 4 KiB。小页面减少内部碎片但增大页表。
Multi-level page tables: used to reduce the memory overhead of large page tables (e.g., 2-level, 3-level, 4-level). / 多级页表：用于减少大页表的内存开销（如二级、三级、四级）。
Inverted page table: one entry per physical frame, containing virtual page info; saves space but requires different lookup. / 反向页表：每个物理帧一个表项，包含虚拟页信息；节省空间，但需要不同查找方式。
TLB hit: translation is fast; TLB miss requires page table walk. / TLB 命中：翻译快速；TLB 未命中需要遍历页表。

10. Secondary Storage Technologies | 辅助存储技术

Secondary storage provides non-volatile, long-term data retention. Hard Disk Drives (HDD) use magnetic platters and moving read/write heads, offering high capacity at low cost but slower access due to mechanical latency. Solid State Drives (SSD) use NAND flash memory with no moving parts, delivering much faster random access times but at a higher cost per gigabyte.

辅助存储提供非易失性的长期数据保存。硬盘驱动器（HDD）使用磁性盘片和移动读写头，容量大、成本低，但由于机械延迟访问速度较慢。固态驱动器（SSD）使用无移动部件的 NAND 闪存，随机访问时间快得多，但每 GB 成本更高。

HDD: seek time, rotational latency; sequential access is efficient. / HDD：寻道时间、旋转延迟；顺序访问效率高。
SSD: no seek latency, faster read/write, but write endurance limited. / SSD：无寻道延迟，读写更快，但写入耐久度有限。
Optical storage: CD, DVD, Blu-ray; used for media distribution. / 光存储：CD、DVD、蓝光；用于媒体分发。
Cloud storage: remote servers accessed via network; scalable but dependent on connectivity. / 云存储：通过网络访问的远程服务器；可扩展但依赖网络连接。

11. Addressing Modes | 寻址模式

Addressing modes define how the operand of an instruction is obtained. Common modes in IB/Edexcel syllabus include immediate, direct, indirect, indexed, and register addressing. Each mode affects instruction execution speed and flexibility.

寻址模式定义了如何获取指令的操作数。IB/Edexcel 考纲中常见模式包括立即寻址、直接寻址、间接寻址、变址寻址和寄存器寻址。每种模式影响指令执行速度和灵活性。

Immediate: operand is part of the instruction. LDR R0, #5 → R0 ← 5. / 立即寻址：操作数是指令的一部分。
Direct: instruction contains the memory address of the operand. LDR R0, 200 → R0 ← M[200]. / 直接寻址：指令包含操作数的内存地址。
Indirect: instruction holds the address of a memory location that contains the address of the operand. LDR R0, (200) → R0 ← M[M[200]]. / 间接寻址：指令中给出一个地址，该地址指向操作数的地址。
Indexed: effective address = base + index register. Useful for array access. / 变址寻址：有效地址 = 基址 + 变址寄存器。适用于数组访问。
Register addressing: operand in a register; fastest. / 寄存器寻址：操作数在寄存器中；最快。

12. Memory Management & Exam Tips | 存储器管理与考试技巧

Good memory management by the OS ensures efficient use of RAM, prevents fragmentation, and supports multitasking. Concepts like segmentation, paging, and virtual memory are frequently tested. In exam questions, always relate specifications to the memory hierarchy: why cache is small but fast, how paging allows multiprogramming, and the difference between volatile and non-volatile storage.

操作系统良好的内存管理能确保高效利用 RAM、防止碎片并支持多任务处理。诸如分段、分页和虚拟内存等概念经常被考查。在试题中，始终将规范与存储器层次结构联系起来：为什么缓存小但快，分页如何实现多道程序设计，以及易失性与非易失性存储器之间的区别。

Terminology: clearly define hit, miss, page fault, fragmentation. / 术语：明确定义命中、未命中、缺页、碎片。
Calculations: average memory access time, tag/index/offset bits, page table size. / 计算：平均访问时间、标签/索引/偏移位数、页表大小。
Comparisons: SRAM vs DRAM, HDD vs SSD, direct vs set-associative cache. / 比较：SRAM vs DRAM、HDD vs SSD、直接映射 vs 组相联缓存。
Applications: explain why a sensor node might use EEPROM, or why a gaming PC benefits from large cache. / 应用：解释为什么传感器节点可能使用 EEPROM，或为什么游戏 PC 受益于大缓存。

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Memory in Computer Systems: IB & Edexcel Key Concepts | IB Edexcel 计算机：存储器 考点精讲