A-Level AQA Computer Science: CPU Essentials | A-Level AQA 计算机：CPU 考点精讲

📚 A-Level AQA Computer Science: CPU Essentials | A-Level AQA 计算机：CPU 考点精讲

The Central Processing Unit (CPU) is the brain of the computer. For AQA A-Level Computer Science, understanding its architecture, instruction cycle, and performance factors is essential. This article provides a bilingual revision guide to all the key CPU concepts you need to know.

中央处理器(CPU)是计算机的大脑。对于AQA A-Level计算机科学来说，理解其架构、指令周期和性能因素至关重要。本文提供一份双语复习指南，涵盖你需要掌握的所有CPU关键概念。

1. CPU Architecture Overview | 中央处理器架构概述

The CPU is made up of the control unit (CU), the arithmetic logic unit (ALU), and a set of registers. The CU manages the execution of instructions and coordinates all other components. The ALU performs arithmetic and logical operations. Registers are small, high-speed storage locations inside the CPU that hold data temporarily.

CPU由控制单元(CU)、算术逻辑单元(ALU)和一组寄存器组成。CU管理指令的执行并协调所有其他组件。ALU执行算术和逻辑运算。寄存器是CPU内部的小型高速存储位置，用于临时保存数据。

Data and instructions are transmitted along three types of bus: the address bus, the data bus, and the control bus. The address bus carries memory addresses, the data bus carries the actual data or instruction, and the control bus sends timing and control signals.

数据和指令通过三种总线传输：地址总线、数据总线和控制总线。地址总线携带内存地址，数据总线携带实际的数据或指令，控制总线发送时序和控制信号。

2. Von Neumann Architecture | 冯·诺依曼架构

Most modern computers use the Von Neumann architecture. Its defining feature is that both instructions and data share the same memory and the same buses. This means a single address bus and a single data bus are used to fetch both types of information, which can create a bottleneck known as the ‘Von Neumann bottleneck’.

大多数现代计算机使用冯·诺依曼架构。其决定性特征是指令和数据共享同一内存和同一总线。这意味着使用单地址总线和单数据总线来获取这两种信息，这可能会产生一种被称为”冯·诺依曼瓶颈”的限制。

In this architecture, the CPU fetches each instruction sequentially unless a branch or jump occurs. The need to alternate between loading instructions and loading data on the same bus limits the overall speed of the system.

在此架构中，除非发生分支或跳转，否则CPU依次获取每条指令。需要在同一总线上交替加载指令和加载数据，这限制了系统的整体速度。

3. Harvard Architecture | 哈佛架构

The Harvard architecture separates storage and buses for instructions and data. It has a dedicated address bus and data bus for instructions, and a separate address bus and data bus for data. This allows the CPU to fetch an instruction and read/write data simultaneously, improving performance.

哈佛架构将指令和数据的存储及总线分离开来。它拥有专用的指令地址总线和数据总线，以及单独的数据地址总线和数据总线。这允许CPU同时获取指令和读/写数据，从而提高了性能。

Harvard architecture is often found in embedded systems and digital signal processors (DSPs) where speed and parallelism are critical. However, it requires more complex hardware and is not typically used in general-purpose personal computers due to its cost and inflexibility with memory handling.

哈佛架构常见于需要速度和并行处理的嵌入式系统和数字信号处理器(DSP)中。但由于硬件更复杂且内存处理不够灵活，通常不用于通用个人计算机。

4. Key CPU Registers | CPU内部关键寄存器

Registers are at the heart of CPU operations. The most important registers you need to know for AQA are:

寄存器是CPU操作的核心。AQA考试需要了解的最重要寄存器有：

Program Counter (PC) – holds the memory address of the next instruction to be fetched. After fetching each instruction, it increments to point to the next sequential instruction, unless a branch instruction changes it.
程序计数器(PC) – 保存下一条要获取的指令的内存地址。每获取一条指令后，它会自增以指向下一条顺序指令，除非分支指令更改了它。
Memory Address Register (MAR) – holds the address of the memory location that the CPU will read from or write to. It is connected to the address bus.
内存地址寄存器(MAR) – 保存CPU将要读取或写入的内存位置的地址。它连接到地址总线。
Memory Data Register (MDR) – holds the actual data or instruction that has been read from memory, or the data to be written to memory. It is connected to the data bus.
内存数据寄存器(MDR) – 保存从内存读出的实际数据或指令，或者将要写入内存的数据。它连接到数据总线。
Current Instruction Register (CIR) – holds the current instruction being decoded and executed, split into the opcode and operand.
当前指令寄存器(CIR) – 保存正在被解码和执行的当前指令，分解为操作码和操作数。
Accumulator (ACC) – stores the intermediate results of calculations performed by the ALU.
累加器(ACC) – 存储由ALU执行的计算的中间结果。

5. The Fetch-Decode-Execute Cycle | 获取-解码-执行周期

The CPU repeats the fetch–decode–execute cycle continuously while the computer is running. This three-step process is how every instruction is carried out. Understanding each phase in detail, including the role of registers and buses, is a core requirement of the AQA specification.

当计算机运行时，CPU不断重复获取-解码-执行周期。这个三步过程是每条指令的执行方式。详细理解每个阶段，包括寄存器和总线的作用，是AQA规范的核心要求。

This cycle is also known as the instruction cycle. In some textbooks, an additional ‘store’ phase is added after execute to write results back to memory or a register, but the AQA syllabus focuses on the three fundamental stages.

该周期也称为指令周期。在某些教科书中，执行后会添加一个额外的”存储”阶段，将结果写回内存或寄存器，但AQA大纲重点仍是这三个基本阶段。

6. Fetch Stage in Detail | 获取阶段详解

During the fetch stage, the CPU retrieves the next instruction from main memory. The sequence of events is:

在获取阶段，CPU从主存中检索下一条指令。事件顺序如下：

The PC value is copied into the MAR.
PC的值被复制到MAR中。
The address bus transmits the address stored in the MAR to main memory.
地址总线将MAR中保存的地址传输到主存。
The control unit sends a read signal along the control bus.
控制单元沿控制总线发送读信号。
The instruction stored at that address is placed onto the data bus and loaded into the MDR.
存储在该地址的指令被放到数据总线上，并加载到MDR中。
The MDR content is copied into the CIR.
MDR的内容被复制到CIR中。
The PC is incremented by 1 (or by the length of the instruction) to point to the next instruction.
PC自增1(或指令长度)以指向下一条指令。

All these actions happen in a single fetch phase. The increment of the PC ensures that, normally, the next sequential instruction will be fetched next.

所有这些操作都发生在单个获取阶段内。PC的自增确保了下一次一般会获取下一条顺序指令。

7. Decode and Execute Stages | 解码与执行阶段

Once the instruction is in the CIR, the decode stage begins. The control unit splits the instruction into two parts: the opcode (the operation to perform) and the operand (the data or address on which to operate). The opcode is decoded so that the CU knows exactly what ALU operation or memory transfer is required.

一旦指令进入CIR，解码阶段就开始了。控制单元将指令分为两部分：操作码(要执行的操作)和操作数(要操作的数据或地址)。解码操作码后，CU就准确地知道需要什么ALU操作或内存传输。

In the execute stage, the CPU carries out the decoded instruction. This may involve:

在执行阶段，CPU执行解码后的指令。这可能涉及：

Loading data from memory into a register,
从内存加载数据到寄存器，
Performing an arithmetic or logical operation in the ALU,
在ALU中执行算术或逻辑运算，
Storing the result from the ACC back to memory,
将ACC的结果存回内存，
Or altering the PC if a jump/branch instruction is executed.
或者如果执行跳转/分支指令，则更改PC。

Once the execute step completes, the cycle begins again with the next fetch unless a halt instruction stops the processor.

执行步骤完成后，周期重新开始下一次获取，除非遇到停止指令使处理器停止。

8. CPU Performance: Clock Speed | CPU性能：时钟速度

Clock speed, measured in Hertz (Hz), determines how many fetch–decode–execute cycles the CPU can perform per second. A CPU with a clock speed of 3.5 GHz carries out 3.5 x 10⁹ cycles every second. A higher clock speed generally means faster processing, but physical limits (heat generation and power consumption) place a ceiling on how fast a processor can run.

时钟速度以赫兹(Hz)为单位，决定了CPU每秒能执行多少个获取-解码-执行周期。时钟速度为3.5 GHz的CPU每秒执行3.5×10⁹个周期。更高的时钟速度通常意味着处理更快，但物理限制(发热和功耗)对处理器运行速度设置了上限。

In the AQA specification, you need to explain that increasing the clock rate reduces the time per cycle and thus the time to complete a task, provided that other components (such as memory) can keep up.

在AQA规范中，你需要解释增加时钟频率会减少每个周期的时间，从而减少完成任务的时间，前提是其他组件(如内存)能跟上。

9. Cache Memory and Number of Cores | 缓存与核心数

Cache is a small amount of very fast memory located inside or very close to the CPU. It stores frequently used instructions and data to reduce the average time taken to access main memory (RAM). The larger the cache, the more likely the CPU finds what it needs without going to slower memory, thus improving performance.

缓存是位于CPU内部或非常靠近CPU的小容量的极快内存。它存储频繁使用的指令和数据，以减少访问主存(RAM)的平均时间。缓存越大，CPU就越有可能在不去访问较慢内存的情况下找到所需内容，从而提高性能。

Modern CPUs often have multiple levels of cache (L1, L2, L3), with L1 being the fastest and smallest and L3 being larger but slower. Key specification point: ‘Explain the effect of clock speed, number of cores, and cache size on performance.’

现代CPU通常有多级缓存(L1, L2, L3)，其中L1最快、最小，L3更大但较慢。规范关键点：”解释时钟速度、核心数和缓存大小对性能的影响。”

A CPU core is an independent processing unit that can execute instructions. A multi-core processor can process multiple instructions simultaneously (parallel processing). For example, a quad-core CPU can theoretically handle four times as many instructions as a single core, but the actual speedup depends on whether the software is designed to use all cores effectively.

CPU核心是能够执行指令的独立处理单元。多核处理器可以同时处理多条指令(并行处理)。例如，四核CPU理论上可以处理单个核心四倍的指令，但实际加速效果取决于软件是否设计为有效使用所有核心。

10. Pipelining and Instruction Sets | 流水线与指令集

Pipelining is a technique that allows the CPU to begin fetching the next instruction before the current one has finished executing. The fetch, decode, and execute stages are overlapped, so while one instruction is being decoded, the next one is being fetched simultaneously. This increases throughput – more instructions are processed per unit time – although each individual instruction still takes the same number of cycles.

流水线是一种允许CPU在当前指令执行完成之前就开始获取下一条指令的技术。获取、解码和执行阶段重叠，因此在解码一条指令的同时可以获取下一条指令。这提高了吞吐量(单位时间处理更多指令)，虽然每条单独指令仍然需要相同的周期数。

AQA also expects understanding of the concept of a reduced instruction set computer (RISC) and complex instruction set computer (CISC). RISC processors use a small, simple set of instructions that each take one clock cycle, enabling efficient pipelining. CISC processors have a larger, more complex instruction set, some of which may take many cycles, making pipelining harder but reducing the number of instructions per program.

AQA还要求理解精简指令集计算机(RISC)和复杂指令集计算机(CISC)的概念。RISC处理器使用一组小巧、简单的指令，每条指令占用一个时钟周期，从而实现高效流水线。CISC处理器拥有更大、更复杂的指令集，其中一些指令可能需要多个周期，令流水线更困难，但减少了每个程序的指令数量。

11. Review of AQA Key Terms | AQA关键术语复习

To succeed in the AQA A-Level examinations, you must be able to define and describe:

要在AQA A-Level考试中取得成功，你必须能够定义和描述以下内容：

Program Counter, MAR, MDR, CIR, ACC and explain their roles in the FDE cycle.
程序计数器、MAR、MDR、CIR、ACC，并解释它们在FDE周期中的作用。
The three bus types: address, data and control, and what each carries.
三种总线类型：地址、数据和控制，以及各自传输的内容。
The difference between Von Neumann and Harvard architectures, and why each is used.
冯·诺依曼架构与哈佛架构的区别，以及各自的使用场景。
How clock speed, number of cores, and cache size affect CPU performance.
时钟速度、核心数和缓存大小如何影响CPU性能。
What pipelining is and how RISC and CISC processors differ.
流水线的含义，以及RISC和CISC处理器的差异。

Use precise technical vocabulary and provide clear, sequenced explanations in both short-answer and extended-response questions.

在简答题和扩展题中使用精确的技术词汇，并提供清晰、有序的解释。

Published by TutorHao | Computer Science Revision Series | aleveler.com

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A-Level AQA Computer Science: CPU Essentials | A-Level AQA 计算机：CPU 考点精讲