📚 IB AQA Computer Science: CPU Key Points | IB AQA 计算机：CPU 考点精讲
The Central Processing Unit (CPU) is the brain of every computer system, executing instructions and processing data at incredible speed. In the IB AQA Computer Science specification, understanding the internal architecture, the fetch-decode-execute cycle, and factors affecting CPU performance is fundamental. This article breaks down every essential concept, from registers and buses to pipelining and multi-core processing, helping you tackle exam questions with confidence.
中央处理器（CPU）是每个计算机系统的大脑，它以惊人的速度执行指令并处理数据。在 IB AQA 计算机科学课程中，理解内部架构、取指-解码-执行周期以及影响 CPU 性能的因素是基础中的基础。本文分解了每一个关键概念，从寄存器和总线到流水线和多核处理，帮助你自信地应对考试题目。
1. The Von Neumann Architecture | 冯·诺依曼架构
The vast majority of modern CPUs are based on the von Neumann architecture, which stores both program instructions and data in the same memory unit. This unified memory concept introduces the stored-program idea, where a computer can be reprogrammed simply by altering the contents of its memory. The key components connected by buses are the processor, memory, input, and output devices, all coordinated by a control unit.
绝大多数现代 CPU 都基于冯·诺依曼架构，该架构将程序指令和数据存储在同一内存单元中。这种统一内存的概念引入了存储程序的思想，即仅通过改变内存内容就能对计算机重新编程。通过总线连接的关键部件是处理器、存储器、输入和输出设备，所有这些都由控制单元协调。
A fundamental limitation is the von Neumann bottleneck, caused by the shared bus for fetching instructions and data. Since data and instructions travel along the same pathway, the CPU often has to wait for memory accesses, limiting overall speed. Examiners often ask you to explain this bottleneck and how Harvard architecture differs by using separate memories for instructions and data.
一个基本局限是冯·诺依曼瓶颈，它由取指令和取数据共享同一总线导致。由于数据和指令沿着同一条路径传输，CPU 常常不得不等待内存访问，从而限制了整体速度。考官常会要求你解释这一瓶颈，以及哈佛架构如何通过使用独立的指令存储器和数据存储器来实现区别。
2. CPU Internal Components | CPU 内部部件
Inside the CPU, several crucial units work together. The Arithmetic Logic Unit (ALU) performs all arithmetic operations (addition, subtraction, multiplication, division) and logical operations (AND, OR, NOT, XOR) on integer data. Floating-point operations may be handled by a separate FPU. The Control Unit (CU) decodes instructions and sends control signals to coordinate the movement of data between registers, ALU, and memory.
CPU 内部有几个关键单元协同工作。算术逻辑单元（ALU）对整数数据执行所有算术运算（加、减、乘、除）和逻辑运算（与、或、非、异或）。浮点运算可能由单独的浮点单元（FPU）处理。控制单元（CU）对指令进行解码，并发出控制信号，以协调寄存器、ALU 和存储器之间的数据移动。
A dedicated clock drives the timing of all operations. The clock generates regular pulses that synchronise changes in state across the processor. The rate of these pulses – clock speed – is measured in Hertz (Hz), with modern CPUs operating in gigahertz. Each tick of the clock allows one or more micro-operations to progress, so higher clock speeds generally mean faster execution, but also higher power consumption and heat.
专用时钟驱动所有操作的时序。时钟产生规则的脉冲，同步处理器中各处状态的变化。这些脉冲的速率——时钟速度——以赫兹（Hz）衡量，现代 CPU 的工作频率达到千兆赫兹。每个时钟滴答允许一个或多个微操作推进，因此更高的时钟速度通常意味着更快的执行，但也带来更高的功耗和发热。
The immediate access store (IAS) or register file is a small set of extremely fast memory locations directly inside the CPU. Registers hold the data, addresses, and status flags currently needed by the processor. The size of registers (e.g., 32-bit or 64-bit) determines how much data the CPU can handle in one operation and the maximum addressable memory.
立即存取存储器（IAS）或寄存器文件是直接位于 CPU 内部的一小组极快速的内存位置。寄存器保存当前处理器所需的数据、地址和状态标志。寄存器的大小（如 32 位或 64 位）决定了 CPU 在一次操作中能处理多少数据以及可寻址的最大内存。
3. Essential Registers | 基本寄存器
You must know the role of each key register. The Program Counter (PC) holds the address of the next instruction to be fetched. After a fetch, it increments to point to the following instruction unless a jump or branch occurs. The Current Instruction Register (CIR) holds the instruction currently being decoded and executed. Together with the CU, the CIR splits the instruction into opcode and operand.
你必须了解每个关键寄存器的作用。程序计数器（PC）保存下一条待取指令的地址。取指之后，它会递增以指向下一条指令，除非发生跳转或分支。当前指令寄存器（CIR）保存当前正在被解码和执行的指令。与控制单元一起，CIR 将指令分割为操作码和操作数。
The Memory Address Register (MAR) stores the address from which data or an instruction is to be read, or to which data is to be written. It is directly connected to the address bus. The Memory Data Register (MDR) – sometimes called Memory Buffer Register – holds the actual data or instruction that has been fetched from memory or is waiting to be written back. After a memory read, the word stored at the address in MAR is placed into MDR.
内存地址寄存器（MAR）存储即将读取数据或指令的地址，或者将要写入数据的地址。它直接连接到地址总线。内存数据寄存器（MDR）——有时称为内存缓冲寄存器——保存已从内存中取回或等待写回的实际数据或指令。一次内存读取后，存储在 MAR 所指示地址的字被放入 MDR。
The Accumulator (ACC) is a general-purpose register that temporarily stores results of ALU operations. Many arithmetic instructions implicitly use the accumulator as both source and destination. Additionally, the Status Register (SR) or flag register contains individual bits indicating conditions like zero, carry, overflow, and negative results after an ALU operation, enabling conditional branching.
累加器（ACC）是一个通用寄存器，临时存储 ALU 运算的结果。许多算术指令隐含地使用累加器作为源操作数和目的操作数。此外，状态寄存器（SR）或标志寄存器包含若干独立的位，用于指示 ALU 运算后的条件，如零、进位、溢出和负数结果，从而实现条件分支。
4. Buses: Address, Data, and Control | 总线：地址总线、数据总线和控制总线
Three distinct buses form the communication backbone linking the CPU to memory and I/O controllers. The address bus is unidirectional (from CPU to memory) and carries the memory location address. Its width determines the maximum addressable memory – a 32-bit address bus can address 2³² different locations, i.e., 4 GB of memory.
三条不同的总线构成了连接 CPU 与存储器和 I/O 控制器的通信主干。地址总线是单向的（从 CPU 到存储器），传输内存单元地址。其宽度决定了最大可寻址内存——32 位地址总线可以寻址 2³² 个不同位置，即 4 GB 内存。
The data bus is bidirectional and transfers the actual instruction or data between the CPU and memory or I/O ports. Its width often matches the word size of the processor (e.g., 64 bits). A wider data bus improves performance by fetching more data per memory access. The control bus carries control signals such as read, write, clock, and interrupt request lines. These signals coordinate the operation of all connected components.
数据总线是双向的，传输 CPU 与存储器或 I/O 端口之间的实际指令或数据。其宽度通常与处理器的字长匹配（例如 64 位）。更宽的数据总线通过每次内存访问获取更多数据来提高性能。控制总线传输控制信号，如读、写、时钟和中断请求线。这些信号协调所有连接部件的操作。
Exam tip: clearly state the direction and typical width for each bus. Remember that the memory read operation involves placing the address on the address bus, activating the read line on the control bus, and then the data being placed on the data bus by memory.
考试提示：清楚说明每条总线的方向和典型宽度。记住，内存读操作包括在地址总线上放置地址，激活控制总线上的读线，然后由存储器把数据放到数据总线上。
5. The Fetch-Decode-Execute Cycle | 取指-解码-执行周期
The fetch-decode-execute cycle, also called the instruction cycle, is the process by which a CPU processes each program instruction. This cycle repeats billions of times per second and can be broken into specific register-transfer steps. Let’s walk through each stage for a typical machine instruction.
取指-解码-执行周期，也称为指令周期，是 CPU 处理每条程序指令的过程。该周期每秒重复数十亿次，可分解为特定的寄存器传输步骤。我们来逐步介绍一条典型机器指令的各个阶段。
Fetch stage: The PC address is copied to MAR; the control unit sends a read signal on the control bus; the memory reads the data at the address on the address bus and places it on the data bus; this data is loaded into MDR and then copied to CIR. Finally, the PC is incremented by 1 (or by the instruction length).
取指阶段：PC 地址被复制到 MAR；控制单元在控制总线上发出读信号；存储器读取地址总线上地址处的数据，并将其放到数据总线上；该数据被加载到 MDR，然后复制到 CIR。最后，PC 增加 1（或增加指令长度）。
Decode stage: The control unit interprets the instruction in the CIR, splitting it into opcode and operand(s). The CU then configures the necessary data paths and ALU operation. If the instruction requires a memory operand, the address part of the instruction may be loaded into MAR for a subsequent memory access.
解码阶段：控制单元解释 CIR 中的指令，将其分割为操作码和操作数。然后 CU 配置必要的数据路径和 ALU 操作。如果指令需要内存操作数，指令的地址部分可能被加载到 MAR 以便后续进行内存访问。
Execute stage: The ALU performs the required operation, which could be arithmetic, logic, memory load/store, or a control transfer (jump). For a load instruction, memory is read and the data placed into the accumulator. For a jump, the PC is updated with the target address. After execute, any results are written back to a register or memory, and the cycle repeats.
执行阶段：ALU 执行所需操作，可能是算术、逻辑、内存加载/存储，或控制转移（跳转）。对于加载指令，读取内存并将数据放入累加器。对于跳转指令，用目标地址更新 PC。执行后，任何结果被写回寄存器或内存，然后周期重复。
6. Factors Affecting CPU Performance | 影响 CPU 性能的因素
Three primary factors are assessed in exam questions: clock speed, number of cores, and cache memory. Clock speed, measured in GHz, indicates the number of fetch-decode-execute cycles that can be completed per second. A 3.5 GHz processor can theoretically carry out 3.5 billion cycles per second. However, raw clock speed comparison is only meaningful within the same architecture; different microarchitectures achieve different amounts of work per cycle (Instructions Per Cycle, IPC).
考题通常评估三个主要因素：时钟速度、核心数量和缓存内存。时钟速度以 GHz 为单位，表示每秒可以完成的取指-解码-执行周期的数量。一个 3.5 GHz 的处理器理论上可以每秒执行 35 亿个周期。然而，原始时钟速度的比较仅在相同架构内才有意义；不同的微架构每个周期完成的工作量不同（每周期指令数，IPC）。
Modern CPUs contain multiple cores, which are independent processing units on the same chip. A quad-core processor can genuinely execute four different processes or threads simultaneously, improving multitasking and throughput for parallel workloads. However, a program must be written to take advantage of multiple cores (parallelised), otherwise a single-threaded application runs no faster on multiple cores than on one core.
现代 CPU 包含多个核心，它们是在同一芯片上的独立处理单元。四核处理器可以真正同时执行四个不同的进程或线程，从而改善多任务处理和平行工作负载的吞吐量。然而，程序必须编写为能够利用多核心（并行化），否则单线程应用程序在多个核心上运行的速度并不比在单核心上更快。
Cache is ultra-fast memory located on the CPU chip (Level 1, Level 2, sometimes Level 3) that stores recently and frequently used data and instructions. When the CPU fetches a memory location, it first checks the cache. A cache hit provides the data in a few clock cycles, whereas a cache miss requires a slower access to main RAM, causing pipeline stalls. Larger caches generally improve hit rates, but they are more expensive and consume more power. L1 is smallest and fastest; L2 is larger but slower; L3 is shared among cores.
缓存是位于 CPU 芯片上的超快速内存（一级、二级，有时三级），存储最近和频繁使用的数据和指令。当 CPU 获取一个内存位置时，它首先检查缓存。缓存命中可在几个时钟周期内提供数据，而缓存缺失则需要较慢的主 RAM 访问，导致流水线停顿。较大的缓存通常可以提高命中率，但更昂贵且功耗更大。一级缓存最小且最快；二级更大但更慢；三级在核心间共享。
7. Instruction Pipelining | 指令流水线
Pipelining is a technique that overlaps the execution of multiple instructions to improve throughput. Rather than completing one instruction’s fetch-decode-execute cycle entirely before starting the next, the CPU works on different stages of several instructions simultaneously. A classic five-stage pipeline includes: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). At the same time that one instruction is being decoded, the next is being fetched, and so on.
流水线是一种重叠执行多条指令以提高吞吐量的技术。CPU 不是完全完成一条指令的取指-解码-执行周期后再开始下一条，而是同时处理多条指令的不同阶段。经典的 5 级流水线包括：取指（IF）、解码（ID）、执行（EX）、内存访问（MEM）和写回（WB）。在一条指令被解码的同时，下一条指令正在被取指，依此类推。
However, pipelines face hazards that reduce efficiency. Data hazards occur when an instruction depends on the result of a previous instruction still in the pipeline; techniques like forwarding can resolve this. Control hazards arise from branch instructions – the CPU does not know which instruction to fetch next until the branch is resolved. Branch prediction is used to guess the outcome and avoid pipeline bubbles. Structural hazards happen when hardware resources are insufficient to support the simultaneous stages.
然而，流水线面临着降低效率的冒险。数据冒险发生在一条指令依赖于仍在流水线中的前一条指令的结果时；前推等技术可以解决这个问题。控制冒险产生于分支指令——在分支解决之前，CPU 不知道下一条该取哪条指令。分支预测用于猜测结果以避免流水线气泡。结构冒险发生在硬件资源不足以支持同时进行的各阶段时。
In the exam, you might be asked to calculate speedup in an ideal pipeline or explain why a four-stage pipeline does not quadruple performance due to hazards and latch overhead. Remember that pipelining reduces the execution time per instruction but increases instruction throughput, not single-instruction latency.
在考试中，你可能需要计算理想流水线的加速比，或解释为何四级流水线由于冒险和锁存器开销并不能将性能提升至四倍。记住，流水线降低了每条指令的执行时间，但增加的是指令吞吐量，而非单条指令的延迟。
8. The Harvard Architecture | 哈佛架构
The Harvard architecture uses physically separate memory storage and signal pathways for instructions and data. This means there is a dedicated instruction memory with its own bus, and a separate data memory with its own bus. The primary advantage is that the CPU can fetch both an instruction and data operand simultaneously, greatly reducing the von Neumann bottleneck. Harvard architecture is commonly found in microcontrollers and special-purpose digital signal processors (DSPs).
哈佛架构使用物理上独立的存储器存储和信号通路分别用于指令和数据。这意味着有一个专用的指令存储器及其自己的总线，以及一个独立的数据存储器及其自己的总线。其主要优势是 CPU 可以同时获取指令和数据操作数，大大减少了冯·诺依曼瓶颈。哈佛架构常见于微控制器和专用数字信号处理器（DSP）。
A modified Harvard architecture is used in many modern general-purpose processors: separate L1 caches for instructions and data (I-cache and D-cache), but a unified main memory and shared bus at lower cache levels. This hybrid approach offers the performance benefit of simultaneous instruction/data access from the fastest memory while keeping the flexibility of a unified main memory. IB AQA expects you to compare the pure Harvard and pure von Neumann models and identify the modified variant.
许多现代通用处理器采用改进的哈佛架构：为指令和数据分别设置独立的一级缓存（I-cache 和 D-cache），但在较低缓存级别使用统一主内存及共享总线。这种混合方式在从最快内存同时访问指令和数据时提供性能优势，同时保持统一主存的灵活性。IB AQA 希望你比较纯哈佛与纯冯·诺依曼模型，并识别改进变体。
9. Fetch and Decode Detailed Example | 取指与解码实例详解
Consider a simple 8-bit processor where an instruction consists of a 4-bit opcode and a 4-bit operand. The instruction 0001 1010 might mean ‘Load the value stored at address 1010 into the accumulator’. During fetch, the PC supplies address 0000 0100 (program location). The memory returns 0001 1010 into the MDR, then CIR. The CU decodes 0001 as LOAD and sets MAR to 0000 1010 (the operand). A second memory read obtains the actual data from address 1010 and loads it into ACC.
考虑一个简单的 8 位处理器，其指令由一个 4 位操作码和一个 4 位操作数组成。指令 0001 1010 可能表示“将地址 1010 处的值加载到累加器”。在取指期间，PC 提供地址 0000 0100（程序位置）。内存将 0001 1010 返回至 MDR，然后送入 CIR。CU 将 0001 解码为 LOAD，并将 MAR 设置为 0000 1010（操作数）。第二次内存读取从地址 1010 获得实际数据并将其加载到 ACC。
If the opcode 0010 means ADD, the instruction 0010 1011 would add the contents of address 1011 to the accumulator. The execute stage would involve fetching the value from memory address 1011 to a temporary register, feeding both ACC and the temporary register into the ALU, and storing the sum back into ACC. The PC is incremented to the next instruction address after each fetch unless a JUMP instruction modifies it.
如果操作码 0010 表示 ADD，则指令 0010 1011 会将地址 1011 的内容与累加器相加。执行阶段将涉及从内存地址 1011 获取值到临时寄存器，将 ACC 和临时寄存器的值送入 ALU，并将和存回 ACC。每次取指后 PC 递增到下一条指令地址，除非 JUMP 指令修改了它。
This step-by-step register-transfer language (RTL) description is typical in exam questions. Practice describing the sequence for different addressing modes (immediate, direct, indirect) to demonstrate your understanding of the data paths inside the processor.
这种逐步的寄存器传输语言（RTL）描述是考题中常见的。练习描述不同寻址模式（立即、直接、间接）下的序列，以展示你对处理器内部数据路径的理解。
10. Cores and Multi-Core Processing | 核心与多核处理
Adding more cores is an effective way to improve performance without increasing clock speed, which is power-hungry and generates excessive heat. Each core contains its own ALU, CU, and registers (typically separate L1 caches), but they share the same main memory and possibly a last-level cache. The operating system schedules programs across available cores, enabling true simultaneous execution.
添加更多核心是一种在不提高时钟速度（这种速度功耗大且产生过多热量）的情况下提高性能的有效方法。每个核心拥有自己的 ALU、CU 和寄存器（通常是独立的一级缓存），但它们共享相同的主内存，可能还共享末级缓存。操作系统在可用核心之间调度程序，实现真正的同步执行。
Amdahl’s law reminds us that the speedup from parallelization is limited by the sequential fraction of a program. If 20% of a program must remain serial, the maximum speedup with an infinite number of cores is 1/0.2 = 5 times. Therefore, simply adding more cores does not linearly increase performance for all tasks, and developers must write concurrent code using threads to exploit multicore architectures.
阿姆达尔定律提醒我们，通过并行化获得的加速比受程序串行部分的限制。如果程序 20% 的部分必须保持串行，那么即使使用无限多个核心，最大加速比也只有 1/0.2 = 5 倍。因此，简单地增加核心数量并不会为所有任务线性提升性能，开发人员必须使用线程编写并发代码以利用多核架构。
Hyper-threading (Intel) or simultaneous multithreading allows a single physical core to appear as two logical cores by duplicating certain hardware units (like register files and PC) while sharing ALUs. This can increase utilisation by switching to another thread when a stall occurs, but it is not a replacement for true multi-core processing. You should distinguish between physical cores and logical threads in performance analysis.
超线程（Intel）或同步多线程技术通过复制某些硬件单元（如寄存器文件和 PC）并共享 ALU，使一个物理核心表现为两个逻辑核心。当发生停顿时切换到另一个线程可提高利用率，但这不能替代真正的多核处理。在性能分析中，你应当区分物理核心和逻辑线程。
11. Cache Memory in Depth | 缓存内存深入
The cache hierarchy exploits the principle of locality: temporal locality (recently accessed data is likely to be accessed again soon) and spatial locality (data near recently accessed locations is likely to be accessed). Caches are organised into lines or blocks. When a cache miss occurs, an entire block of contiguous memory is fetched, not just the requested word. This prefetching leverages spatial locality to improve future hit rates.
缓存层次利用了局部性原理：时间局部性（最近访问的数据很可能很快再次被访问）和空间局部性（最近访问位置附近的数据很可能被访问）。缓存被组织成行或块。当发生缓存缺失时，将获取整个连续内存块，而不仅仅是请求的字。这种预取利用了空间局部性来提高未来的命中率。
Mapping schemes determine how main memory blocks are placed into cache lines. Direct-mapped cache assigns each memory block to exactly one cache line, causing potential conflict misses. Fully-associative cache allows any block to be stored in any line, requiring extensive hardware searching. Set-associative cache is a compromise, grouping lines into sets. IB AQA may ask you to recognize these and their impact on miss rates.
映射方案决定主存块如何放入缓存行。直接映射缓存将每个内存块精确分配到唯一一个缓存行，导致可能的冲突缺失。全相联缓存允许任何块存储在任何行，但需要大量硬件搜索。组相联缓存是一种折中方案，将行分组为组。IB AQA 可能要求你识别这些方案及其对缺失率的影响。
When the CPU writes data to a cached location, cache coherence and consistency policies come into play. Write-through writes to both cache and main memory simultaneously, ensuring consistency but is slower. Write-back writes only to cache initially, marking the line as dirty; the line is written back to memory when evicted, which is faster but more complex. In multi-core systems, snooping protocols ensure all caches see a consistent view of memory.
当 CPU 向缓存中的位置写入数据时，缓存一致性和一致性策略发挥作用。写通过同时写入缓存和主内存，确保一致性但速度较慢。写回最初只写入缓存，将行标记为脏；当行被驱逐时再写回内存，速度更快但更复杂。在多核系统中，嗅探协议确保所有缓存看到一致的内存视图。
12. Summary and Exam Technique | 总结与答题技巧
A solid understanding of CPU architecture comes from being able to trace the flow of data in the fetch-decode-execute cycle, identify the function of every register, and explain how architectural choices affect performance. When confronted with a diagram, practice naming each component and stating its role. For extended-response questions, use precise technical vocabulary: ‘opcode’, ‘control bus’, ‘memory address register’, ‘pipeline stall’, ‘spatial locality’.
扎实理解 CPU 架构来自于能够追踪取指-解码-执行周期中的数据流动，识别每个寄存器的功能，并解释架构选择如何影响性能。当面对示意图时，练习命名每个部件并说明其作用。对于扩展答题，使用精确的技术词汇：“操作码”、“控制总线”、“内存地址寄存器”、“流水线停顿”、“空间局部性”。
Remember to link the three performance factors to real-world scenarios: a database server benefits from multiple cores and large cache, while a simple embedded controller may work perfectly with a single-core Harvard architecture processor running at moderate clock speed. If asked to suggest improvements, always justify with reference to the limitations of the current system, whether it be a narrow data bus causing bottlenecks or insufficient cache leading to high miss rates.
记住将三个性能因素与实际场景联系起来：数据库服务器从多核和大缓存中受益，而简单的嵌入式控制器可能完美运行在具有中等时钟速度的单核哈佛架构处理器上。如果要求提出改进建议，务必引用当前系统的局限性来论证，无论是窄数据总线导致瓶颈，还是缓存不足导致高缺失率。
Finally, be aware of current trends mentioned in the specification, such as the move towards heterogeneous multi-core systems (combining high-performance and energy-efficient cores) and the increasing importance of parallel processing in modern computing. This context can enrich your longer answers and demonstrate a wider appreciation of the subject.
最后，注意规范中提及的当前趋势，如向异构多核系统（结合高性能与高能效核心）的发展，以及并行处理在现代计算中日益增长的重要性。这种背景知识可丰富你的长答案，展现对该学科更广泛的认知。
Published by TutorHao | Computer Science Revision Series | aleveler.com
更多咨询请联系16621398022（同微信）
屏轩国际教育cambridge primary/secondary checkpoint, cat4, ukiset,ukcat,igcse,alevel,PAT,STEP,MAT, ibdp,ap,ssat,sat,sat2课程辅导，国外大学本科硕士研究生博士课程论文辅导