📚 IB & CCEA Computer Science: CPU Essentials | IB 与 CCEA 计算机 CPU 考点精讲
The Central Processing Unit (CPU) is the brain of the computer, responsible for executing instructions and processing data. In IB and CCEA Computer Science, you must understand its architecture, how it operates, and the factors that influence its performance. This article covers all key concepts in a clear, bilingual format to help you master CPU-related exam questions.
中央处理器 (CPU) 是计算机的大脑，负责执行指令和处理数据。在 IB 和 CCEA 计算机科学中，你必须理解其架构、运作方式以及影响性能的因素。本文以清晰的双语形式涵盖所有核心概念，助你彻底掌握 CPU 相关考点。
1. What is a CPU? | 什么是 CPU？
The CPU is the primary component of a computer that performs most of the processing. It executes program instructions by carrying out basic arithmetic, logical, control, and input/output operations. In both IB and CCEA syllabuses, the CPU is treated as a complex system of interacting sub-units.
CPU 是计算机中执行大部分处理工作的核心部件。它通过基本的算术、逻辑、控制和输入/输出操作来执行程序指令。在 IB 和 CCEA 课程大纲中，CPU 被视为一个由多个交互子单元组成的复杂系统。
2. CPU Components: ALU, CU, and Registers | CPU 组成：算术逻辑单元、控制单元与寄存器
The Arithmetic Logic Unit (ALU) performs arithmetic (addition, subtraction, etc.) and logical (AND, OR, NOT) operations. The Control Unit (CU) directs the operation of the processor by fetching instructions, decoding them, and controlling the flow of data between the CPU and other components. Registers are small, high-speed storage locations inside the CPU, such as the Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), Current Instruction Register (CIR), and Accumulator (ACC).
算术逻辑单元 (ALU) 执行算术运算（加、减等）和逻辑运算（与、或、非）。控制单元 (CU) 负责取指令、译码，并控制 CPU 与其他部件之间的数据流，从而指挥处理器的运行。寄存器是 CPU 内部的小容量高速存储单元，例如程序计数器 (PC)、存储器地址寄存器 (MAR)、存储器数据寄存器 (MDR)、当前指令寄存器 (CIR) 和累加器 (ACC)。
3. System Buses: Data, Address, and Control | 系统总线：数据总线、地址总线与控制总线
The CPU communicates with memory and I/O devices via three buses. The data bus carries the actual data being transferred; its width (e.g., 32-bit, 64-bit) determines how much data can move at once. The address bus carries memory addresses from the CPU to memory, and its width determines the maximum addressable memory space (e.g., 32 lines → 2³² addresses). The control bus transmits control signals such as read, write, and clock signals to coordinate activities.
CPU 通过三条总线与内存和 I/O 设备通信。数据总线传输实际数据；其宽度（如 32 位、64 位）决定了一次可传输的数据量。地址总线将内存地址从 CPU 传送到存储器，其宽度决定了可寻址的最大内存空间（如 32 条线 → 2³² 个地址）。控制总线传送读、写和时钟等控制信号，以协调各部件的工作。
4. The Fetch-Decode-Execute Cycle | 取指 – 译码 – 执行周期
The fundamental operation of a CPU is the fetch‑decode‑execute cycle. First, the address in the PC is transferred to the MAR, and the CU fetches the instruction from memory into the MDR, then copies it to the CIR. The PC is incremented. Next, the CU decodes the instruction into opcode and operands. Finally, the execute stage carries out the instruction, which may involve the ALU, registers, or memory. This cycle repeats billions of times per second.
CPU 的基本操作是取指 – 译码 – 执行周期。首先，PC 中的地址被传送到 MAR，CU 从内存取出指令到 MDR，然后复制到 CIR；PC 加 1。接着，CU 将指令译码为操作码和操作数。最后，执行阶段完成该指令，可能涉及 ALU、寄存器或存储器。这个周期每秒钟重复数十亿次。
5. Factors Affecting CPU Performance: Clock Speed | 影响 CPU 性能的因素：时钟速度
Clock speed, measured in gigahertz (GHz), is the number of cycles the CPU can execute per second. A higher clock speed means more fetch‑decode‑execute cycles per second, leading to faster processing. However, speed is limited by heat generation and the physical properties of silicon. In exams, you should link clock speed directly to the number of instructions per second.
时钟速度以吉赫 (GHz) 为单位，是 CPU 每秒可执行的周期数。时钟频率越高，每秒取指 – 译码 – 执行周期越多，处理速度越快。但速度受发热和硅物理特性限制。考试中，应将时钟速度与每秒执行的指令数直接关联。
6. Factors Affecting CPU Performance: Cores and Cache | 影响 CPU 性能的因素：内核与缓存
A core is an independent processing unit that can execute its own fetch‑decode‑execute cycle. Multiple cores allow true parallel processing, efficiently handling multi‑threaded applications. Cache memory is a small, high‑speed memory inside the CPU that stores frequently accessed data and instructions, reducing the need to fetch from slower main memory. Levels of cache (L1, L2, L3) differ in size and speed. More cores and larger caches generally improve performance, but not linearly.
内核是一个独立处理单元，可执行自己的取指 – 译码 – 执行周期。多个内核实现真正的并行处理，高效处理多线程应用。高速缓存是 CPU 内部的小容量高速内存，存储频繁使用的数据和指令，减少从较慢主存取数据的需求。缓存分为 L1、L2、L3 级，大小和速度不同。更多的内核和更大的缓存通常能提升性能，但并不呈线性增长。
7. Instruction Set Architecture (ISA) | 指令集架构 (ISA)
The ISA defines the set of instructions a CPU can execute, including opcodes, data types, registers, addressing modes, and memory architecture. It is the interface between hardware and software. Both IB and CCEA require you to know how an ISA influences programming and performance, and to differentiate between CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer).
指令集架构定义了 CPU 可执行的指令集合，包括操作码、数据类型、寄存器、寻址模式和存储架构等。它是软硬件之间的接口。IB 和 CCEA 都要求了解 ISA 如何影响编程和性能，并区分 CISC（复杂指令集计算机）和 RISC（精简指令集计算机）。
8. Addressing Modes | 寻址模式
Addressing modes specify how the operands of an instruction are accessed. Common modes include immediate addressing (the operand is a constant value), direct addressing (the instruction gives the memory address of the operand), indirect addressing (the address points to another address where the operand is located), and indexed addressing (effective address = base + index register). These modes impact code size and execution speed.
寻址模式规定了如何访问指令的操作数。常见模式包括立即寻址（操作数是一个常量）、直接寻址（指令给出操作数的内存地址）、间接寻址（地址指向另一个含有操作数的地址）以及变址寻址（有效地址 = 基址 + 变址寄存器）。这些模式影响代码大小和执行速度。
9. Pipelining and Parallelism | 流水线与并行处理
Pipelining allows the CPU to overlap the stages of different instructions. For example, while an instruction is being decoded, the next one can be fetched. This increases throughput without increasing clock speed. Hazards such as data dependencies can cause pipeline stalls. Parallelism also occurs at the instruction level (superscalar processors) and data level (SIMD – Single Instruction Multiple Data), all of which are relevant to understanding modern CPU performance.
流水线技术使 CPU 能将不同指令的各阶段重叠执行。例如，在一条指令译码时，下一条指令可以同时取指。这在不提高时钟频率的情况下增加了吞吐量。数据依赖等冒险情况可能引起流水线停顿。并行还体现在指令级（超标量处理器）和数据级（SIMD – 单指令多数据流），这些都是理解现代 CPU 性能的关键。
10. Comparison of CISC and RISC | CISC 与 RISC 的比较
CISC processors have a large set of complex instructions, often capable of multi‑step operations in one instruction. They use variable‑length instruction formats and require sophisticated hardware. RISC processors use a small set of simple, uniform instructions, typically executed in one clock cycle, with a load/store architecture and fixed‑length instructions. RISC designs rely on efficient pipelining and compilers, and consume less power, making them common in mobile and embedded devices.
CISC 处理器拥有大量复杂指令，常能在一个指令中完成多步操作。它们使用可变长指令格式，需要更复杂的硬件。RISC 处理器使用精简、统一的指令集，通常在一个时钟周期内执行，采用加载/存储架构和固定长指令。RISC 设计依赖高效流水线和编译器，功耗更低，因此广泛用于移动和嵌入式设备。
Published by TutorHao | Computer Science Revision Series | aleveler.com
更多咨询请联系16621398022（同微信）
屏轩国际教育cambridge primary/secondary checkpoint, cat4, ukiset,ukcat,igcse,alevel,PAT,STEP,MAT, ibdp,ap,ssat,sat,sat2课程辅导，国外大学本科硕士研究生博士课程论文辅导