Logic Gates | 逻辑门考点精讲

📚 Logic Gates | 逻辑门考点精讲

In this comprehensive revision guide for A-Level WJEC Computer Science, we cover everything you need to know about logic gates – from basic definitions to complex combinational circuits. Logic gates form the fundamental building blocks of digital electronics and understanding them is essential for the examination. We will explore truth tables, Boolean algebra, universal gates, Karnaugh maps, and practical applications such as adders.

在这份针对A-Level WJEC计算机科学的全面复习指南中，我们将涵盖你所需了解的有关逻辑门的一切内容——从基本定义到复杂的组合电路。逻辑门是数字电子技术的基本构建模块，理解它们对于考试至关重要。我们将深入探讨真值表、布尔代数、通用门、卡诺图以及加法器等实际应用。

1. Introduction to Logic Gates | 逻辑门简介

A logic gate is an elementary building block of a digital circuit. Most logic gates have two inputs and one output. At any given moment, every terminal is in one of two binary states: low (0) or high (1). The state is represented by a voltage level; in positive logic, a high voltage represents 1 and a low voltage represents 0.

逻辑门是数字电路的基本构建模块。多数逻辑门有两个输入和一个输出。在任一时刻，每个端点都处于两种二进制状态之一：低电平（0）或高电平（1）。状态由电压电平表示；在正逻辑中，高电压表示1，低电压表示0。

Logic gates are implemented using transistors, and by combining them we can build circuits that perform arithmetic, store data, and control processes. In WJEC Computer Science, you are expected to recognise standard symbols, derive truth tables, simplify Boolean expressions, and design combinational logic circuits.

逻辑门使用晶体管实现，通过组合它们我们可以构建执行算术运算、存储数据和控制进程的电路。在WJEC计算机科学中，你需要识别标准符号、推导真值表、简化布尔表达式并设计组合逻辑电路。

2. Basic Logic Gates: AND, OR, NOT | 基本逻辑门：与、或、非

The three fundamental logic gates are AND, OR, and NOT. The AND gate outputs 1 only if all inputs are 1. For a two-input AND gate, the output Y = A AND B, often written as Y = A · B or simply AB. The OR gate outputs 1 if at least one input is 1, denoted Y = A + B. The NOT gate (inverter) outputs the complement of the single input; Y = NOT A, written as Y = A’ or Y = ¬A.

三种基本逻辑门是AND（与门）、OR（或门）和NOT（非门）。AND门仅在所有输入均为1时输出1。对于两输入AND门，输出Y = A AND B，通常写作Y = A·B或简单写成AB。OR门在至少一个输入为1时输出1，表示为Y = A + B。NOT门（反相器）输出单个输入的补码；Y = NOT A，写作Y = A’ 或 Y = ¬A。

For an AND gate: input A=0 and B=0 gives output 0; A=0, B=1 gives 0; A=1, B=0 gives 0; only A=1, B=1 gives 1. For OR: 0+0=0, 0+1=1, 1+0=1, 1+1=1. NOT simply flips the input: if A=0, Y=1; if A=1, Y=0.

对于与门：输入A=0且B=0时输出0；A=0, B=1输出0；A=1, B=0输出0；只有A=1, B=1时输出1。对于或门：0+0=0, 0+1=1, 1+0=1, 1+1=1。非门直接反转输入：如果A=0, Y=1；如果A=1, Y=0。

3. Truth Tables | 真值表

A truth table lists all possible input combinations and the corresponding output for a logic circuit or gate. For n inputs, there are 2ⁿ rows. The inputs are usually listed in binary counting order. Truth tables are essential for verifying circuit behaviour and for deriving Boolean expressions.

真值表列出了逻辑电路或门的所有可能输入组合及其对应输出。对于n个输入，有2ⁿ行。输入通常按二进制计数顺序列出。真值表对于验证电路行为和推导布尔表达式是必不可少的。

Example: For a three-input AND gate (A, B, C), the output is 1 only when A=1, B=1, C=1. The truth table has 2³ = 8 rows, with output 0 for all other combinations.

示例：对于一个三输入与门（A、B、C），只有当A=1、B=1、C=1时输出为1。真值表有2³=8行，所有其他组合的输出均为0。

Row 0: 000 -> 0
Row 1: 001 -> 0
Row 2: 010 -> 0
Row 3: 011 -> 0
Row 4: 100 -> 0
Row 5: 101 -> 0
Row 6: 110 -> 0
Row 7: 111 -> 1

行0：000 -> 0
行1：001 -> 0
行2：010 -> 0
行3：011 -> 0
行4：100 -> 0
行5：101 -> 0
行6：110 -> 0
行7：111 -> 1

When constructing truth tables for any combinational circuit, start by listing all input combinations, then evaluate intermediate signals if needed, and finally determine the output column. This systematic approach helps avoid errors.

在为任何组合电路构建真值表时，首先列出所有输入组合，然后如有必要评估中间信号，最后确定输出列。这种系统方法有助于避免错误。

4. Derived Gates: NAND and NOR | 衍生门：与非和或非

NAND and NOR gates are derived by combining an AND or OR gate with a NOT gate. The NAND gate (Not AND) outputs the inverse of AND; hence output is 0 only when all inputs are 1. Its Boolean expression is Y = (AB)’. The NOR gate (Not OR) outputs 1 only when all inputs are 0; Y = (A+B)’. These gates are particularly important because they are universal gates – any logic function can be implemented using only NAND gates or only NOR gates.

NAND门和NOR门是将AND门或OR门与NOT门组合而成的衍生门。NAND门（与非门）输出AND的补码；因此只有当所有输入为1时输出为0。其布尔表达式为Y = (AB)’。NOR门（或非门）仅在所有输入为0时输出1；Y = (A+B)’。这些门特别重要，因为它们都是通用门——任何逻辑功能都可以仅用NAND门或仅用NOR门实现。

NAND truth table: A B | Y: 00->1, 01->1, 10->1, 11->0.

NAND真值表：A B | Y：00->1, 01->1, 10->1, 11->0。

NOR truth table: A B | Y: 00->1, 01->0, 10->0, 11->0.

NOR真值表：A B | Y：00->1, 01->0, 10->0, 11->0。

The bubble at the output of these symbols indicates inversion. You must be able to convert between AND-OR circuits and NAND/NOR equivalents.

这些符号输出端的圆圈表示反相。你必须能够在AND-OR电路和NAND/NOR等效电路之间进行转换。

5. Exclusive Gates: XOR and XNOR | 异或门和同或门

The XOR (Exclusive OR) gate outputs 1 when an odd number of inputs are 1. For two inputs, output is 1 if A and B are different. Its Boolean expression is Y = A’B + AB’, sometimes written as Y = A ⊕ B. The XNOR (Exclusive NOR) gate is the complement of XOR; it outputs 1 when the two inputs are equal. Y = A XNOR B = AB + A’B’ = (A ⊕ B)’.

XOR（异或）门在输入中1的个数为奇数时输出1。对于两个输入，如果A和B不同，则输出为1。其布尔表达式为Y = A’B + AB’，有时写作Y = A ⊕ B。XNOR（同或）门是XOR门的补码；当两个输入相等时输出1。Y = A XNOR B = AB + A’B’ = (A ⊕ B)’。

XOR truth table: 00->0, 01->1, 10->1, 11->0. XNOR truth table: 00->1, 01->0, 10->0, 11->1.

XOR真值表：00->0, 01->1, 10->1, 11->0。XNOR真值表：00->1, 01->0, 10->0, 11->1。

XOR gates are widely used in parity checkers and binary addition (half adder sum output). XNOR is used in equality comparators.

XOR门广泛用于奇偶校验器和二进制加法（半加器的和输出）。XNOR用于相等比较器。

6. Logic Gate Symbols and Diagrams | 逻辑门符号与电路图

You must be able to recognise and draw the standard symbols for logic gates used in WJEC. The AND gate is a D-shaped symbol with a flat left side and curved right side. The OR gate is similar but has a curved back and a pointed front. The NOT gate is a triangle with a small circle (bubble) at its output. NAND and NOR gates combine these with a bubble. XOR has an extra curved line at the inputs.

你必须能够识别并绘制WJEC使用的标准逻辑门符号。与门是一个左侧平直、右侧弯曲的D形符号。或门类似，但后部弯曲、前部尖

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Logic Gates | 逻辑门考点精讲