Combined Operations: Combinational Logic in Processor ALU | 组合操作：处理器ALU中的组合逻辑

📚 Combined Operations: Combinational Logic in Processor ALU | 组合操作：处理器ALU中的组合逻辑

In the heart of every modern processor lies the Arithmetic Logic Unit (ALU), a combinational circuit responsible for performing arithmetic and logical operations. Understanding how combinational logic design makes this possible is a fundamental skill for A-Level Computer Science, bridging transistors to computation. We will explore how simple logic gates combine to build adders and an entire ALU.

在每个现代处理器的核心，都布置着算术逻辑单元（ALU），这是一种负责执行算术与逻辑操作的组合电路。理解组合逻辑设计如何实现这一功能，是A-Level计算机科学的基础技能，它架起了晶体管与计算之间的桥梁。我们将探索如何用简单的逻辑门组合出加法器乃至完整的ALU。

1. Introduction to Combinational Logic | 组合逻辑简介

A combinational logic circuit is one whose outputs depend only on the current inputs, with no memory of past states. In contrast to sequential circuits that store data in flip-flops, combinational circuits are built from basic gates and perform instantaneous decision-making. The ALU is a prime example: for a given set of operand bits and a control signal, it produces a result immediately.

组合逻辑电路的输出仅取决于当前输入，没有对过去状态的记忆。与在触发器中存储数据的时序电路不同，组合电路由基本门电路组成，并执行即时决策。ALU就是最好的例子：对于给定的一组操作数位和控制信号，它会立刻产生结果。

2. Basic Logic Gates | 基本逻辑门

The AND, OR, and NOT gates form the foundation. An AND gate outputs 1 only if all inputs are 1; an OR gate outputs 1 if at least one input is 1; a NOT gate inverts the input. From these, we derive NAND, NOR, XOR, and XNOR gates. XOR (exclusive OR) is particularly important for arithmetic: it gives 1 when inputs differ, acting as a conditional inverter.

与门、或门、非门构成了基础。与门仅在所有输入均为1时输出1；或门在至少一个输入为1时输出1；非门对输入取反。由此可衍生出与非门、或非门、异或门和同或门。异或门（XOR）对算术尤为重要：当输入不同时它输出1，充当条件反相器。

3. Boolean Expressions and Truth Tables | 布尔表达式与真值表

Every combinational circuit can be described by a Boolean expression and a truth table. For a 2-input XOR gate, the expression is A ⊕ B and the truth table shows output 1 for inputs (0,1) and (1,0). In ALU design, multiple control signals select which Boolean function is applied to the operands, making truth tables essential for verifying behaviour.

每个组合电路都可用布尔表达式和真值表来描述。对于2输入异或门，表达式为A ⊕ B，真值表显示输入(0,1)和(1,0)时输出为1。在ALU设计中，多个控制信号选择对操作数应用何种布尔函数，因此真值表对验证行为至关重要。

4. Half Adder: Adding Two Bits | 半加器：两个比特相加

The half adder is the simplest arithmetic circuit. It takes two input bits, A and B, and produces a Sum (S) and a Carry-out (C_out). S = A ⊕ B, while C_out = A · B. It cannot accept a carry-in, so it is only suitable for the least significant bit of a multi-bit addition.

半加器是最简单的算术电路。它取两个输入比特A和B，产生和（S）与进位输出（C_out）。S = A ⊕ B，而C_out = A · B。它不能接受进位输入，因此仅适用于多比特加法的最低位。

5. Full Adder: Handling Carry-In | 全加器：处理进位输入

A full adder extends the half adder by including a carry-in (C_in). It adds three bits: A, B, and C_in. The sum output becomes S = A ⊕ B ⊕ C_in, and the carry-out is C_out = (A · B) + (C_in · (A ⊕ B)). This allows cascading adders to build multi-bit additions, with each stage’s carry-out feeding the next stage’s carry-in.

全加器通过加入进位输入（C_in）扩展了半加器。它对三个比特（A、B和C_in）进行加法。和输出变为S = A ⊕ B ⊕ C_in，进位输出为C_out = (A · B) + (C_in · (A ⊕ B))。这使得级联加法器可以构建多比特加法，每一级的进位输出馈入下一级的进位输入。

6. Ripple Carry Adder | 行波进位加法器

By connecting n full adders in series, we obtain an n-bit ripple carry adder. The carry ripples from bit 0 to bit n-1, making the worst-case delay proportional to n. Despite its speed limitation, it is simple and forms the conceptual basis for faster adders and ALU structures. In processors, carry look-ahead is often used to overcome this delay.

将n个全加器串联，就得到n位行波进位加法器。进位从第0位“波动”至第n-1位，使最坏情况延迟与n成正比。尽管存在速度限制，但它结构简单，为更快的加法器和ALU结构奠定了概念基础。在处理器中，常采用超前进位来克服这一延迟。

7. Arithmetic Logic Unit (ALU) Overview | 算术逻辑单元概览

An ALU is a combinational circuit that performs several operations on two binary operands, selected by a set of control lines. Typical operations include ADD, SUB, AND, OR, XOR, and bit-shift. The operation select lines (often labelled OP code or ALU control) determine which internal path is activated to produce the desired result.

ALU是一个组合电路，对两个二进制操作数执行多种操作，由一组控制线进行选择。典型操作包括ADD、SUB、AND、OR、XOR和位移。操作选择线（常标注为OP码或ALU控制）决定激活哪条内部路径以产生所需结果。

8. ALU Operations | ALU 操作

Subtraction is achieved by adding the two’s complement: A – B = A + (¬B + 1). Therefore, an ALU can perform subtraction using the same adder by inverting B and setting the initial carry-in to 1. Logical operations bypass the adder; for instance, an AND operation simply routes both inputs through an array of AND gates, and the OR operation uses OR gates. A multiplexer at the output selects between the arithmetic and logic results.

减法通过加补码实现：A – B = A + (¬B + 1)。因此，ALU可利用同一个加法器执行减法，只需将B取反并将初始进位设为1。逻辑操作则绕过加法器；例如，AND操作直接让两个输入通过一组与门，OR操作则采用或门。输出端的多路复用器在算术结果与逻辑结果之间进行选择。

9. Combining Adders and Logic for an ALU | 组合加法器和逻辑构建 ALU

A simplified ALU block can be built around an n-bit adder. One input to the adder can be either B or its complement, selected by a control line. Logic functions are computed by parallel gate arrays, and a final multiplexer driven by the ALU opcode picks the adder output or a logic output. For example, a 4-bit ALU might have a 3-bit control word: one bit to invert B, one to set carry-in, and one to choose between arithmetic and logic outputs.

一个简化的ALU模块可围绕n位加法器构建。加法器的一个输入可以是B本身或其补码，由控制线选择。逻辑功能由并行门阵列计算，而由ALU操作码驱动的最终多路复用器选取加法器输出或逻辑输出。例如，一个4位ALU可能拥有3位控制字：一位用于取反B，一位用于设置进位输入，还有一位用于在算术和逻辑输出之间选择。

10. Flags: Carry, Zero, Overflow, Negative | 标志位：进位、零、溢出、负

Many ALU designs also output status flags that influence program flow. The carry flag signals a carry or borrow out of the most significant bit. The zero flag is set when all result bits are 0. The overflow flag detects signed arithmetic overflow (e.g., adding two positive numbers producing a negative result). The negative flag simply copies the most significant bit of the result to indicate sign.

很多ALU设计还会输出影响程序流程的状态标志。进位标志指示最高有效位是否有进位或借位。当所有结果位均为0时，零标志置位。溢出标志检测有符号运算溢出（例如，两个正数相加却产生负数）。负标志简单复制结果的最高有效位以指示符号。

11. Applications in Processor Design | 在处理器设计中的应用

In a typical CPU architecture, the ALU forms the execution stage, receiving operands from registers and writing results back. The control unit decodes instructions and asserts the appropriate ALU control signals. Pipelined processors may have separate ALU units for integer arithmetic, logic, and floating-point operations, but the underlying combinational design principles remain the same.

在典型的CPU架构中，ALU构成执行阶段，它从寄存器接收操作数并将结果写回。控制单元对指令进行译码并发出相应的ALU控制信号。流水线处理器可能为整数算术、逻辑和浮点运算设有独立的ALU单元，但底层的组合设计原理保持不变。

12. Summary | 总结

Combinational logic is the bedrock of processor arithmetic. From basic gates to full adders and ALUs, each layer builds upon the last to deliver the operations that drive all digital computing. Mastering these concepts gives you insight into how programming instructions translate into hardware actions, a core goal of the A-Level Edexcel Computer Science specification.

组合逻辑是处理器算术的基石。从基本门到全加器再到ALU，每一层都承上启下，实现驱动所有数字计算的操作。掌握这些概念将使你洞悉编程指令如何转化为硬件动作，这正是A-Level Edexcel计算机科学课程的核心目标。

Published by TutorHao | Computer Science Revision Series | aleveler.com

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