📚 CIE AS and A Level Computing Core Revision Guide | CIE AS及A Level计算核心复习指南
This revision guide distils the most examinable ideas from the CIE AS and A Level Computing syllabus, using the Leadbetter, Blackford and Piper coursebook as a framework. It focuses on data representation, hardware, software, networking, databases, logic, algorithms and the system life cycle.
本复习指南以 Leadbetter、Blackford 和 Piper 编写的教材为框架，提炼 CIE AS 及 A Level 计算课程中最常考的核心概念，涵盖数据表示、硬件、软件、网络、数据库、逻辑、算法和系统生命周期。
1. Data Representation: Binary, Hex and Two’s Complement | 数据表示：二进制、十六进制与补码
Computers store all data as binary digits, or bits. In the Cambridge International Computing course you must be able to convert between denary, binary and hexadecimal, and explain why hex is used as a shorthand for binary.
计算机以二进制数字（比特）存储所有数据。在剑桥国际计算课程中，你必须能够在十进制、二进制和十六进制之间进行转换，并解释为什么十六进制被用作二进制的简写形式。
Negative integers are commonly represented by two’s complement. For an 8-bit number, the most significant bit has a negative place value of -128. For example, -1 is stored as 11111111.
负整数通常用补码表示。对于 8 位数字，最高有效位的权值为负，即 -128。例如，-1 存储为 11111111。
(-1)₁₀ = 11111111₂ (8-bit two’s complement)
Floating-point representation stores a mantissa and an exponent. Increasing the exponent increases range but may reduce precision because fewer bits remain for the mantissa.
浮点表示存储尾数和指数。增大指数会扩大表示范围，但可能会降低精度，因为留给尾数的位数会减少。
2. Processor Architecture and the Fetch-Execute Cycle | 处理器结构与取指-执行周期
The von Neumann architecture stores both instructions and data in the same memory. The processor repeatedly follows the fetch-decode-execute cycle.
冯·诺依曼体系结构将指令和数据存储在同一个内存中。处理器反复执行取指-解码-执行周期。
Key registers include the program counter (PC), memory address register (MAR), memory data register (MDR), current instruction register (CIR) and accumulator (ACC). The PC holds the address of the next instruction; the MAR sends an address to memory; the MDR holds data moving to or from memory; the CIR holds the current instruction; the ACC stores results.
关键寄存器包括程序计数器（PC）、存储器地址寄存器（MAR）、存储器数据寄存器（MDR）、当前指令寄存器（CIR）和累加器（ACC）。PC 存放下一条指令的地址；MAR 向内存发送地址；MDR 存放进出内存的数据；CIR 存放当前指令；ACC 存储运算结果。
During the fetch phase, the address in the PC is copied to the MAR and the PC is incremented. The instruction is read into the MDR and then transferred to the CIR. In the decode phase, the control unit interprets the opcode and addressing mode. In the execute phase, the relevant operation is carried out, often using the ALU.
在取指阶段，PC 中的地址被复制到 MAR，然后 PC 递增。指令被读入 MDR，再传送到 CIR。在解码阶段，控制单元解释操作码和寻址方式。在执行阶段，相关操作被执行，通常使用算术逻辑单元 ALU。
3. Assembly Language and Addressing Modes | 汇编语言与寻址方式
Assembly language uses mnemonics such as LDA, STA, ADD and JMP instead of raw binary opcodes. An assembler translates assembly code into machine code.
汇编语言使用助记符（如 LDA、STA、ADD 和 JMP）代替原始二进制操作码。汇编器将汇编代码翻译成机器代码。
Addressing modes determine where an operand is located. Immediate addressing uses the value in the instruction itself; direct addressing gives the memory address of the operand; indirect addressing gives the address of the address containing the operand; indexed addressing adds a base register value to an offset.
寻址方式决定操作数的位置。立即寻址使用指令本身中的数值；直接寻址给出操作数的内存地址；间接寻址给出存放操作数地址的地址；变址寻址将基址寄存器的值加上偏移量。
| Addressing mode | Meaning |
| Immediate | Operand is the value in the instruction |
| Direct | Instruction holds the memory address of the operand |
| Indirect | Instruction holds address of a location that holds the operand address |
| Indexed | Operand address = index register + offset |
In exam questions you may be asked to identify the addressing mode from a short piece of assembly code, or to explain why indexed addressing is useful for accessing arrays.
在考试题目中，你可能会被要求从一段简短的汇编代码中识别寻址方式，或者解释为什么变址寻址对访问数组很有用。
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